Read-only memory employing striplines
阅读：472发布：2023-01-04
专利汇可以提供Read-only memory employing striplines专利检索，专利查询，专利分析的服务。并且A read-only memory apparatus is described employing a plurality of stripline-type transmission lines. The input and output transmission lines are formed by signal conductors provided on the opposite sides of a common ground plane conductor. A plurality of openings are provided through the common ground plane at some of the intersections of the input and output signal conductors and such openings are positioned to produce a digitally coded output signal on the output signal conductors when an input signal applied to the input signal conductors crosses such openings.，下面是Read-only memory employing striplines专利的具体信息内容。
1. A permanent read-only memory apparatus of unitary construction, comprising: a fixed common ground plane conductor formed by a sheet of electrically conductive material having a plurality of openings therethrough positioned in a stored information code; first transmission line means including a plurality of first signal conductors extending in substantially parallel-shaped relationship to said ground plane conductor to form therewith a plurality of first transmission lines of uniform characteristic impedance; second transmission line means including at least one second signal conductor extending in a substantially parallel spaced relationship to said ground plane conductor to form therewith a second transmission line, and having said second signal conductor positioned on the opposite side of the ground plane conductor from said first signal conductors so that the ground plane conductor extends as a shield between the first and second signal conductors; and support means for electrically insulating said first signal conductors and said second signal conductor from each other and from said ground plane conductor and for supporting said first and second signal conductors and said ground plane conductor as a unitary structure, said second signal conductor having portions extending across said first conductors at a plurality of intersections at least some of which are in alignment with the openings in said ground plane conductor so that an input signal pulse transmitted through said second signal conductor causes an output pulse to be produced on the first signal conductors each time such input pulse is transmitted across one of said openings.
2. A memory apparatus in accordance with claim 1 in which the first transmission line means includes a plurality of first termination resistors each connected between ground and one end of a different one of said first signal conductors, and having a resistance equal to the characteristic impedance of the first transmission line, each of said first transmission lines having only one signal conductor.
3. A memory apparatus in accordance with claim 2 in which the second transmission line means includes a second termination resistor connected between ground and one end of the second signal conductor, and having a resistance equal to the characteristic impedance of the second transmission line.
4. A memory apparatus in accordance with claim 1 in which the openings in the ground plane conductor are positioned to produce a digitally coded output signal on the first signal conductors.
5. A memory apparatus in accordance with claim 1 in which the second transmission line means includes a plurality of second signal conductors forming a plurality of second transmission lines with said ground plane conductor, each of said second signal conductors crossing all of said first signal conductors at a plurality of intersections at least some of which are aligned with the opEnings in the ground plane conductor.
6. A memory apparatus in accordance with claim 5 which also includes a series input signal means for applying an input signal pulse to one of the second signal conductors and producing a plurality of output pulses on different ones of said first signal conductors to form a parallel output signal.
7. A memory apparatus in accordance with claim 5 which also includes a parallel input signal means for applying a plurality of sequentially timed input pulses to the second signal conductors and producing a plurality of output pulses on at least one of the first signal conductors which form a series output signal.
8. A memory apparatus in accordance with claim 1 in which only one second signal conductor is employed and crosses each of the first signal conductors at a plurality of intersections at least some of which are aligned with said openings.
9. A memory apparatus in accordance with claim 8 which also includes an input signal means for applying an input pulse to one end of the second signal conductor and producing a plurality of output pulses on each first signal conductor to form a series output signal, said output pulses being spaced from each other by the time delays of the second transmission line corresponding to the lengths of the portions of said second line extending between the openings aligned with the first signal conductor on which the series output signal is produced.
10. A memory apparatus in accordance with claim 8 in which the second signal conductor is wrapped in a spiral path about a second ground plane and insulatingly spaced therefrom to form a delay line on the opposite side of the ground plane conductor from the first conductors.
11. A memory apparatus in accordance with claim 10 in which the second signal conductor is connected to ground at its output end through a termination resistor equal to the characteristic impedance of the second transmission line, and the delay line has the same characteristic impedance as said second transmission line.
12. A memory apparatus in accordance with claim 1 in which the insulation means includes at least two layers of insulating material provided on opposite sides of a layer of metal forming the ground plane conductor, and the first and second signal conductors are strips of metal provided on the outer surfaces of said insulating layers.
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