We claim:1. In an internal combustion engine having an intake system, an exhaust system, an engine block, a plurality of cylinders disposed in said engine block, a piston mounted for reciprocal movement within each of said plurality of cylinders, means responsive to the generation of one or more control signals for controlling the supply of fuel to a selected one or more of said plurality of cylinders of said engine and the ignition thereof, the improvement comprising:a microprocessor including memory means for storing a program for implementing one or more control laws, said microprocessor being responsive to one or more engine-operating parameters for implementing said control laws and computing one or more of said control signals;means for sensing one or more of said engine-operating parameters and generating corresponding analog signals indicative of the measured value thereof;analog-to-digital converter means for converting a selected one of said analog signals into a corresponding binary data word indicative thereof, said microprocessor system being responsive to one or more of said binary data words for implementing said control laws and computing said control signals;said analog-to-digital converter means including a ramp-type analog to digital converter and a binary counter for operating said binary counter so long as a generated ramp signal does not exceed the value of said analog signal, window means for enabling said counter to continue counting even if said analog input signal momentarily drops below the value of said generated ramp voltage due to noise or the like, said window counter including multiple count detects associated with the output thereof, and means for storing a microprocessor-generated data bit for selecting either an "n" bit or a "m" bit conversion, where "m" is greater than "n", thereby extending the range of said converter and enabling it to perform both "n" and "m" bit conversions depending on the conversion time.2. In an A/D conversion system wherein an analog input signal is compared with a ramp signal to produce a pulse-width signal indicative of the value of said analog input signal and wherein a binary counter counts clock pulses during the duration of said pulse-width signal to produce a digital count indicative of the value of said analog input signal an improved ramp signal generating system comprising current source means, a ramp capacitor coupled between said current source means and ground, said ramp capacitor means being responsive to charging current from said current source means for generating a ramp signal, reset means for initially discharging said ramp capacitor and establishing a predetermined initial reference voltage thereon from which to begin the generation of said ramp signal and hence a subsequent conversion operation, counter means, decoder means coupled to the output of said counter means and responsive to one or more predetermined counts attained therein for generating a corresponding one or more count decode signals indicative of said attained predetermined counts, said reset means being responsive to one of said count decode signals for initiating the discharging of said ramp capacitor and the beginning of said conversion operation, a feedback comparator having first and second inputs and a comparator output, said first comparator input being operatively coupled to said ramp capacitor to receive said generated ramp signal, means operatively coupled to said second input of said feedback comparator for establishing a reference voltage indicative of the desired voltage level said generated ramp signal should have reached at the time of attainment of another predetermined one of said counts, the output of said feedback comparator generating a pulse-width signal which begins with the generation of said ramp voltage and ends when said ramp voltage becomes equal to said reference voltage level such that the pulse-width duration of said feedback comparator output signal is proportional to the error in the rate of generation of said ramp signal, logical gating means operatively coupled to the output of said feedback comparator and responsive to another one of said count decode signals indicative of the attainment of said another predetermined one of said counts and to the output of said feedback comparator for generating a feedback correction signal indicative of ramp rate error, the improvement comprising:means for generating one of at least a first conversion command signal requesting an "m" bit conversion and a second conversion command signal requesting an "n" bit conversion where m is greater than n and where the number of bits to be converted depends on the conversion time available and determines the accuracy of the conversion process, andmultiple decoding means associated with said decoder means and responsive to said one of at least first and second conversion command signals for selectively controlling the number of bit positions utilized in said binary counter for said pulse-width-to-binary conversion thereby selectively extending the range of values over which said A/D converter may be used while optimizing the accuracy of the resulting conversions.3. The improved A/D converter system of claim 2 further including window counting means for defining a predetermined noise immunity count duration window during which said pulse-width-to-binary counter will resume counting even though said counting was temporarily stopped due to transient noise signals causing the value of said generated ramp signal to be erroneously and momentarily greater than the value of said analog input signal being converted and wherein said multiple decoding means is further responsive to said selected first or second conversion command signals for selectively controlling the size of said noise immunity window to insure conversion accuracy and prevent erroneous readings.4. The improved A/D converter system of claim 3 wherein said window counter means includes a window counter having enough stages to enable said window counter to count the entire period of said count duration window for said "m" bit conversion when all "m" bit positions of said pulse-width-to-binary counter are utilized for optimal conversion accuracy.5. The improved A/D converter system of claim 3 further including computer means, memory means associated with said computer means, program means stored within said memory means for implementing various computational functions, control laws, and the like, said computer means executing said program means for calculating which of said first and second conversion command signals are to be generated, and means for temporarily storing one of said first and second converter command signals for controllably selecting the use of all "m" bit positions in said pulse-width-to-binary counter of said converter when the time available for the conversion is relatively long for optimal conversion accuracy or only "n" bit positions of said pulse-width-to-binary counter of said converter when the time available for conversion is relatively short for optimal conversion accuracy.6. In an A/D converter system wherein an analog input signal is compared with a generated ramp voltage signal to produce a pulse-width signal indicative of the value of said analog input signal and wherein a pulse-width-to-binary counter having "m" bit positions counts clock pulses during the duration of said pulse-width signal to accumulate a binary count indicative of the value of said analog input signal within said counter upon the termination of said pulse-width signal, current source means, a ramp capacitor coupled between said current source means and ground, said ramp capacitor means being responsive to charging current from said current source for accumulating a charge to generate a ramp voltage signal, reset means for initially discharging said ramp capacitor, and establishing a predetermined initial reference voltage thereon from which all conversions begin, second counter means, decoder means coupled to the output of said second counter means for detecting one or more predetermined counts attained therein and generating a corresponding one or more count decode signals in response thereto, said reset means being responsive to one of said count decode signals for initiating said conversion process, a feedback comparator having first and second inputs and a feedback comparator output, said first input of said feedback comparator being operatively coupled to said ramp capacitor for receiving said generated ramp voltage signal, means operatively coupled to said second input of said feedback comparator for generating a reference voltage indicative of the desired voltage level which said ramp voltage signal should have reached at the time of attainment of another predetermined one of the counts attained in said second counter means, the output of said feedback comparator generating a pulse-width signal beginning with the initial charging of said ramp capacitor and ending when the value of said ramp voltage signal is equal to the value of said established reference voltage, logical gating means operatively coupled to the output of said feedback comparator and responsive to another one of said predetermined count decode signals indicative of the attainment of said another predetermined one of said counts attained in said second counter means for generating a feedback correction signal indicative of ramp rate error, means responsive to said signal indicative of ramp rate error for selectively controlling the operation of said current source means to charge said ramp capacitor and therefore selectively varying the rate of generation of said ramp voltage signal for correcting same, a computer-based control system including computer means, memory means, and program means stored within said memory means for implementing one or more control laws and various computational sequences, the improvement comprising:said computer means executing said program means for generating a first conversion command signal requesting an "m" bit conversion and a second conversion command signal requesting an "n" bit conversion where m is greater than n and where the greater the number of bit positions within said pulse-width-to-binary counter, the greater the time required for the conversion;window counter means for defining a predetermined noise immunity count duration window period during which said pulse-width-to-binary counter resumes counting even though said counting was temporarily stopped due to transient noise signals or the like causing the value of said generated ramp voltage signal to be erroneously greater than the value of said analog input signal being converted;means for temporarily storing the program-generated one of said first and second conversion command signals; andmultiple decoding means responsive to said stored conversion command signal for selecting all "m" bit positions of said pulse-width-to-binary counter and for selectively controlling and maximizing the size of said defined window period for a greater accuracy conversion and for selecting only "n" bits of said pulse-width-to-binary counter and for selectively decreasing the size of said defined window period for increasing the accuracy of said conversion so that the range of values over which said A/D conversion may be used and the accuracy of the resulting conversions may be optimized depending upon the nature of said analog input signal and the conversion time available.7. In an A/D converter system wherein an analog input signal to be converted into a binary number indicative of the value thereof is generated by comparing the analog input signal against a voltage ramp signal generated at a predetermined rate established by the charging rate of a ramp capacitor to output a pulse-width signal indicative of the value of said analog input signal and a multiple stage pulse-width-to-binary counter is enabled to count clock pulses during the duration of said pulse-width output signal such that the binary number stored in said pulse-width-to-binary counter at the termination of said pulse-width output signal is a highly accurate digital representation of the value of said analog input signal, a closed loop self-correcting feedback method for automatically compensating the rate of generation of said ramp voltage signal for capacitive leakage, variations in circuit parameters with temperature, age, fluctuations and power supply voltage, including the steps of (a) initially discharging said ramp capacitor to begin the generation of said ramp voltage signal at a predetermined initial reference level from which each and every conversion cycle is begun, (b) counting at a fixed rate during the charging of said ramp capacitor, (c) comparing the generated ramp voltage signal with an established reference voltage indicative of a desired value of voltage which said ramp voltage signal should have attained when said counting step indicates that a predetermined particular count has been attained, (d) generating a feedback correction signal indicative of the difference between the time the value of said ramp voltage signal reaches the value of said voltage reference and the time of attainment of said predetermined count, and (e) correcting the charging rate of said ramp capacitor for selectively varying the rate of generation of said ramp voltage signal in response to said feedback correction signal, the improvement comprising the steps of: (f) selecting all of the stages of said pulse-width-to-binary counter for use in said conversion process to achieve optimal conversion accuracy when a relatively long conversion time is available or selecting less than all of the stages of said pulse-width-to-binary counter to achieve optimal conversion accuracy when a relatively shorter conversion time is available.8. The method of claim 7 further including the steps of counting clock pulses to establish a noise immunity window having a given count duration period to provide noise immunity so that said pulse-width-to-binary counter may automatically resume counting even though said counting was temporarily interrupted due to transient noise signals causing the value of said generated ramp voltage signal to be erroneously greater than the value of said analog input signal being converted, the count duration period of said window normally being greater than the maximum count time of said pulse-width-to-binary counter when all of the stages of said multiple stage binary counter are selected for the conversion process, and selectively increasing or decreasing the count duration period of said window to provide said noise immunity regardless of the number of stages chosen to be used in said pulse-width-to-binary counter.9. A switchable range analog-to-digital converter system including a ramp-type A/D converter for converting an analog input signal into a binary number indicative of the value thereof, window counter means for defining a predetermined count duration noise immunity window and enabling said binary counter to operate throughout the period defined by said noise immunity window even if transient noise signals make it temporarily appear that the value of the ramp voltage is greater than the value of the analog input signal to temporarily discontinue the operation of the conversion process, and multiple count detection means associated with the output of said window counter for selectively extending the range of said converter system between at least first and second different and distinct multi-bit conversion accuracies, and means for storing a signal for selecting either a first or a second multi-bit converter mode of operation.