专利汇可以提供REDUCED S/D CONTACT RESISTANCE OF III-V MOSFET USING LOW TEMPERATURE METAL-INDUCED CRYSTALLIZATION OF n+ Ge专利检索,专利查询,专利分析的服务。并且Embodiments of this invention provide a method to fabricate an electrical contact. The method includes providing a substrate of a compound Group III-V semiconductor material having at least one electrically conducting doped region adjacent to a surface of the substrate. The method further includes fabricating the electrical contact to the at least one electrically conducting doped region by depositing a single crystal layer of germanium over the surface of the substrate so as to at least partially overlie the at least one electrically conducting doped region, converting the single crystal layer of germanium into a layer of amorphous germanium by implanting a dopant, forming a metal layer over exposed surfaces of the amorphous germanium layer, and performing a metal-induced crystallization (MIC) process on the amorphous germanium layer having the overlying metal layer to convert the amorphous germanium layer to a crystalline germanium layer and to activate the implanted dopant. The electrical contact can be a source or a drain contact of a transistor.,下面是REDUCED S/D CONTACT RESISTANCE OF III-V MOSFET USING LOW TEMPERATURE METAL-INDUCED CRYSTALLIZATION OF n+ Ge专利的具体信息内容。
What is claimed is:
The exemplary embodiments of this invention relate generally to semiconductor devices and to procedures to fabricate semiconductor devices and, more specifically, relate to transistors, such as MOSFETs, comprised of Group III-V semiconductor material having amorphous Germanium contacts.
The use of metal-induced dopant activation (MIDA) in amorphous Germanium (α-Ge) (Germanium is a Group IV element) is a known process. For example, reference can be made to Jin-Hong Park, M. Tada, D. Kuzum, P. Kapur, H-.Y. Yu, H-.S. Philip Wong, and K. C. Saraswat, “Low Temperature (≦380° C.) and High Performance Ge CMOS Technology with Novel Source/Drain by Metal-Induced Dopants Activation and High-K/Metal Gate Stack for Monolithic 3D Integration,” IEEE International Electron Devices Meeting (IEDM) 2008 Technical Digest, pp. 389-392, San Francisco, Calif., Dec. 15-17, 2008; and Jin-Hong Park, D. Kuzum, M. Tada and K. C. Saraswat, “High Performance Germanium N+/P and P30/N junction diodes formed at Low Temperature (<380° C.) using Metal-Induced Dopant Activation”, Applied Physics Letters 93, 193507 (2008). Reference can also be made to Jin-Hong Park, M. Tada, Woo-Shik Jung, H-.S. Philip Wong, and K. C. Saraswat, “Metal-induced dopant (boron and phosphorus) activation process in amorphous germanium for monolithic three-dimensional integration”, Journal of Applied Physics 106, 074510 (2009).
A problem that arises when considering the fabrication of transistors using a Group III-V compound semiconductor (composed of elements from Group III and Group V of the periodic table of elements) is that due at least to a reliable silicide process, the self-aligned integration of a Group III-V transistor (e.g., a metal oxide semiconductor field effect transistor or MOSFET) is difficult to accomplish. This difficulty can affect the ability to fabricate low resistance electrical contacts to the source and drain regions of the transistor.
The foregoing and other problems are overcome, and other advantages are realized, in accordance with the exemplary embodiments of this invention.
In one aspect thereof the embodiments of this invention provide a method to fabricate an electrical contact, comprising providing a substrate comprised of a compound Group III-V semiconductor material having at least one electrically conducting doped region adjacent to a surface of the substrate; and fabricating the electrical contact to the at least one electrically conducting doped region by depositing a single crystal layer of germanium over the surface of the substrate so as to at least partially overlie the at least one electrically conducting doped region, converting the single crystal layer of germanium into a layer of amorphous germanium by implanting a dopant, forming a metal layer over exposed surfaces of the amorphous germanium layer, and performing a metal-induced crystallization (MIC) process on the amorphous germanium layer having the overlying metal layer to convert the amorphous germanium layer to a crystalline germanium layer and to activate the implanted dopant.
In another aspect thereof the embodiments of this invention provide a method to fabricate a semiconductor device, comprising providing a Group III-V substrate having a source region and a drain region that are spaced apart adjacent to a surface of the substrate and that define a channel there between, and disposed over the channel a gate stack structure contained within a dielectric material; and fabricating a source contact and a drain contact by selectively depositing a single crystal layer of germanium over the surface of the substrate so as to overlie the source region and the drain region but not the dielectric material, implanting the crystalline layer of germanium with a dopant and converting the crystalline layer of germanium to a doped amorphous germanium layer, forming an overlying metal layer over exposed surfaces of the doped amorphous germanium layer, applying heat to convert the amorphous germanium layer having the overlying metal layer to a crystalline germanium layer and to activate the implanted dopant, and removing the overlying metal layer and the underlying dielectric material from the gate stack structure so as leave a source spacer between the crystalline germanium layer that overlies the source region and a drain spacer between the crystalline germanium layer that overlies the drain region.
In a further aspect thereof the embodiments of this invention provide a transistor that comprises a compound Group III-V substrate having a source region and a drain region that are spaced apart adjacent to a surface of the substrate and that define a channel there between; a gate stack structure disposed over the channel; electrically insulating source and drain spacers disposed at least partially over the source and drain regions, respectively, and abutting the gate stack structure; and a source contact and a drain contact at least partially overlying the source region and the drain region, respectively, and separated from the gate stack structure by the source and drain spacers, respectively, said source and drain contacts each comprised of a layer of crystalline doped germanium having an overlying layer of metal.
This aspect of the invention thus selectively grows Ge on a III-V substrate patterned with, for example, SiOx, SiNx or Al2O3. While it is possible that there may be some minor nucleation of Ge on the dielectric surface as well this can be inhibited by, for example, increasing the growth temperature or by introducing HCl gas during the Ge growth in CVD.
It should be realized that the embodiments of this invention may be implemented by using materials other than those expressly mentioned above, and/or by using different material thicknesses, and/or by using different temperatures and times, and/or by using different dopant concentrations and ion implant species (e.g., Boron) and implant parameters. For example, in other embodiments a metal such as Al may be used instead of Ni or Co, with corresponding adjustments made to MIC temperatures and times so as to achieve the desired crystalline grain size and dopant activation. Reference in this regard can be made to, for example, Shu Hu, Ann F. Marshall, and Paul C. McIntyre, “Interface-controlled layer exchange in metal-induced crystallization of germanium thin films”, Applied Physics Letters 97, 082104 (2010). These authors report metal (Al)-induced crystallization to form poly-Ge thin films on glass and polymer substrates. To avoid a disordered mixture of Al and crystalline Ge the α-Ge surface is intentionally oxidized by flowing ozone gas at room temperature to form a very thin GeOx layer prior to Al deposition, followed by an anneal of the bilayers in vacuum at 250° C. for one hour. The same or a similar procedure can be used during fabrication of the final transistor structure shown in
Further by example, in other embodiments a transistor having p+ source and drain regions 12 and 14 may be formed, and in still other embodiments the electronic device that is fabricated to have improved contacts may be other than a transistor (e.g., a light-emitting or a photodiode or a solar cell).
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiment was chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated.
As such, various modifications and adaptations may become apparent to those skilled in the relevant arts in view of the foregoing description, when read in conjunction with the accompanying drawings and the appended claims. As but a few some examples, and as was indicated previously, the use of other similar or equivalent semiconductor materials, dopants, etchants, process chambers and the like may be used by those skilled in the art. However, all such and similar modifications of the teachings of this invention will still fall within the scope of this invention.
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