专利汇可以提供Speed controller专利检索,专利查询,专利分析的服务。并且PURPOSE: To suppress influence of the duty ratio of FG pulse by averaging the value during preceding interval between edge signals stored in a memory means and the current count between edge detection signals counted through a counting means then providing the averaged output signal, as an error signal, to a rotary body.
CONSTITUTION: A speed detection value is held, synchronously with a trigger pulse 1, in a latch circuit 14. Then thus held data and the data stored at a memory section 15, i.e., a previously detected speed, are inputted into an adder 16 synchronously with a trigger pulse 2 having phase lag. The adder 16 performs adding/averaging operation for the previously detected speed and current speed detected through a speed detector. Then data stored in the latch 14 are transferred, synchronously with a trigger pulse 3, to a memory section 15. Finally, an averaged speed detection value is transferred, synchronously with a pulse 4, to a latch circuit 17. A D/A converter 18 converts the averaged speed detection value into an analog signal which is then fed as an error signal.
COPYRIGHT: (C)1990,JPO&Japio,下面是Speed controller专利的具体信息内容。
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