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Watchdog timer circuit

阅读:237发布:2021-09-11

专利汇可以提供Watchdog timer circuit专利检索,专利查询,专利分析的服务。并且PURPOSE: To reduce greatly the possibility of an erroneous decision to device a faulty state as a normal state and to improve the reliability for a watchdog timer circuit, by deciding as faulty the execution state of a program if a CPU does not write the prescribed data of plural bits into a register.
CONSTITUTION: In a normal execution state of program, the prescribed data of plural bits is written to a register 60 every prescribed cycle time T. The comparison output 71 of a comparator 70 repeats coincidence discordance every time T and supplies the pulse output which repeats 1 and 0 alternately to a counter 80. The counter 80 counts clock pulse 91 and delivers a carry output 81 when a prescribed time T' elapses. This output 81 resets a CPU20. If the program execution is faulty, the output 71 is fixed at 1 or 0. Then the CPU20 is reset when the time T' elapses from the final rise. The program is executed again after the reset state is released.
COPYRIGHT: (C)1984,JPO&Japio,下面是Watchdog timer circuit专利的具体信息内容。

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