Method in microcircuit package assembly providing nonabrasive, electrically passive edges on integrated circuit chips
阅读：551发布：2023-12-10
专利汇可以提供Method in microcircuit package assembly providing nonabrasive, electrically passive edges on integrated circuit chips专利检索，专利查询，专利分析的服务。并且A channel is formed in the kerf area of an integrated circuit wafer prior to forming a passivating or protective layer of material on the surface of the wafer. The passivated channel, after separation of the wafer into chips, forms conditioned edges which prevent shorting of interconnecting leads.，下面是Method in microcircuit package assembly providing nonabrasive, electrically passive edges on integrated circuit chips专利的具体信息内容。
1. An improved method in microelectronic circuit fabrication and assembly providing nonabrasive electrically passive edges on face-up mounted chips, the improvement comprising the steps of: forming a channel in a kerf area on an active surface of a wafer of semiconductor material; depositing a layer of passivating material on the active surface of the wafer, the layer covering the channel formed in the previous step; separating the wafer into individual chips along the centerline of the channel, the separating kerf having a width substantially less than the width of the channel, the remaining portions of the bisected channel forming chamfered, passivated edges on each of the separated chips; attaching a lead to a contact pad of one of the individual chips, the lead being free cantilevered over the remaining channel portion of the chip; attaching the one chip face-up to one surface of a planiform insulator, the lead aligned over an external circuit formed on the one surface; and forcing the cantilevered lead toward the external circuit to make electrical contact therewith, the chamfered passivated edge reducing the probability of electrical shorts between the lead and the semiconductor material of the chip.
2. An improved method in microcircuit fabrication and assembly providing nonabrasive electrically passive edges on face-up mounted chips, the improvement comprising the steps of: forming a channel in a kerf area on an active surface of a wafer of semiconductor material; depositing a layer of passivating material on the surface of the wafer, the layer covering the channel formed in the previous step; attaching a lead to a contact pad on the active surface, the lead freely extending in a cantilevered fashion over the channel; separating the wafer into individual chips along the centerline of the channel, the separating kerf having a width substantially less than the width of the channel, the remaining portions of the bisected channel forming chamfered, passivated edges on the chips; attaching the chip having the lead face-up to one surface of a planiform insulator, the lead aligned over an external circuit formed on the one surface; and forcing the cantilevered lead toward the external circuit to make electrical contact therewith, the chamfered passivated edge reducing the probability of electrical shorts between the lead and the semiconductor material of the chip.
3. An improved method in microcircuit fabrication and assembly providing nonabrasive electrically passive edges on face-up mounted integrated circuit dice, the improvement comprising the steps of: forming a channel in a kerf area on an active surface of a wafer of semiconductor material, after circuits have been formed on the active surface of the wafer but prior to final wafer passivation; depositing a layer of passivating material on the active surface of the wafer, the layer covering the channel formed in the previous step; dicing the wafer along the centerline of the channel, the separating kerf having a width substantially less than the width of the channel, the remaining portions of the bisected channel forming chamfered, passivated edges on each of the dice; attaching a lead to a contact pad of at least one of the circuits, the lead freely extending in cantilevered fashion over the remaining channel portion of the die; attaching the die having the lead attached thereto to one surface of a planar substrate having an external circuit formed thereon, the plane of the lead separated from the plane of the external circuit by the thickness of the die, the lead aligned over the external circuit; and forcing the extended portion of the lead toward the external circuit to make electrical contact therewith, the chamfered passivated edge reducing the probability of electrical shorts between the lead and the semiconductor material of the die.
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