Data bus transmission line termination circuit
阅读：408发布：2023-12-16
专利汇可以提供Data bus transmission line termination circuit专利检索，专利查询，专利分析的服务。并且A data bus transmission line termination circuit for connection either to the terminal end of a data bus or to an intermediate portion of the bus. The circuit is programmable to either a lowimpedance state for connection to the terminal end of the data bus so as to provide an optimum terminating load for the bus, or to a high-impedance state for connection to an intermediate portion of the data bus so as not to load down the latter when so connected. The termination circuit is preferably formed on the same integrated circuit chip as the receiver circuit so as to be located adjacent the effective end of the total transmission line including the portion extending from the data bus proper through the connections and conductors of the board, card, module and chip to the receiver circuit on the chip.，下面是Data bus transmission line termination circuit专利的具体信息内容。
1. A transmission line circuit comprising a data output source, a transmission line data bus connected to said source, a terminal receiver circuit connected to a terminal end of said bus, at least one intermediate receiver circuit connected to said bus intermediate said source and said terminal end, a plurality of impedance means, each being switchable to either a first state wherein said impedance means has a predetermined impedance or to a second state wherein said impedance means has an impedance substantially higher than said predetermined impedance, and signal responsive means connected to each of said impedance means for selectively switching said impedance means either said first or said second state, one of said plurality of impedance means being switched to said first state and connected to said terminal end of said bus, and at least one of said plurality of impedance means being switched to second state and connected to said bus proximate the point of connection of said intermediate receiver circuit.
2. The transmission line circuit of claim 1 wherein said impedance means connected to the bus are connected in parallel with said receiver circuits.
3. A circuit as set forth in claim 1 wherein each of said plurality of impedance means comprises an impedance element biased either to a conductive state to provide said predetermined impedance or to a substantially nonconductive state to provide said higher impedance.
4. A circuit as set forth in claim 2 wherein said signal responsive means comprises means for biasing said impedance element either to said conductive state or to said substantially nonconductive state.
5. A circuit as set forth in claim 2 wherein said impedance element comprises a diode.
6. A circuit as set forth in claim 2 wherein said impedance means comprises a substantially constant current source, said impedance element and said current source being connected in series.
7. A circuit as set forth in claim 2 wherein said impedance means further comprises a transistor having an electrode, said electrode and said impedance element being connected to said transmission line data bus.
8. A circuit as set forth in claim 7 wherein said transistor electrode is the emitter electrode of a bipolar transistor.
9. A circuit as set forth in claim 8 wherein said impedance element is a bipolar transistor having a collector and a base both connected to said data bus.
10. A circuit as set forth in claim 1 wherein said impedance means comprises a current switch including a source of substantially constant current and two alternate network branches connected to said source, said signal responsive means including means to selectively switch said substantially constant current to either one of said two alternate network branches, said impedance means being connected to one of said two alternate network branches.
11. A circuit as set forth in claim 10 wherein said current switch comprises a diode and a transistor, said diode having a first electrode connected to said data bus and a second electrode connected to said current source, said transistor having an electrode connected to said current source.
12. A circuit s set forth in claim 11 wherein said transistor electrode is the emitter electrode of a bipolar transistor.
13. A circuit as set forth in claim 11 wherein said transistor electrode is the source electrode of a field-effect transistor.
14. A circuit as set forth in claim 11 wherein said transistor has an input electrode, said signal responsive means being connected to said input electrode.
15. A circuit as set forth in claim 14 wherein said transistor input electrode is the base electrode of a bipolar transistor.
16. A circuit as set forth in claim 14 wherein said transistor input electrode is the gate electrode of a field-effect transistor.
17. A circuit as set forth in claim 1 and comprising signal input means for receiving an input signal, said signal responsive means including means for selectively switching said impedance means to either of said two states thereof in response to both said input signal and the voltage level of said data bus.
18. A circuit as set forth in claim 17 wherein said signal responsive means comprises a logic gate having two inputs and an output, first means connecting said signal input means to one of said logic gate inputs, second means connecting said data bus to the other of said logic gate inputs, and third means connecting said logic gate output to said impedance means for selectively switching the latter to either of said two states thereof in response to the voltage level of said logic gate output.
19. A circuit as set forth in claim 18 wherein said logic gate is an AND gate.
20. A circuit as set forth in claim 18 wherein said third means comprises a current switch.
21. A circuit as set forth in claim 18 wherein said first means comprises a latch circuit.
22. As circuit as set forth in claim 1 wherein each of said plurality of impedance means comprises a diode biased either to a conductive state to provide said predetermined impedance or to a substantially nonconductive state to provide said higher impedance, said signal responsive means comprising means for biasing said diode either to said conductive state or to said substantially nonconductive state, said impedance means further comprising a substantially constant current source, said diode and said current source being connected in series, said impedance means further comprising a transistor having an electrode, said electrode and said diode being connected to said transmission line data bus.
23. A circuit as set forth in claim 22 and comprising signal input means for receiving an input signal, said signal responsive means including means for selectively switching said impedance means to either of said two states thereof in response to both said input signal and the voltage level of said data bus, said signal responsive means comprising a logic gate having two inputs and an output, first means connecting said signal input means to one of said logic gate inputs, second means connecting said data bus to the other of said logic gate inputs, and third means connecting said logic gate output to said impedance means for selectively switching the latter to either of said two states thereof in response to the voltage level of said logic gate output.
24. A circuit as set forth in claim 22 wherein said impedance means comprises a current switch including said source of substantially constant current and two alternate network branches connected to said source, said transistor and said diode constituting one of said branches, said signal responsive means including means to selectively switch said substantially constant current to either one of said two alternate network branches, said current switch comprising a second transistor constituting the other of said branches, said diode having a first electrode connected to said data bus and a second electrode connected to said current source, said second transistor having an electrode connected to said current source, said second transistor having an input electrode, said signal responsive means being connected to said input electrode.
25. A circuit as set forth in claim 24 and comprising signal input means for receiving an input signal, said signal responsive means including means for selectively switching said impedance means to either of said two states thereof in response to both said input signal and the voltage level of said data bus, said signal responsive means comprising a logic gate having two inputs and an output, first means connecting said signal input means to one of said logic gate inputs, second means connecting said data bus to the other of said logic gate inputs, and third means connecting said logic gate output to said second transistor input eletrode for selectively switching the current switch in response to the voltage level of said logic gate output.
26. A circuit as set forth in claim 25 wherein said first-recited transistor electrode is an emitter electrode, said second transistor electrode is an emitter electrode, and said second transistor input electrode is a base electrode.
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