Fault simulation system for determining the testability of a non-linear integrated circuit by an electrical signal test pattern
阅读：905发布：2023-12-28
专利汇可以提供Fault simulation system for determining the testability of a non-linear integrated circuit by an electrical signal test pattern专利检索，专利查询，专利分析的服务。并且A system involving the use of fault simulation for determining whether a proposed non-linear integrated circuit is testable by a proposed incremental bilevel electrical signal test pattern. The system, which is particularly advantageous in determining the testability of integrated circuits having sequential logic, involves the conversion of the bilevel electrical test pattern into a corresponding three-level test pattern, and the application of said three-level pattern to a three-level ''''good'''' circuit simulation of the integrated circuit and to a number of three-level ''''bad'''' circuit simulations of said circuit, each of said ''''bad'''' circuit simulations being representative of a different stuck fault condition which is to be determined by the test pattern. The resulting output of the ''''good'''' circuit simulation is compared to each of the resulting outputs of the ''''bad'''' circuit simulations, and there is determined both the proportion of the total ''''bad'''' circuits whose definitive outputs fail to compare at least once with the corresponding definitive outputs from the ''''good'''' circuit simulation, and the proportion of total ''''bad'''' circuit simulation manifesting an output at an indeterminate level when the ''''good'''' circuit simulation is at a definitive level.，下面是Fault simulation system for determining the testability of a non-linear integrated circuit by an electrical signal test pattern专利的具体信息内容。
1. In the testing of non-linear integrated circuits having nlevel logic by the application to a plurality of input terminals in the circuit being tested of an n-level electrical signal test pattern having a plurality of sequential pattern increments, each comprising a plurality of parallel n-level signals, each signal respectively applied to one of said input terminals and the sensing of the resulting circuit output from at least one circuit output terminal, a system for determining whether a given n-level test pattern is an acceptable test pattern for a given n-level integrated circuit comprising: means for converting the n-level signal pattern to an (n+1)level signal pattern in which the n levels respectively represent the n definitive levels in the original pattern and said one level represents an indeterminate state; means for forming an (n+1)-level logic ''''good'''' circuit simulation of said n-level integrated circuit in which the n levels represent the n definitive states in the circuit and said one level represents an indeterminate circuit state, said simulation having input nodes representative of said input terminals and at least one output node representative of said output terminal, and said ''''good'''' circuit simulation being free of fault conditions; for each fault condition to be detected by said signal patter, means for forming an (n+1)-level logic ''''bad'''' circuit simulation, repreSentative of the circuit with said fault condition, said simulation being identical with said ''''good'''' circuit simulation except that the circuit portion at which the fault occurs is fixed at said fault condition; means for applying said (n+1)-level test pattern to the plurality of input nodes of said ''''good'''' circuit simulation and to the plurality of input nodes in each of said ''''bad'''' circuit simulations; for each applied increment of said pattern, means for comparing the output signal increments resulting from said applied increment at said at least one output node of said ''''good'''' circuit simulation with the corresponding output signal increment at each of said ''''bad'''' circuit simulations; means, connected to and receiving the output of said comparing means, for recording the total number of ''''bad'''' circuit simulations having at least one output signal at a definitive level which fails to compare with its corresponding ''''good'''' circuit simulation output signal which is at a definitive level; and, means, connected to and receiving the output of said comparing means, for recording the total number of ''''bad'''' circuit simulations having at least one output signal at said indeterminate level when its corresponding ''''good'''' circuit simulation output signal is at a definitive level.
2. In the testing of non-linear bilevel integrated circuits by the application to a plurality of input terminals in the circuit being tested of a bilevel electrical signal test pattern having a plurality of sequential pattern increments, each comprising a plurality of parallel bilevel signals, each signal respectively applied to one of said input terminals and the sensing of the resulting circuit output from at least one circuit output terminal, a system for determining whether a given bilevel test pattern is an acceptable test pattern for a given bilevel integrated circuit comprising: means for converting the bilevel signal pattern to a three-level signal pattern in which the first and second levels respectively represent the two definitive levels in the original pattern and the third level represents an indeterminate state; means for forming a three-level logic ''''good'''' circuit simulation of said bilevel integrated circuit in which the first and second levels represent the two definitive states in the bilevel circuit and the third level represents an indeterminate circuit state, said simulation having input nodes representative of said input terminals and at least one output node representative of said output terminal, and said ''''good'''' circuit simulation being free of fault conditions; for each fault condition to be detected by said signal pattern, means for forming a three-level logic ''''bad'''' circuit simulation, representative of the circuit with said fault condition, said simulation being identical with said ''''good'''' circuit simulation except that the circuit portion at which the fault occurs is fixed at said fault condition; means for applying said three-level test pattern to the plurality of input nodes of said ''''good'''' circuit simulation and to the plurality of input nodes in each of said ''''bad'''' circuit simulations; for each applied increment of said pattern, means for comparing the output signal increments resulting from said applied increment at said at least one output node of said ''''good'''' circuit simulation with the corresponding output signal increment at each of said ''''bad'''' circuit simulations; means, connected to and receiving the output of said comparing means, for recording the total number of ''''bad'''' circuit simulations having at least one output signal at a definitive level which fails to compare with its corresponding ''''good'''' circuit simulation output signal which is at a definitive level; and, means, connected to and receiving the output of said comparing means, for recording the total number of ''''bad'''' circuit simulations having at least one output signal at said indeterminate level when its corresponding ''''good'''' circuit simulation output signal is at a definitive level.
3. The system of claim 2 wherein said given integrated circuit to be tested is only a portion of a more extensive integrated circuit.
4. In the testing of non-linear bilevel integrated circuits by the application to a plurality of input nodes in the circuit being tested of a bilevel electrical signal test pattern having a plurality of sequential pattern increments, each comprising a plurality of parallel bilevel signals, each signal respectively applied to one of said input nodes and the sensing of the resulting circuit output from at least one circuit output node, a system for determining whether a given bilevel test pattern is an acceptable test pattern for a given bilevel integrated circuit comprising: means for converting the bilevel signal pattern to a three-level signal pattern in which the first and second levels respectively represent the two definitive levels in the original pattern and the third level represents an indeterminate state; means for forming a three-level logic ''''good'''' circuit simulation of said bilevel integrated circuit in which the first and second levels represent the two definitive states in the bilevel circuit and the third level represents an indeterminate circuit state, said simulation having input and output nodes representative of said circuit nodes and a plurality of circuit nodes intermediate said input and output nodes, and said ''''good'''' circuit simulation being free of stuck faults; for each stuck fault to be detected by said signal pattern, means for forming a three-level logic ''''bad'''' circuit simulation, representative of the circuit with said fault condition, said simulation being identical with said ''''good'''' circuit simulation except that the one node at which the fault occurs is fixed at one of said first and second levels; means for applying said three-level test pattern to the plurality of input nodes of said ''''good'''' circuit simulation and to the plurality of input nodes in each of said ''''bad'''' circuit simulations; for each applied increment of said pattern, means for comparing the output signal increments resulting from said applied increment at said at least one output node of said ''''good'''' circuit simulation with the corresponding output signal increment at each of said ''''bad'''' circuit simulations; means, connected to and receiving the output of said comparing means, for recording the total number of ''''bad'''' circuit simulations having at least one output signal at a definitive level which fails to compare with its corresponding ''''good'''' circuit simulation output signal which is at a definitive level; and, means, connected to and receiving the output of said comparing means, for recording the total number of ''''bad'''' circuit simulations having at least one output signal at said indeterminate level when its corresponding ''''good'''' circuit simulation output signal is at a definitive level.
5. The system of claim 3 wherein the means for recording said fail-to-compare totals and said indeterminate level totals record said respective totals separately, and said means for recording said indeterminate level totals are adapted so as to include in the indeterminate level totals only ''''bad'''' circuits which do not manifest a fail-to-compare.
6. The system of claim 5 further including means, connected to both of said means for recording, for calculating the proportions: Mfail/Mtotal and Mx/Mtotal are determined, where Mtotal Total ''''Bad'''' Circuits Total Stuck Faults, Mfail Recorded Total ''''Bad'''' Circuits with outputs which fail to compare at least once, and Mx Recorded Total ''''Bad'''' Circuits with outputs at indeterminate levels when ''''Good'''' Circuit output is at definitive level.
7. The system of claim 6 further including means, connected to said calculating means, for further calculating the two calculated proportions.
8. The system of claim 4 wherein each of said stuck faults to be detected results from a circuit node being stuck at either one of said definitive levels.
9. The system of claim 4 wherein said means for comparing are operable only if the output increment of the ''''good'''' circuit simulation is at a definitive level.
10. The system of claim 4 wherein said three-level signal pattern and said three-level logic simulations are formed in double-rail logic.
11. The system of claim 4 wherein said given bilevel test pattern is a randomly generated test pattern.
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