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Integrated circuit chips

阅读:466发布:2023-12-24

专利汇可以提供Integrated circuit chips专利检索,专利查询,专利分析的服务。并且The present invention provides an integrated circuit package having a plurality of package connection electrodes and containing a semiconductor chip, the semiconductor chip having formed thereon a first chain of n first count to X circuit elements each having an individual output, an input terminal to the chain connected to a first of said connection electrodes, a reset terminal for the chain connected to a second of said connection electrodes, said first chain being arranged to divide by Xn, a plurality of storage count to X circuit elements associated one with each of said n first count to X circuit elements, each said storage count to X circuit elements having an individual input and an individual output, a plurality of transfer gate circuit elements interposed one between the individual output of each said first count to X circuit element and the individual input of its associated storage count to X circuit element, each said transfer gate having a control input terminal for a signal to transfer the content of its respective first count to X circuit element to its associated storage count to X circuit element and the input terminals of all said transfer gates being connected to a third of said connection electrodes, and a plurality of output gate circuit elements associated one with each said storage count to X circuit element and connected to the output thereof, each said output gate gate circuit element having an output connected to a first group of said connection electrodes and a control input terminal operatively connected to a second group of said connection electrodes so that the content of each said storage count to X circuit element may be made selectively available at said second group of connection electrodes.,下面是Integrated circuit chips专利的具体信息内容。

1. An integrated circuit package having a plurality of package connection electrodes and containing a semiconductor chip, the semiconductor chip having formed thereon, a first chain of n first count to X circuit elements each having an individual output, an input terminal to the chain connected to a first of said connection electrodes, a reset terminal for the chain connected to a second of said connection electrodes, said first chain being arranged to divide by Xn, a plurality of storage count to X circuit elements associated one with each of said n first count to X circuit elements, each said storage count to X circuit elements having an individual input and an individual output, a plurality of transfer gate circuit elements interposed one between the individual output of each said first count to X circuit element and the individual input of its associated storage count to X circuit element, each said transfer gate having a control input terminal for a signal to transfer the content of its respective first count to X circuit element to its associated storage count to X circuit element and the input terminals of all said transfer gates being connected to a third of said connection electrodes, and a plurality of output gate circuit elements associated one with each said storage count to X circuit element and connected to the output thereof, each said output gate circuit element having an output connected to a first group of said connection electrodes and a control input terminal operatively connected to a second group of said connection electrodes so that the content of each said storage count to X circuit element may be made selectively available at said second group of connection electrodes.
2. An integrated circuit package as claimed in claim 1, including a plurality of carry inhibit gate circuit elements formed on said chip, one between each of said storage count to X circuit elements to connect them in cascade to form a second chain arranged to count to Xn, each said carry inhibit gate having an inhibit input terminal connected to said third connection electrode.
3. An integrated circuit package as claimed in claim 1, including an input gate circuit element formed on said chip, arranged between said input terminAl of said first chain of count to X circuit elements and said first connection electrode, and having a gating input terminal connected to a fourth of said plurality of connection electrodes.
4. An integrated circuit package as claimed in claim 1, wherein said first chain of count to X circuit elements has an output terminal connected to a fifth of said plurality of connection electrodes.
5. An integrated circuit package as claimed in claim 2, wherein said second chain of count to X circuit elements is provided with an input terminal and a further carry inhibit gate is formed on said chip arranged between said second chain input terminal and a sixth of said plurality of connection electrodes, the further carry inhibit gate having an inhibit terminal connected to said third connection electrode.
6. An integrated circuit package as claimed in claim 2, wherein said second chain of count to X circuit elements is provided with an output terminal connected to a seventh of said plurality of connection electrodes.
7. An integrated circuit package as claimed in claim 2, wherein an output control circuit element is formed on said chip arranged between said first group of connection electrodes and the control input terminals of said output gate circuit element, whereby coded signals applied to said first group of connection electrodes may select the operation of said output gates.
8. An integrated circuit package as claimed in claim 7, wherein said first and storage count to X circuit elements are each decade counting binary circuit groups and said output gate outputs are connected to eighth, ninth, 10th and 11th of said plurality of connection electrodes forming said first group.
9. An integrated circuit package as claimed in claim 7, wherein there are four each of said first and storage count to X circuit elements and said output control circuit is connected to 12th and 13th of said plurality of connection electrodes forming said second group.
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