Integrated circuit
专利汇可以提供Integrated circuit专利检索，专利查询，专利分析的服务。并且PURPOSE:To shorten a time required for the die sort process and to facilitate fabrication of probe cards by an integrated circuit wherein pads are arranged into a combined shape of U-forms or L-forms on chips for EPROM. CONSTITUTION:In EPROM formed of floating gate type MOSFET, for example, pads 13 are provided along only three sides of each chip. On a wafer every two chips 11, 12 are arranged as one pair in such a manner that the two sides of the respective chips including no pad 13 are faced to each other. Plural pairs of chips are arranged in the same manner successively. As an alternative, the pads 13 are provided along only two sides of each chip and every four chips 14-17 are arranged as one set on the wafer in such a manner that the corresponding two sides of the respective chips including no pads are faced to each other. Plural sets of chps are arranged on the wafer similarly. By so doing, it becomes possible to carry out the die sort test for a plurality of chips at the same time and also to shorten a time required for the process. In addition, a pin arrangement for a probe card is made to have high density in part and it may not occur that other pins across above one pin, so that fabrication of the probe case can be facilitated.，下面是Integrated circuit专利的具体信息内容。
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