Parallel multiplier
专利汇可以提供Parallel multiplier专利检索，专利查询，专利分析的服务。并且PURPOSE: To perform the addition at high speed with a circuit of a small scale by using a full adder which connects adders in a tree structure and adds the output of the adder of a first stage with a carry signal and adding 4 data input terminals to those adders forming a tree structure.
CONSTITUTION: The adders 1 and 2 set on the 1st stage of an i-th digit perform the addition at every 7 bits supplied in parallel and process 14 bits in all. Then the adders 1 and 2 send the sums S
1 and S
2 to an adder 3 of a 2nd stage. Furthermore the adder 1 sends a 1-bit carrier signal C
1a which is carried up to the (i+1)-th digit and a 1-bit carry signal C
2a carried up to the (i+2)-th digit to the adders 30 and 35 respectively. While the adder 2 sends the carry signals C
1b and C
2b to the adders 30 and 35. An unprocessed bit out of the inner product of 15 bits, both sums S
1 and S
2 , and each bit of carry signals C
1a ', C
1b ' and C
2b ' received from the adder of the 1st stage are inputted to the adder 3 and added together. This sum S
3 is sent to a full adder 4 and at the same time the carry signals C
3d and C
3e are sent to the full adders 31 and 36 and added with the sums S
3 received from the adders 30 and 35 respectively.
COPYRIGHT: (C)1990,JPO&Japio，下面是Parallel multiplier专利的具体信息内容。
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