CROSS-REFERENCE TO RELATED APPLICATION

This application is related to application Ser. No. 122,299 filed concurrently herewith by Joseph M. Lenart entitled, "Ring Communication System" and assigned to the assignee of the present application.

BACKGROUND OF THE INVENTION

This invention relates to communication systems. More particularly, it is concerned with communication systems employing a network of switching stages connected in a closed ring.

Ring communication systems generally include a plurality of switching nodes intercoupled in a ring with ring transmission paths interconnecting the nodes for transmitting data from node to node around the ring. Each of the switching nodes is an interface at which data may be coupled onto and off of the ring. Ring switching allows various levels of distributing or decentralizing the logic and physical control of a communication system. Ring switching systems may be structured to provide a distributed switching system in which control is dispersed to the switching stage at each individual switching node. That is, all of the control functions are performed independently and autonomously by the switching stages. Only the timing function for synchronizing the operations of the switching stages is common to all the switching stages.

In ring switching systems of this type, the individual switching stages should have low propagation delay so as to permit a large number of nodes to be incorporated in a ring, thus providing high capacity for the network. The switching stages should independently provide the necessary driving power for transmitting data therefrom both on and off the ring, thus permitting expansion without creating additional load on output devices.

SUMMARY OF THE INVENTION

Time-division multiplexed switching apparatus in accordance with the present invention includes a plurality of switching stages arranged in a closed ring with ring bus means connecting each switching stage to the preceding switching stage of the ring and to the succeeding switching stage of the ring. Each switching stage in the ring is designated by a unique address. Words of digitally encoded information are transferred from one switching stage to the succeeding switching stage at a first data rate.

Each of the switching stages comprises a ring input storage means coupled to the ring bus means for receiving and storing a word of digitally encoded information transferred over the ring bus means from the preceding switching stage. The ring input storage means has an input coupled to the ring bus means from the preceding switching stage and has an output. The apparatus also includes a transfer input storage means for receiving and storing a word of digitally encoded information to be transferred onto the ring. The transfer input storage means has an input and an output. A transfer output storage means for storing a word of digitally encoded information has an input and an output.

A multiplexing means has a first input coupled to the output of the ring input storage means and a second input coupled to the output of the transfer input storage means. The multiplexing means has an output coupled to the ring bus means to the succeeding switching stage. The apparatus also includes means for producing clock signals at the first data rate. The ring input storage means is operable to store a word received on the ring bus means from the preceding switching stage on the leading edge of each clock signal. An address means determines if a word stored in the ring input storage means is addressed to the address of the switching stage.

A multiplexer control means is coupled to the multiplexing means. The multiplexer control means operates when a word is stored in the ring input storage means and the address means determines that the stored word is not addressed to the address of the switching stage to cause the multiplexing means to couple the output of the ring input storage means to the ring bus means to the succeeding switching stage. The multiplexer control means operates when a word is stored in the ring input storage means and the address means determines that the stored word is addressed to the address of the switching stage to cause the multiplexing means to couple the output of the ring input storage means to the input of the transfer output storage means. The multiplexer control means operates when a word is stored in the transfer input storage means, unless a word is stored in the ring input storage means and the address means determines that that word is not addressed to the address of the switching stage, to cause the multiplexing means to couple the output of the transfer input storage means to the ring bus means to the succeeding switching stage. The transfer output storage means operates in response to the termination of a clock signal to store a word present at its input.

BRIEF DESCRIPTION OF THE DRAWINGS

In the drawings:

FIG. 1 is a schematic representation of a time-division multiplexed ring switching network in accordance with the present invention;

FIG. 2 is a block diagram of a single switching stage of the network of FIG. 1:

FIG. 3 is a table showing relationships between signals internally of a switching stage under various conditions for explaining the operation of a switching stage of FIG. 2; and

FIG. 4 is a timing diagram of a single clock pulse or operating cycle of a switching stage.

For a better understanding of the present invention together with other and further objects, advantages, and capabilities thereof, reference is made to the following disclosure and appended claims in connection with the above-described drawings.

DETAILED DESCRIPTION

A time-division multiplexed switching network in accordance with the present invention is illustrated schematically in FIG. 1. The switching network 10 includes N switching stages 11, one at each node, connected in series in a ring by interconnecting ring transmission paths labeled T_X. Each of the substantially identical switching stages 11 also receives data over an incoming communication path T₁ and transmits data over an outgoing communication path labeled T₁. Words of digitally encoded information are received at a switching stage over the incoming path T₁ and placed on the ring by the switching stage. Each word may be a single byte, several bytes, or any combination of bits which are handled together. The word is passed from switching stage to switching stage around the ring until it arrives at its destination switching stage where it is removed from the ring and placed on the outgoing T₁ path. The destination switching stage is designated by address information either contained in each word or in the first word of a message.

Words of a message may be transmitted over a T₁ path to a switching stage at the conventional T1 rate. That is, each frame of 24 channels, or time slots, is repeated every 125 microseconds. The bits of each word are transmitted in parallel during a channel period or time slot. Each word is transmitted from node to node around the ring at a rate such that it would be propagated completely around the ring in a period of time equal to a single T1 time slot or channel period. That is, the rate of transmitting data from switching stage to switching stage around the ring is equal to N times the T1 rate, where N is the number of nodes or switching stages in the ring network. Timing within the switching stages of the ring is synchronized by a common clock 12 which produces a continuous series of clock pulses.

In the specific embodiment under discussion each word includes address information in addition to other data being transmitted. The address information designates the switching stage destination, each switching stage having a unique address. A status bit indicating the presence or absence of a word is associated with each word.

FIG. 2 is a block diagram illustrating a switching stage 11 of the network. An incoming ring bus T_Xi from the preceding switching stage is connected to the input of a ring input register 15 for receiving and storing the bits of an incoming word in parallel. A word present on the bus T_Xi is latched into the register 15 on the leading edge of a clock pulse, as indicated in FIG. 4. A similar register is connected to an incoming bus T_1i and designated as the transfer input register 16. The bits of a word on incoming bus T_1i are applied directly to the input of register 16 and the associated status bit is applied to a flip-flop 17, the function of which will be explained hereinbelow. The transfer input register 16 is also clocked to latch the word present on the T_1i bus on the leading edge of each clock pulse.

The outputs of the ring input register 15 and of the transfer input register 16, except for the status bits, are connected to two separate sets of inputs of a multiplexer 21. The output of the multiplexer 21 is connected to the ring bus T_Xo to the succeeding switching stage of the ring for loading into the succeeding switching stage on the leading edge of the next clock pulse.

The output of the ring input register 15 is also connected to the input of a transfer output register 25. The output of the transfer output register 25 is connected to an outgoing bus T_1o. The transfer output register 25 is triggered to latch the data present at its input by a signal OUT generated on the trailing edge of the clock pulse as indicated by FIG. 4.

The address of the individual switching stage 11 is stored in a switching stage address register 31, which may be a ROM. The address bits of a word on the ring bus T_xi to the input of the ring input register 15 are compared with the address stored in the switching stage address register 31 by a comparator 32. The comparator 32 produces an appropriate output signal X= designating whether or not the address of the word to be loaded into the ring input register 15 is the same as the address of the switching stage. If the dddress in the word is not the address of the switching stage, the word is to be passed through the switching stage to the succeeding switching stage of the ring. If the address in the word is the address of the switching stage, the word is to be transferred off, or dropped from, the ring to the bus T_1o by way of the transfer output register 25. All words received on the transfer input bus T_1i are to be transferred to, or inserted on the ring output bus T_xo.

Each switching stage also includes control logic 30 which receives certain information from components of the switching stage and in response thereto produces certain signals which control components to cause predetermined actions. FIG. 3 is a truth table of the possible input conditions to the control logic 30 and the resulting output signals, and includes a summary of the overall actions of the switching stage for each condition. The various signals are designated as logic 1 or logic 0 bits. Included in the data applied to the control logic 30 are the status bits S_X and S₁ indicating whether a valid word is present or not present in the ring input register 15 and the transfer input register 16, respectively. A status bit of logic 1 indicates the presence of the respective word and a logic 0 indicates its absence. The output signal X= of the comparator 32 is a logic 1 if there is a match between the address information of the word in the ring input register 15 and the address of the switching stage as stored in the switching stage address register 31. Otherwise X= is logic 0. The clock pulses are also applied to the control logic 30.

In response to these inputs the control logic 30 produces a set of outputs. A multiplexer control signal M to the multiplexer 21 is either a logic 1 or logic 0. The control logic 30 also produces signals labelled OUT and IN on termination of the clock pulse. Signal OUT is a loading signal and controls the latching of words into the transfer output register 25. Signal IN is an inhibiting signal and resets the flip-flop 17 to change the status bit S₁ stored in the transfer input register 16. Both bits OUT and IN are active at the 0 logic levels, and more specifically on changing to logic 0 on the trailing edge of a clock pulse.

The output M of the control logic 30 is a logic 1 to cause the multiplexer 21 to couple the output of the ring input register 15 to the ring output bus T_xo. The multiplexer control signal M is a logic 0 to prevent the output of the ring input register 15 from being coupled to the ring output bus T_xo and also to cause the output of the transfer input register 16 to be coupled to the ring output bus T_xo.

Signal OUT which is a logic 1 during a clock pulse will change to a logic 0 upon termination of the clock pulse only if a word is to be loaded into the transfer output register 25 from the transfer input register 16. Also upon termination of a clock pulse the signal IN changes from a logic 1 to logic 0 only if a word is present in the transfer input register 16 and has been coupled to the ring output bus T_xo. The signal IN triggers the flip-flop 17 so as to change the status bit S₁ in the transfer input register 16 from a logic 1 to logic 0. Thus, until the status bit is replaced, S₁ is logic 0 preventing the contents of the transfer input register 16 from being inserted onto the ring output bus T_xo more than once. On receipt of the next word on incoming bus T_1i, the accompanying status bit of logic 1 sets the flip-flop 17 so that it presents a logic 1 at the input to the transfer input register 16.

The switching stage as illustrated operates during an operating cycle of a clock pulse when no valid word has been presented over either of the incoming buses T_Xi or T_1i to load nothing into the transfer output register 25 and transmit no information on outgoing buses T_Xo or T_1o, as illustrated for condition 1 in the table of FIG. 3. Under condition 2 a word is loaded into the ring input register 15 on the leading edge of a clock pulse and the address of the word is not the address of the switching stage. The word is coupled through the multiplexer 21 for transmittal over the outgoing bus T_Xo to the succeeding switching stage. Under condition 3 a word is loaded into the ring input register 15 and is identified as being addressed to the switching stage. The word is loaded into the transfer output register 25 at the termination of the clock pulse and is available for transmission on bus T_1o. No information is transmitted to the succeeding switching stage.

Under condition 4 a word is loaded into the transfer input register 16 from the incoming bus T_1i and there is no valid word loaded into the ring input register 15. The word is coupled from the transfer input register 16 through the multiplexer 21 to the ring output bus T_Xo to the succeeding switching stage. An IN bit of logic 0 is also produced resetting flip-flop 17 and thus preventing the contents of the transfer input register 16 from being processed more than once.

Under condition 5 a word is loaded into the ring input register 15 and a word is also loaded into the transfer input register 16 on the leading edge of a clock pulse, the byte loaded into the ring input register 15 not being addressed to the switching stage. The control logic 30 causes the first multiplexer 21 to couple the word in the ring input register 15 to the ring output bus T_xo. Since under these conditions the OUT signal remains at logic 1, nothing is loaded into the transfer output register 25. The word in the transfer input register 16 remains in that register and is available to be transferred to the ring output bus T_xo during the first subsequent clock period in which there is no word being passed from the ring input register 15 to the ring output bus T_xo.

In the event that the word stored in the ring input register 15 is addressed to the switching stage as indicated under condition 6, M signal of logic 0 causes the multiplexer 21 to couple the contents of the transfer input register 16 to the ring output bus T_xo. The contents of the ring input register 15 are applied to the input of the transfer output register 25, and on the trailing edge of the clock pulse the control logic 30 causes the OUT signal to become logic 0 latching the transfer output register 25. At the same time the IN signal becomes logic 0 triggering the flip-flop 17 to reset the status bit S₁ to logic 0 so that the contents of the transfer input register 16 cannot be reprocessed during subsequent clock pulses.

As illustrated in the timing diagram of FIG. 4, the input registers 15 and 16 are latched on the leading edge of each clock pulse to load the words present at their inputs, if any. The various resulting signals S_X, S₁, and X=, are coupled to the control logic 30. A sufficient decode period is provided for the control logic 30 to decode the received information and become stabilized before the termination of the clock pulse. Logic 0 signals for OUT and IN are not produced until the trailing edge of the clock pulse. There are no other critical timing relationships internally of the switching stage. The period between the trailing edge of one clock pulse and the leading edge of the next clock pulse is such as to allow for propagation delay from each switching stage to the succeeding switching stage along the ring bus.

With the apparatus as shown, each word includes address bits to identify its destination switching stage in the ring. Alternatively, the address bits may be included in only the first word of a message. The switching stage would include a counter which counts through N (the number of switching stages) clock pulses and transfers a word off the ring every Nth clock pulse.

The network and switching stages as described provide a truly distributed switching network in which each of the switching stages operates independently of all the others except for the common clock. The capacity of the network is limited only by the number of switching stages and the clock speed. There are no common control or stored program control limitations. The simplicity of the logic at each node permits each stage to be small and highly integrated. The stages can, therefore, be physically placed close together with short connecting paths. Consequently the load on the output of each stage is low and propagation delay through the network is low. The propagation delay within each switching stage is one clock period. In addition, the network provides for expansion in that the switching stages are regenerative and connected in series so that the loading on output driver circuits of each switching stage does not limit further expansion as would be the case if the switching stages were connected to a common bus rather than in series in a ring configuration.

While there has been shown and described what is considered a preferred embodiment of the present invention, it will be obvious to those skilled in the art that various changes and modifications may be made therein without departing from the invention as defined by the appended claims.