| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 41 | 一种聚变反应装置 | CN201710995686.6 | 2017-10-23 | CN109698032A | 2019-04-30 | 黄耀辉 |
| 本发明涉及核聚变领域，公开了一种聚变反应装置，该聚变反应装置包括反应腔室、电子发生器和至少一个放电电极，其中所述放电电极和所述电子发生器位于所述反应腔室内，所述放电电极的基底是渐缩结构，在进行聚变反应时，聚变燃料和所述电子发生器产生的电子都被提供到所述基底中，且从聚变燃料中产生的具有离子和中性粒子的等离子体在被施加了电功率的所述放电电极所产生的振荡电场的驱动下旋转以发生聚变反应，所述电子发生器所产生的电子用于降低所述等离子体中两个正在靠近的原子核内的带正电的质子之间的库仑势垒。该聚变反应装置成本低且能够容易地完成核聚变。 | ||||||
| 42 | 一种基于SOI量子线的单电子晶体管及其制作方法 | CN200710064857.X | 2007-03-28 | CN101276836A | 2008-10-01 | 王琴; 李维龙; 贾锐; 刘明; 叶甜春 |
| 一种基于SOI量子线的单电子晶体管及其制作方法。本发明的主要特征是在SOI衬底上制备量子线，利用金属栅对量子线的势垒受限形成隧道结和库仑岛，从而降低了微纳加工的难度，实现隧道结有效尺寸可调的单电子晶体管。其主要工艺步骤如下：(a)离子注入及快速退火；(b)电子束光刻，形成量子线图形；(c)干法刻蚀，将图形转移至SOI的顶层硅上；(d)光刻；(e)蒸发金属，剥离，合金；(f)二次电子束套刻，形成栅图形；(g)蒸发栅金属；(h)剥离，形成金属栅；采用本发明方法制备的基于SOI量子线的单电子晶体管具有工艺难度低，可实行性高，易于大规模集成的优点。 | ||||||
| 43 | 一种聚变反应装置 | CN201721367961.1 | 2017-10-23 | CN208077617U | 2018-11-09 | 黄耀辉 |
| 本实用新型涉及核聚变领域，公开了一种聚变反应装置，该聚变反应装置包括反应腔室、电子发生器和至少一个放电电极，其中所述放电电极和所述电子发生器位于所述反应腔室内，所述放电电极的基底是渐缩结构，在进行聚变反应时，聚变燃料和所述电子发生器产生的电子都被提供到所述基底中，且从聚变燃料中产生的具有离子和中性粒子的等离子体在被施加了电功率的所述放电电极所产生的振荡电场的驱动下旋转以发生聚变反应，所述电子发生器所产生的电子用于降低所述等离子体中两个正在靠近的原子核内的带正电的质子之间的库仑势垒。该聚变反应装置成本低且能够容易地完成核聚变。(ESM)同样的发明创造已同日申请发明专利 | ||||||
| 44 | 核力约束惯性制导冷核直接对撞聚变堆和直流变压器 | CN200910129632.7 | 2009-03-14 | CN101540211A | 2009-09-23 | 黄振强 |
| 核力约束惯性制导冷核直接对撞聚变堆和直流变压器发明，特征是：在常温真空条件下，根据轻原子核固有的磁矩和内电场，先设置空间特定组合的电磁场。在强正电场背景中，以静电场矢量叠加方式，构成一条线状零电场。将两串由30～150万伏特静电直线型粒子加速器中喷射出来待聚变的原子核约束在这条线状零电场构成的线形通道内。外加强磁场平行于这条线状零电场，对原子核的自旋动量矩矢量起关键的定向作用。再利用原子核固有的自旋动量矩矢量形成近光速自旋的超强力自转陀螺惯性制导特性，来克服库仑强势垒的偏向排斥作用，实现惯性主动瞄准制导直接对撞核聚变的。应用相似的核力约束惯性制导方式，对不同速度和能量的离子束进行混合调速，研制成的离子调速直流变压器，是冷核聚变堆、核发动机和该类核电站启动核聚变和电能输送系统的重要配套设备，所以合并申请一个专利权。 | ||||||
| 45 | 核力约束惯性制导冷核聚变堆和离子调速直流变压器 | CN200810087911.7 | 2008-03-18 | CN101350582A | 2009-01-21 | 黄振强 |
| 核力约束惯性制导冷核聚变堆和离子调速直流变压器发明项目，有望一劳永逸地彻底解决全人类面临的能源和环保难题。为一切宇宙飞船、飞机、舰船、车辆及发电厂……等耗能设备、工厂提供洁净安全无限的核动力能源，使全人类真正进入核能时代。本发明项目特征是：在常温条件下，设置空间特定组合的电磁场，根据轻原子核固有的磁矩和内电场，先将两串待聚变的原子核约束在同一条线段内；再利用原子核固有的自旋动量矩矢量形成近光速自旋的超强力自转陀螺惯性制导特性，来克服库仑强势垒的偏向作用，实现直接对撞核聚变的；应用相似的核力约束惯性制导方式，对不同速度和能量的离子束进行混合调速，研制成的离子调速直流变压器，是冷核聚变堆、核发动机和该类核电站启动核聚变和电能输送系统的重要配套设备，所以合并申请一个专利权。 | ||||||
| 46 | FUSION ENERGY PRODUCTION | US13295163 | 2011-11-14 | US20120057666A1 | 2012-03-08 | Joseph M. JACOBSON |
| Systems and methods are described for carrying out fusion reactions by changing the Coulombic energy barrier via Muon Catalyzed Fusion. | ||||||
| 47 | 쿨롱진동 위상제어 가능한 단전자 소자 | KR1020030008960 | 2003-02-07 | KR1020040072453A | 2004-08-18 | 최중범; 이상돈 |
| PURPOSE: A single electron device for controlling a phase of coulomb oscillation is provided to reduce the size of a quantum dot and generate spontaneously a tunneling barrier by using a PADOX(PAttern Dependent OXidation) method and an anisotropic oxidation method. CONSTITUTION: A lateral gate(6) is patterned vertically from a center part of a conductive channel(5) for connecting a source(3) and a drain(4) on a top silicon layer of an SOI(Silicon On Insulator) substrate(1) by using an electron-beam direct writing method. A phase of coulomb oscillation of a quantum dot is controlled by using the supplied voltage. The size of the quantum dot is reduced and a tunneling barrier is spontaneously generated in a process for forming a gate oxide layer by using a PADOX method. | ||||||
| 48 | 마이크로전자 디바이스 | KR1019990043361 | 1999-10-08 | KR1020000034979A | 2000-06-26 | 베튠도날드스팀슨; 티와리샌딥 |
| PURPOSE: A micro electric device is provided to minimize the size of capacitors, to decrease capacitance thereof, and to increase the coulomb trap effect and safety of the micro electric device. CONSTITUTION: A micro electric device includes a board(2), an insulation layer(6), and a field effect transistor. The board(2) includes a source(3) region and a drain(4) region divided by a channel region(5). The insulation layer(6) is placed on the channel region(5). The insulation material includes at least one cage molecule(8) including a closed hollow shell. The cage molecule(8) is able to conduct electrons substantially, and to define a coulomb barrier, and to accept and store at least one electron when a voltage high enough to overcome the coulomb barrier is applied between the source region(3) and drain region(4) and the gate. | ||||||
| 49 | COULOMB BARRIER STORAGE DEVICE, COMPRISING A PLURALITY OF ELECTRON TRAPS, AND METHOD FOR MAKING SAME | PCT/FR2001/001446 | 2001-05-14 | WO01088988A1 | 2001-11-22 | |
| The invention concerns a Coulomb barrier storage device comprising a single continuous floating gate (22) associated with a plurality of barrier islands and a control gate (38, 42), the gates being separated from said plurality of barrier islands (34), and each barrier island comprising an alternating pile (24) of a plurality of conductive (24b) and dielectric layers (24a). The invention is useful for making random-access storage units. | ||||||
| 50 | Conduction control device | EP95304592.9 | 1995-06-29 | EP0696065A2 | 1996-02-07 | Nakazato, Kazuo |
A conduction control device, for example a single electron transistor consists of a source 1, a drain 2 and a charge-receiving island 3 separated from the source and drain by respective tunnel barrier junctions TJ1, TJ2. The device is constructed on the nanometre scale, and the charge on the island 3 is limited by the Coulomb blockade effect to a small discrete number of electrons. A gate electrode 4 overlies the island 3. In order to provide a high gate/drain gain, a voltage drop region 15 is connected in series between the tunnel barrier junction TJ2 and the drain 2 so as to increase the effective Coulomb gap voltage Vc. |
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| 51 | MULTILEVEL MEMORY DEVICE WITH COULOMB BARRIER, METHOD FOR MAKING SAME AND READING/WRITING/ERASING METHOD OF SUCH A DEVICE | PCT/FR1998/002768 | 1998-12-17 | WO99033120A1 | 1999-07-01 | |
| The invention concerns a multilevel memory device with Coulomb barrier comprising a MOSFET with floating grid. The dielectric (32) separating the floating grid (20) from the control grid (28) comprises a plurality of nanometric conducting islands (34) forming a three-dimensional structure (30) wherein they are evenly distributed. | ||||||
| 52 | APPARATUS AND PROCESS FOR PENETRATION OF THE COULOMB BARRIER | EP13780663.4 | 2013-04-25 | EP2842132A2 | 2015-03-04 | YAZDANBOD, Azaroghly |
| A device and method for penetrating the Coulomb barrier is disclosed, An electrode is positioned within a hollow shell, the shell enclosing an inner space containing a fusion reactive fuel such as deuterium. The inner space with the fuel is coaxially centered about the electrode, and a confinement layer made of a high dielectric strength material is located at the outer edge of the inner space, on the inside surface of the spherical shell. A high voltage power source charges the electrode, which causes a tightly packed fusion fuel nucleus cloud such as a deuteron cloud to form on the inner face of the confinement layer, facilitating coulomb barrier penetration. Using the device of the invention, conditions can also be created which enable Coulomb barrier penetration by firing nuclei towards the cloud of nuclei by applying high voltage pulses to the electrode. | ||||||
| 53 | APPARATUS AND PROCESS FOR PENETRATION OF THE COULOMB BARRIER | PCT/US2013038146 | 2013-04-25 | WO2013163382A2 | 2013-10-31 | YAZDANBOD AZAROGHLY |
| A device and method for penetrating the Coulomb barrier is disclosed, An electrode is positioned within a hollow shell, the shell enclosing an inner space containing a fusion reactive fuel such as deuterium. The inner space with the fuel is coaxially centered about the electrode, and a confinement layer made of a high dielectric strength material is located at the outer edge of the inner space, on the inside surface of the spherical shell. A high voltage power source charges the electrode, which causes a tightly packed fusion fuel nucleus cloud such as a deuteron cloud to form on the inner face of the confinement layer, facilitating coulomb barrier penetration. Using the device of the invention, conditions can also be created which enable Coulomb barrier penetration by firing nuclei towards the cloud of nuclei by applying high voltage pulses to the electrode. | ||||||
| 54 | Logic apparatus and logic circuit | US09990362 | 2001-11-23 | US06787795B2 | 2004-09-07 | Ken Uchida; Junji Koga; Ryuji Ohba |
| A logic apparatus having first and second single-electron devices connected serially or in parallel. Each of the single-electron devices includes a conductive island insulatively disposed between two tunnel barriers, which separate the conductive island from respective source/drain electrodes. A first charge storage region is insulatively disposed over and under the conductive island and a gate electrode, respectively. When charges are accumulated in the charge storage region, a Coulomb oscillation of the respective device is shifted by a half-period from the Coulomb oscillation that results when no charge has accumulated therein. | ||||||
| 55 | Logic device | EP93301982.0 | 1993-03-16 | EP0562751A2 | 1993-09-29 | Nakazato, Kazuo; White, Julian D. |
A logic device comprises a series of charge storage nodes NO - N3 that are interconnected by tunnel barriers D. Clock waveforms V1 - V3 applied to clock lines CI 1 - CI 3 selectively alter the probability of charge carriers passing through the tunnel diodes D from node to node, the arrangement being such that the amount of charge at each node is limited by Coulomb blockade so as to define first and second logical levels. Typically, the logical levels are defined by the presence or absence of a single electron, although larger numbers e.g. ten, can be utilised. An output device, typically a Coulomb blockade electrometer provides an output logical signal indicative of the logical state of node N3. |
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| 56 | Fusion energy production | US11800610 | 2007-05-07 | US20080008286A1 | 2008-01-10 | Joseph Jacobson |
| Systems and methods are described for carrying out fusion reactions by changing either the Coulombic energy barrier or the reaction cross section or both. Such systems and methods are useful for creating fusion reactions which exceed energy breakeven (Q>1) and which have a relatively low cost and compact size. | ||||||
| 57 | 단전자 나노소자의 제작방법 및 그에 따른 단전자 나노소자 | KR1020050089930 | 2005-09-23 | KR101050875B1 | 2011-07-20 | 최중범; 이상돈; 신승준 |
| 본 발명은 단전자 나노소자의 제작방법 및 그에 따른 단전자 나노소자에 관한 것으로, 더욱 상세하게는 확산기법을 사용하여 도핑함으로써 측면게이트의 전계효과를 양자점으로 효과적으로 전달할 수 있고, 실리콘 산화막을 더 형성함으로써 게이트 누설전류를 방지하고, 측면게이트에 인가되는 전압을 향상시켜 측면게이트에 의한 터널링 장벽과 다중양자점의 형성 및 쿨롱진동의 위상제어가 용이한 단전자 나노소자의 제작방법 및 그에 따라 제작된 단전자 나노소자에 관한 것이다. SOI 기판, 단전자 나노소자, 양자점, 쿨롱진동, 확산, 측면게이트 | ||||||
| 58 | 電界効果型化合物半導体装置 | JP2015532595 | 2013-08-19 | JPWO2015025349A1 | 2017-03-02 | 聡 遠藤 |
| 電界効果型化合物半導体装置に関し、高濃度δドーピングによるシート抵抗の低減とリモートクーロン散乱の低減を両立する。下部バリア層及び上部バリア層の少なくとも一方の層中にチャネル電子の供給源となる不純物原子が面状ドーピングされた面状ドーピング層を設け、バリア層のチャネル層に接する部分をV族元素がSbであるIII-V族化合物半導体スペーサ層とする。 | ||||||
| 59 | VERTICAL GATE-DEPLETED SINGLE ELECTRON TRANSISTORS | PCT/US2003/035809 | 2003-11-12 | WO2004049396A2 | 2004-06-10 | ZHANG, Yaohui; BARON, Filipp, A.; WANG, Kang, L. |
A vertical gate-depleted single electron transistor (SET) is fabricated on a conducting or insulating substrate. A plurality of lightly doped basic materials and tunneling barriers are fabricated on top of a substrate, wherein at least two of the layers of basic materials sandwich the layers of tunneling barriers and at least two of the layers of tunneling barriers sandwich at least one of the layers of basic materials. A mesa is fabricated on top of the layers of basic materials and tunneling barriers, and has an undercut shape. An ohmic contact is fabricated on top of the mesa, and one or more gate Schottky contacts are fabricated on top of the layers of lightly doped basic materials and tunneling barriers. A quantum dot is induced by gate depletion, when a source voltage is set as zero, a drain voltage is set to be less than 0.1, and a gate voltage is set to be negative. The depletion region expands toward the center of the device and forms a lateral confinement to the quantum well, wherein a quantum dot is obtained. Because the size of the quantum dot is so small, the Coulomb charging energy achieved is large enough to let the device operate at room temperature. |
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| 60 | 電界効果型化合物半導体装置 | PCT/JP2013/072061 | 2013-08-19 | WO2015025349A1 | 2015-02-26 | 遠藤聡 |
電界効果型化合物半導体装置に関し、高濃度δドーピングによるシート抵抗の低減とリモートクーロン散乱の低減を両立する。下部バリア層及び上部バリア層の少なくとも一方の層中にチャネル電子の供給源となる不純物原子が面状ドーピングされた面状ドーピング層を設け、バリア層のチャネル層に接する部分をＶ族元素がＳｂであるIII-Ｖ族化合物半導体スペーサ層とする。 |
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