Differential pulse coded system using shift register companding |
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| 申请号 | US46187874 | 申请日 | 1974-04-18 | 公开(公告)号 | US3925731A | 公开(公告)日 | 1975-12-09 |
| 申请人 | BELL TELEPHONE LABOR INC; | 发明人 | BRAINARD RALPH CARTER; CANDY JAMES CHARLES; | ||||
| 摘要 | A digital accumulator employing a reversible shift register converts a 1-bit differential pulse code to a logarithmically companded, or n:m, pulse code. The accumulator is coupled through a digital-to-analog converter to a subtraction circuit which also receives an analog signal to be represented in the differential pulse code. Output from the subtractor is integrated and thresholded to produce the differential pulse code. A decoder using the same type of accumulator is also shown. | ||||||
| 权利要求 | 1. In a differential pulse code system, an encoder comprising an analog subtraction circuit having a first input for receiving an analog signal to be converted to digital format, and having a second input for receiving a discrete analog approximation of the digital format, means for integrating a difference output signal from said subtraction circuit, means for producing an output pulse in response to each attainment of a predetermined threshold amplitude by an output signal from said integrating means, the output from said producing means comprising said digital format, one or the other of a pulse state or a no-pulse state in said producing means output indicating an increasing analog signal and the other of such states indicating a decreasing analog signal, means responsive to said pulses for digitally accumulating increasing and decreasing pulse state information represented by said digital format to produce a continuous digital summation of analog signal increases and decreases, and means for applying an analog representation of the contents of said digital accumulating means to said second input as said analog approximation of said digital format. 2. The system in accordance with claim 1 in which said producing means is a 1-bit trigger circuit, and said applying means comprises means for converting each summation in said accumulating means to an analog signal having an amplitude corresponding to the binary value of said summation. 3. The system in accordance with claim 2 in which said accumulating means includes means for forming said summation in accordance with a binary companded form of coding, and means are provided for receiving a clock signal to enable said trigger circuit at a rate which is at least equal to the product of the Nyquist rate for anticipated analog signals to be converted and the number of amplitude intervals per segment of a piecewise linear approximation pulse code in said companded form of coding. 4. The system in accordance with claim 3 in which said receiving means receives a clock signal which is twice the rate of said product. 5. The system in accordance with claim 1 in which said accumulating means comprises a reversible shift register, and means for operating said shift register in one direction or the other in response to first and second predetermined signal states, respectively, at the output of said producing means. 6. The system in accordance with claim 1 in which there is provided in addition a decoder coupled to said encoder and comprising means responsive to said pulses for digitally accumulating said increasing and decreasing pulse state information represented by said digital format, and means responsive to outputs of said decoder accumuLating means for producing a further discrete analog approximation of said analog signal. 7. The system in accordance with claim 1 in which said integrating means includes means fixing a substantially uniform integration characteristic extending over a frequency range between the low frequencies of interest in said analog signal to be converted and the frequency at which said producing means are periodically enabled. 8. The system in accordance with claim 1 in which said producing means has a predetermined range of variation in said threshold amplitude, and said subtraction circuit and said integrating means include means for providing sufficient gain so that a signal step of the smallest size in said discrete analog approximation produces in said output from said integrating means a signal change much greater than said variation range. 9. In a differential pulse code system, digital signal decoding means comprising a reversible shift register having an input connection for application of shift clock signals means, including said shift register, for accumulating information represented by a differential pulse coded signal train, said accumulating means comprises means responsive to said pulse coded signal train for controlling shifting direction in said shift register to shift in a first direction in response to a pulse signal state in said train and to shift in a second direction in response to a no-pulse signal state in said train, said signal train including a succession of signal bit times recurring at the same rate as said clock signals, and means for deriving from said shift register a discrete analog approximation signal having in each bit time an amplitude corresponding to the binary coded value of the contents of said shift register at that time. 10. The system in accordance with claim 9 in which there are provided in said accumulating means means for entering binary ONE signal bits into the least significant stage or said shift register during shifting operations from the least significant stage toward the most significant stage, and means for inserting a binary ZERO into the most significant stage of said shift register during each shifting operation from the most significant stage toward the least significant stage. 11. The system in accordance with claim 9 in which there is provided in the deriving means a resistance ladder network having input connections from respective stages of said shift register and having an output connection from an end of said ladder network at the most significant stage position of said shift register for deriving from said network a discrete analog approximation of information represented by said signal train. 12. The system in accordance with claim 11 in which said ladder network is an R/2R type of resistance ladder network driven by bit-parallel outputs of said shift register. 13. The system in accordance with claim 11 in which said network includes input connections comprising first selectively actuatable means for coupling to said ladder network true outputs of said shift register stages, second selectively actuatable means for coupling to said ladder network complement outputs of said shift register stages. means for extracting from the least significant bit stage of said shift register a signal indicating a predetermined binary signal state therein, and means, responsive to different states of said indicating signal, for either actuating only said second selectively actuatable means or both actuating said first selectively actuatable means and forcing said second selectively actuatable means to a predetermined signal state for providing a corresponding fixed pedestal signal to said ladder network. 14. The system in accordance with claim 13 in which said ladder network includes a resistor connected between ground and the least significant bit end of said network, and said first selectively actuatable means includes mEans, responsive to actuation of such first selectively actuatable means, for supplying in parallel with said grounded resistor a signal of a magnitude which is sufficient to establish said pedestal at a small positive value. 15. The system in accordance with claim 9 in which there are provided in said accumulating means means, responsive to a binary ONE signal state in a most significant bit stage of said register, for forcing said register to shift from the most significant stage toward the least significant stage. 16. The system in accordance with claim 9 in which there are provided in said accumulating means means for selectably inverting the signal state of said pulse coded signal train, and means, responsive to a predetermined signal state of the least significant bit stage of said shift register in coincidence with a signal state in said signal train directing a shift toward said stage, for actuating said inverting means. 17. The system in accordance with claim 9 in which there are provided an additional reversible shift register having an input connection for application of shift clock signals in synchronism with said signal train, and means, responsive to said pulse coded signal train, for controlling shifting direction in said additional shift register whereby the contents of said additional shift register comprise a binary coded representation of the analog information underlying said signal train. 18. The system in accordance with claim 9 in which there are provided in combination with said decoding means means for producing a difference error signal in response to a continuous analog signal and said discrete analog approximation signal, and means, responsive to said error signal, for producing said pulse coded signal train to represent variations in said error signal. 19. The system in accordance with claim 18 in which said pulse coded signal train producing means comprises means for integrating said error signal, and means, periodically enabled at said signal train bit rate, for producing an output pulse in response to at least a predetermined threshold amplitude of an output of said integrating means. 20. The system in accordance with claim 19 in which said integrating means includes means for establishing an integrating response characteristic in said integrating means over a frequency band extending approximately from low frequencies of a frequency band of interest in said continuous analog signal to the frequency at which said producing means are periodically enabled. 21. The system in accordance with claim 18 in which said signal train producing means has a predetermined input signal amplitude threshold which must be attained to produce a pulse in said train, said threshold being subject to a predetermined range of variation in amplitude, and said error signal producing means includes means for providing sufficient gain to said analog approximation so that a step of the smallest size in said approximation produces in said error signal a change that is much greater than said variation range. 22. The system in accordance with claim 18 in which said shift register accumulates a digital approximation of said continuous analog signal in response to said pulse coded signal train, and means are provided for complementing said signal train in response to a change in polarity of said digital approximation. 23. The system in accordance with claim 22 in which said complementary means comprises means, responsive to coincidence of a binary ZERO in the least significant bit stage of said register and of a signal state in said signal train directing said register to shift its contents toward said least significant bit stage, for producing a polarity change signal, and means for inverting said signal train in response to said polarity change signal, and said deriving means includes means, responsive to said polarity change signal, for changing polarity of said analog approximation. 24. The system in accordance with claim 23 in which there are provided means for biasing the continuous analog signal input and the analog approximation signal input of said error signal producing means toward opposite polarity states, and means responsive to said polarity change signal to control said biasing means for fixing the relative polarities of said opposite polarity states. 25. The system in accordance with claim 18 in which there are provided a further reversible shift register having an input connection for application of shift clock signals in synchronism with said signal train, means responsive to said pulse coded signal train for controlling shifting direction in said further shift register, and means responsive to outputs of said further shift register for producing a further approximation of said analog signal. |
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