专利检索_ 涉及A/D或D/A转换的索引专利检索_ 涉及A/D或D/A转换的索引专利检索查询

子分类：

序号	专利名	申请号	申请日	公开（公告）号	公开（公告）日	发明人
1	ANALOGUE-TO-DIGITAL CONVERTER	US15663411	2017-07-28	US20170346501A1	2017-11-30	John Paul LESSO; Emmanuel Philippe Christian HARDY
This application relates to analogue-to-digital converters (ADCs). An ADC 200 has a first converter (201) for receiving an analogue input signal (AIN) and outputting a time encode signal (DT), such as a pulse-width-modulated (PWM) signal, based on input signal and a first conversion gain setting (GIN). In some embodiments the first converter has a PWM modulator (401) for generating a PWM signal such that the input signal is encoded by pulse widths that can vary continuously in time. A second converter (202) receives the time encoded signal and outputs a digital output signal (DOUT) based on the time encoded signal (DT) and a second conversion gain setting (GO). The second converter may have a first PWM-to-digital modulator (403). A gain allocation block (204) generates the first and second conversion gain settings based on the time encoded signal (DT). The gain allocation block (204) may have a second PWM-to-digital modulator (203) which may be of lower latency and/or lower resolution that the first PWM-to-digital modulator (403).
2	Analogue-to-digital converter	US15243305	2016-08-22	US09748971B2	2017-08-29	John Paul Lesso; Emmanuel Philippe Christian Hardy
This application relates to analogue-to-digital converters (ADCs). An ADC 200 has a first converter (201) for receiving an analogue input signal (AIN) and outputting a time encode signal (DT), such as a pulse-width-modulated (PWM) signal, based on input signal and a first conversion gain setting (GIN). In some embodiments the first converter has a PWM modulator (401) for generating a PWM signal such that the input signal is encoded by pulse widths that can vary continuously in time. A second converter (202) receives the time encoded signal and outputs a digital output signal (DOUT) based on the time encoded signal (DT) and a second conversion gain setting (GO). The second converter may have a first PWM-to-digital modulator (403). A gain allocation block (204) generates the first and second conversion gain settings based on the time encoded signal (DT). The gain allocation block (204) may have a second PWM-to-digital modulator (203) which may be of lower latency and/or lower resolution that the first PWM-to-digital modulator (403).
3	Analogue-to-digital converter	US15663411	2017-07-28	US09923574B2	2018-03-20	John Paul Lesso; Emmanuel Philippe Christian Hardy
This application relates to analog-to-digital converters (ADCs). An ADC 200 has a first converter (201) for receiving an analog input signal (AIN) and outputting a time encode signal (DT), such as a pulse-width-modulated (PWM) signal, based on input signal and a first conversion gain setting (GIN). In some embodiments the first converter has a PWM modulator (401) for generating a PWM signal such that the input signal is encoded by pulse widths that can vary continuously in time. A second converter (202) receives the time encoded signal and outputs a digital output signal (DOUT) based on the time encoded signal (DT) and a second conversion gain setting (GO). The second converter may have a first PWM-to-digital modulator (403). A gain allocation block (204) generates the first and second conversion gain settings based on the time encoded signal (DT). The gain allocation block (204) may have a second PWM-to-digital modulator (203) which may be of lower latency and/or lower resolution that the first PWM-to-digital modulator (403).
4	ANALOGUE-TO-DIGITAL CONVERTER	US14931332	2015-11-03	US20160126968A1	2016-05-05	John Paul Lesso; Emmanuel Philippe Christian Hardy
This application relates to analogue-to-digital converters (ADCs). An ADC 200 has a first converter (201) for receiving an analogue input signal (AIN) and outputting a time encode signal (DT), such as a pulse-width-modulated (PWM) signal, based on input signal and a first conversion gain setting (GIN). In some embodiments the first converter has a PWM modulator (401) for generating a PWM signal such that the input signal is encoded by pulse widths that can vary continuously in time. A second converter (202) receives the time encoded signal and outputs a digital output signal (DOUT) based on the time encoded signal (DT) and a second conversion gain setting (GO). The second converter may have a first PWM-to-digital modulator (403). A gain allocation block (204) generates the first and second conversion gain settings based on the time encoded signal (DT). The gain allocation block (204) may have a second PWM-to-digital modulator (203) which may be of lower latency and/or lower resolution that the first PWM-to-digital modulator (403).
5	ANALOGUE-TO-DIGITAL CONVERTER	US15878907	2018-01-24	US20180152198A1	2018-05-31	John Paul LESSO; Emmanuel Philippe Christian HARDY
This application relates to analogue-to-digital converters (ADCs). An ADC 200 has a first converter (201) for receiving an analogue input signal (AIN) and outputting a time encode signal (DT), such as a pulse-width-modulated (PWM) signal, based on input signal and a first conversion gain setting (GIN). In some embodiments the first converter has a PWM modulator (401) for generating a PWM signal such that the input signal is encoded by pulse widths that can vary continuously in time. A second converter (202) receives the time encoded signal and outputs a digital output signal (DOUT) based on the time encoded signal (DT) and a second conversion gain setting (GO). The second converter may have a first PWM-to-digital modulator (403). A gain allocation block (204) generates the first and second conversion gain settings based on the time encoded signal (DT). The gain allocation block (204) may have a second PWM-to-digital modulator (203) which may be of lower latency and/or lower resolution that the first PWM-to-digital modulator (403).
6	ANALOGUE-TO-DIGITAL CONVERTER	US15243305	2016-08-22	US20160359500A1	2016-12-08	John Paul LESSO; Emmanuel Philippe Christian HARDY
This application relates to analogue-to-digital converters (ADCs). An ADC 200 has a first converter (201) for receiving an analogue input signal (AIN) and outputting a time encode signal (DT), such as a pulse-width-modulated (PWM) signal, based on input signal and a first conversion gain setting (GIN). In some embodiments the first converter has a PWM modulator (401) for generating a PWM signal such that the input signal is encoded by pulse widths that can vary continuously in time. A second converter (202) receives the time encoded signal and outputs a digital output signal (DOUT) based on the time encoded signal (DT) and a second conversion gain setting (GO). The second converter may have a first PWM-to-digital modulator (403). A gain allocation block (204) generates the first and second conversion gain settings based on the time encoded signal (DT). The gain allocation block (204) may have a second PWM-to-digital modulator (203) which may be of lower latency and/or lower resolution that the first PWM-to-digital modulator (403).
7	Analogue-to-digital converter	US14931332	2015-11-03	US09425813B2	2016-08-23	John Paul Lesso; Emmanuel Philippe Christian Hardy
This application relates to analogue-to-digital converters (ADCs). An ADC 200 has a first converter (201) for receiving an analogue input signal (AIN) and outputting a time encode signal (DT), such as a pulse-width-modulated (PWM) signal, based on input signal and a first conversion gain setting (GIN). In some embodiments the first converter has a PWM modulator (401) for generating a PWM signal such that the input signal is encoded by pulse widths that can vary continuously in time. A second converter (202) receives the time encoded signal and outputs a digital output signal (DOUT) based on the time encoded signal (DT) and a second conversion gain setting (GO). The second converter may have a first PWM-to-digital modulator (403). A gain allocation block (204) generates the first and second conversion gain settings based on the time encoded signal (DT). The gain allocation block (204) may have a second PWM-to-digital modulator (203) which may be of lower latency and/or lower resolution that the first PWM-to-digital modulator (403).
8	개선된 아날로그-디지털 변환기	KR1020177014929	2015-10-29	KR1020170097642A	2017-08-28	레소,존폴; 하디,엠마뉴엘
본출원은아날로그-디지털변환기(ADC)들에관한것이다. ADC(200)는아날로그입력신호(AIN)를수신하고, 입력신호및 제1 변환이득설정(GIN)에기초하여, 펄스폭 변조(PWM) 신호와같은, 시간인코딩된신호(DT)를출력하는제1 변환기(201)를갖는다. 일부실시예들에서, 제1 변환기는입력신호가시간상으로연속적으로변할수 있는펄스폭들에의해인코딩되도록 PWM 신호를발생시키는 PWM 변조기(401)를갖는다. 제2 변환기(202)는시간인코딩된신호를수신하고시간인코딩된신호(DT) 및제2 변환이득설정(GO)에기초하여디지털출력신호(DOUT)를출력한다. 제2 변환기는제1 PWM-디지털변조기(403)를가질수 있다. 이득할당블록(204)은시간인코딩된신호(DT)에기초하여제1 및제2 변환이득설정들을발생시킨다. 이득할당블록(204)은제1 PWM-디지털변조기(403)보다더 낮은지연시간및/또는더 낮은분해능을가질수 있는제2 PWM-디지털변조기(203)를가질수 있다.

该功能需要专业版企业版VIP权限，您可以：