| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 1 | Systems and methods for error correction in structured light | US14820419 | 2015-08-06 | US09948920B2 | 2018-04-17 | James Wilson Nash; Kalin Mitkov Atanassov; Sergiu Radu Goma |
| Systems and methods for error correction in structured light are disclosed. In one aspect, a method includes receiving, via a receiver sensor, a structured light image of at least a portion of a composite code mask encoding a plurality of codewords, the image including an invalid codeword. The method further includes detecting the invalid codeword. The method further includes generating a plurality of candidate codewords based on the invalid codeword. The method further includes selecting one of the plurality of candidate codewords to replace the invalid codeword. The method further includes generating a depth map for an image of the scene based on the selected candidate codeword. The method further includes generating a digital representation of a scene based on the depth map. The method further includes outputting the digital representation of the scene to an output device. | ||||||
| 2 | FLASH MEMORY CODEWORD ARCHITECTURES | US15408508 | 2017-01-18 | US20170123895A1 | 2017-05-04 | Charles J. Camp; Timothy J. Fisher; Aaron D. Fry; Lincoln T. Simmons; Adalberto G. Yanes |
| A flash memory codeword architecture is provided. A non-integer count of logical pages is packed into a codeword payload data container. A codeword payload header is generated. The codeword payload header includes an offset to a first logical page that is packed, at least in part, into the codeword payload data container. The codeword payload data container and the codeword payload header are concatenated to generate a codeword payload. Error-correcting code data is generated based, at least in part, on the codeword payload using a systematic error-correcting code. The codeword payload and error-correcting code data is concatenated to generate a codeword. A physical page is programmed with the codeword. | ||||||
| 3 | Early de-allocation of write buffer in an SSD | US14090596 | 2013-11-26 | US09170939B1 | 2015-10-27 | Justin Jones; Andrew J. Tomlin; Rodney N. Mullendore; Radoslav Danilak |
| A data storage system includes: non-volatile solid state memory including non-volatile storage units and a temporary register; a data storage controller configured to receive a write command including a plurality of logical segments of data from a host; a write buffer allocated to receive a portion of the plurality of logical segments of data and accumulate a physical segment of data corresponding to a write unit of the solid state memory; a solid state memory controller configured to transmit the accumulated data from the write buffer to the temporary storage register each time the write buffer accumulates a physical segment of data. The data storage controller acknowledges completion of the write command to the host after the last logical segment of data is written to the write buffer; and deallocates the write buffer after the solid state memory completes reception of the accumulated data into the temporary storage register. | ||||||
| 4 | 構造化光における誤り訂正のためのシステムおよび方法 | JP2017545343 | 2016-02-11 | JP2018509617A | 2018-04-05 | ナッシュ、ジェームズ・ウィルソン; アタナソフ、カリン・ミトコフ; ゴマ、セルジュ・ラドゥ |
| 構造化光における誤り訂正のためのシステムおよび方法が開示される。一態様では、方法は、受信機センサーを介して、複数のコードワードを符号化する複合コードマスクの少なくとも一部分の構造化光画像を受信することを含み、画像は無効コードワードを含む。本方法は、無効コードワードを検出することをさらに含む。本方法は、無効コードワードに基づいて複数の候補コードワードを生成することをさらに含む。本方法は、無効コードワードを置き換えるために、複数の候補コードワードのうちの1つを選択することをさらに含む。本方法は、選択された候補コードワードに基づいてシーンの画像のための深度マップを生成することをさらに含む。本方法は、深度マップに基づいてシーンのデジタル表現を生成することをさらに含む。本方法は、出力デバイスにシーンのデジタル表現を出力することをさらに含む。 | ||||||
| 5 | 構造化光における誤り訂正のためのシステムおよび方法 | JP2017545343 | 2016-02-11 | JP6419988B2 | 2018-11-07 | ナッシュ、ジェームズ・ウィルソン; アタナソフ、カリン・ミトコフ; ゴマ、セルジュ・ラドゥ |
| 6 | SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF | US15686188 | 2017-08-25 | US20180190366A1 | 2018-07-05 | Jung-Ho LIM |
| A semiconductor memory device may include a memory core unit including a plurality of memory cells suitable for storing data, an error correction code (ECC) control unit suitable for detecting an error of the data to output a flag signal corresponding to a result of detection of the error, and an address control unit suitable for adjusting a refresh interval of at least one memory cell that stores data in which the error is detected, or repairing the memory cell among the memory cells, in response to the flag signal. | ||||||
| 7 | Validation bits and offsets to represent logical pages split between data containers | US15408476 | 2017-01-18 | US09875153B2 | 2018-01-23 | Charles J. Camp; Timothy J. Fisher; Aaron D. Fry; Lincoln T. Simmons; Adalberto G. Yanes |
| A flash memory codeword architecture is provided. A non-integer count of logical pages is packed into a codeword payload data container. A codeword payload header is generated. The codeword payload header includes an offset to a first logical page that is packed, at least in part, into the codeword payload data container. The codeword payload data container and the codeword payload header are concatenated to generate a codeword payload. Error-correcting code data is generated based, at least in part, on the codeword payload using a systematic error-correcting code. The codeword payload and error-correcting code data is concatenated to generate a codeword. A physical page is programmed with the codeword. | ||||||
| 8 | Validation bits and offsets to represent logical pages split between data containers | US15408508 | 2017-01-18 | US09811419B2 | 2017-11-07 | Charles J. Camp; Timothy J. Fisher; Aaron D. Fry; Lincoln T. Simmons; Adalberto G. Yanes |
| A flash memory codeword architecture is provided. A non-integer count of logical pages is packed into a codeword payload data container. A codeword payload header is generated. The codeword payload header includes an offset to a first logical page that is packed, at least in part, into the codeword payload data container. The codeword payload data container and the codeword payload header are concatenated to generate a codeword payload. Error-correcting code data is generated based, at least in part, on the codeword payload using a systematic error-correcting code. The codeword payload and error-correcting code data is concatenated to generate a codeword. A physical page is programmed with the codeword. | ||||||
| 9 | FLASH MEMORY CODEWORD ARCHITECTURES | US14829924 | 2015-08-19 | US20170052844A1 | 2017-02-23 | Charles J. Camp; Timothy J. Fisher; Aaron D. Fry; Lincoln T. Simmons; Adalberto G. Yanes |
| A flash memory codeword architecture is provided. A non-integer count of logical pages is packed into a codeword payload data container. A codeword payload header is generated. The codeword payload header includes an offset to a first logical page that is packed, at least in part, into the codeword payload data container. The codeword payload data container and the codeword payload header are concatenated to generate a codeword payload. Error-correcting code data is generated based, at least in part, on the codeword payload using a systematic error-correcting code. The codeword payload and error-correcting code data is concatenated to generate a codeword. A physical page is programmed with the codeword. | ||||||
| 10 | Early de-allocation of write buffer in an SSD | US14887672 | 2015-10-20 | US09471242B2 | 2016-10-18 | Justin Jones; Andrew J. Tomlin; Rodney N. Mullendore; Radoslav Danilak |
| A data storage system includes: non-volatile solid state memory including non-volatile storage units and a temporary register; a data storage controller configured to receive a write command including a plurality of logical segments of data from a host; a write buffer allocated to receive a portion of the plurality of logical segments of data and accumulate a physical segment of data corresponding to a write unit of the solid state memory; a solid state memory controller configured to transmit the accumulated data from the write buffer to the temporary storage register each time the write buffer accumulates a physical segment of data. The data storage controller acknowledges completion of the write command to the host after the last logical segment of data is written to the write buffer; and deallocates the write buffer after the solid state memory completes reception of the accumulated data into the temporary storage register. | ||||||
| 11 | Semiconductor memory device and operating method thereof | US15686188 | 2017-08-25 | US10062452B2 | 2018-08-28 | Jung-Ho Lim |
| A semiconductor memory device may include a memory core unit including a plurality of memory cells suitable for storing data, an error correction code (ECC) control unit suitable for detecting an error of the data to output a flag signal corresponding to a result of detection of the error, and an address control unit suitable for adjusting a refresh interval of at least one memory cell that stores data in which the error is detected, or repairing the memory cell among the memory cells, in response to the flag signal. | ||||||
| 12 | Validation bits and offsets to represent logical pages split between data containers | US14829924 | 2015-08-19 | US09946594B2 | 2018-04-17 | Charles J. Camp; Timothy J. Fisher; Aaron D. Fry; Lincoln T. Simmons; Adalberto G. Yanes |
| A flash memory codeword architecture is provided. A non-integer count of logical pages is packed into a codeword payload data container. A codeword payload header is generated. The codeword payload header includes an offset to a first logical page that is packed, at least in part, into the codeword payload data container. The codeword payload data container and the codeword payload header are concatenated to generate a codeword payload. Error-correcting code data is generated based, at least in part, on the codeword payload using a systematic error-correcting code. The codeword payload and error-correcting code data is concatenated to generate a codeword. A physical page is programmed with the codeword. | ||||||
| 13 | FLASH MEMORY CODEWORD ARCHITECTURES | US15408476 | 2017-01-18 | US20170123893A1 | 2017-05-04 | Charles J. Camp; Timothy J. Fisher; Aaron D. Fry; Lincoln T. Simmons; Adalberto G. Yanes |
| A flash memory codeword architecture is provided. A non-integer count of logical pages is packed into a codeword payload data container. A codeword payload header is generated. The codeword payload header includes an offset to a first logical page that is packed, at least in part, into the codeword payload data container. The codeword payload data container and the codeword payload header are concatenated to generate a codeword payload. Error-correcting code data is generated based, at least in part, on the codeword payload using a systematic error-correcting code. The codeword payload and error-correcting code data is concatenated to generate a codeword. A physical page is programmed with the codeword. | ||||||
| 14 | Flash memory codeword architectures | US15014434 | 2016-02-03 | US09483350B1 | 2016-11-01 | Charles J. Camp; Timothy J. Fisher; Aaron D. Fry; Lincoln T. Simmons; Adalberto G. Yanes |
| A flash memory codeword architecture is provided. A non-integer count of logical pages is packed into a codeword payload data container. A codeword payload header is generated. The codeword payload header includes an offset to a first logical page that is packed, at least in part, into the codeword payload data container. The codeword payload data container and the codeword payload header are concatenated to generate a codeword payload. Error-correcting code data is generated based, at least in part, on the codeword payload using a systematic error-correcting code. The codeword payload and error-correcting code data is concatenated to generate a codeword. A physical page is programmed with the codeword. | ||||||
| 15 | SYSTEMS AND METHODS FOR ERROR CORRECTION IN STRUCTURED LIGHT | US14820419 | 2015-08-06 | US20160255332A1 | 2016-09-01 | James Wilson Nash; Kalin Mitkov Atanassov; Sergiu Radu Goma |
| Systems and methods for error correction in structured light are disclosed. In one aspect, a method includes receiving, via a receiver sensor, a structured light image of at least a portion of a composite code mask encoding a plurality of codewords, the image including an invalid codeword. The method further includes detecting the invalid codeword. The method further includes generating a plurality of candidate codewords based on the invalid codeword. The method further includes selecting one of the plurality of candidate codewords to replace the invalid codeword. The method further includes generating a depth map for an image of the scene based on the selected candidate codeword. The method further includes generating a digital representation of a scene based on the depth map. The method further includes outputting the digital representation of the scene to an output device. | ||||||
| 16 | EARLY DE-ALLOCATION OF WRITE BUFFER IN AN SSD | US14887672 | 2015-10-20 | US20160041790A1 | 2016-02-11 | Justin JONES; Andrew J. TOMLIN; Rodney N. MULLENDORE; Radoslav DANILAK |
| A data storage system includes: non-volatile solid state memory including non-volatile storage units and a temporary register; a data storage controller configured to receive a write command including a plurality of logical segments of data from a host; a write buffer allocated to receive a portion of the plurality of logical segments of data and accumulate a physical segment of data corresponding to a write unit of the solid state memory; a solid state memory controller configured to transmit the accumulated data from the write buffer to the temporary storage register each time the write buffer accumulates a physical segment of data. The data storage controller acknowledges completion of the write command to the host after the last logical segment of data is written to the write buffer; and deallocates the write buffer after the solid state memory completes reception of the accumulated data into the temporary storage register. | ||||||
| 17 | SYSTEMS AND METHODS FOR ERROR CORRECTION IN STRUCTURED LIGHT | EP16712104.5 | 2016-02-11 | EP3262607A1 | 2018-01-03 | NASH, James Wilson; ATANASSOV, Kalin Mitkov; GOMA, Sergiu Radu |
| Systems and methods for error correction in structured light are disclosed. In one aspect, a method includes receiving, via a receiver sensor, a structured light image of at least a portion of a composite code mask encoding a plurality of codewords, the image including an invalid codeword. The method further includes detecting the invalid codeword. The method further includes generating a plurality of candidate codewords based on the invalid codeword. The method further includes selecting one of the plurality of candidate codewords to replace the invalid codeword. The method further includes generating a depth map for an image of the scene based on the selected candidate codeword. The method further includes generating a digital representation of a scene based on the depth map. The method further includes outputting the digital representation of the scene to an output device. | ||||||
| 18 | 유전자 RNA 코드 기반 재킷 행렬을 이용한 신호 처리 방법 및 장치 | KR20160124621 | 2016-09-28 | KR20180034873A | 2018-04-05 | 이문호; 박주용; 이성국 |
| 유전자 RNA 코드기반재킷행렬을이용한신호처리방법및 장치가제공된다. 본발명의실시예에따른방법및 장치는, 유전자 RNA Code의 C(Cytosine), U(Uracil), G(Guanine), A(Adenine) 유전자코드가 Circulant 행렬을갖고있음을이용하여, Element (Block)-wise Inverse인 Jacket 행렬로적용하여신호처리하는방법을제시하였다. | ||||||
| 19 | 오디오 출력 장치 및 오디오 출력 방법 | KR1020050046262 | 2005-05-31 | KR1020060124370A | 2006-12-05 | 이명훈 |
| An audio output apparatus and a method for outputting audio sound are provided to reduce noise due to an error by detecting effectively an error in a receiving audio stream. A reception unit(100) receives an encoded audio signal. A decoder(200) receives the audio signal from the reception unit and decodes the audio signal in frame units. An error detector(500) determines the presence of a decoding error by checking a time for decoding one frame. A PCM signal storage unit(300) receives a decoded PCM signal from the decoder and stores a PCM signal in one frame unit when the decoding error is not detected by the error detector. An output unit(400) outputs an audio signal of an audible range stored in the PCM signal storage unit. | ||||||
| 20 | 양자 오류 정정 부호간 결함 허용 방식의 상호 변환 장치 및 방법 | KR1020160115723 | 2016-09-08 | KR101768595B1 | 2017-08-17 | 허준; 손일권; 황용수 |
| 본발명은양자오류정정부호간결함허용방식의상호변환장치및 방법에관한것으로, 특히변환의대상이되는양자오류정정부호들을기준형으로변환한뒤 서로를비교하여변환에필요한게이트를선택하고, 해당게이트들을적절히배치하여변환과정이양자노이즈의영향을잘 제어할수 있도록한 양자오류정정부호간결함허용방식의상호변환장치및 방법에관한것이다. 또한, 본발명에따르면, 초기양자오류정정부호와목적양자오류정정부호를일반형에서표준형으로변환하는표준형변환기; 초기양자오류정정부호와목적양자오류정정부호를표준형에서기준형으로변환하는기준형변환기; 기준형으로변환된초기양자오류정정부호와목적양자오류정정부호를비교하여양자연산자들을선정하는양자연산자선정기; 선정된양자연산자들을배치하여양자회로를설계하는양자회로설계기; 및설계된양자회로를초기양자오류정정부호에적용하여목적양자오류정정부호를산출하는양자변환기를포함하는양자오류정정부호간결함허용방식의상호변환장치및 방법을제공한다. | ||||||
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