| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 241 | Wireless communication device and wireless communication method | JP2011534001 | 2009-09-30 | JP5344045B2 | 2013-11-20 | 哲也 矢野; 義博 河▲崎▼; 良紀 田中; 俊治 宮崎 |
| In a wireless communication method, a first wireless communication apparatus transmits through a first wireless resource to a second wireless communication apparatus a first signal generated from a second signal for use in processing performed by the second wireless communication apparatus and a third signal for use in error checking of the second signal. The second wireless communication apparatus detects a second wireless resource to be used in the processing on the basis of the first signal, and performs the processing by using the second signal and the detected second wireless resource. For the detection, a section of the first signal corresponding to the second wireless resource is scrambled, or the first signal is scrambled with a scrambling sequence corresponding to the second wireless resource, or the bit order in at least part of the first signal is changed in a manner corresponding to the second wireless resource. | ||||||
| 242 | A method and apparatus for decoding Raptor code | JP2008554272 | 2007-01-31 | JP5237119B2 | 2013-07-17 | ガオ，ウェン |
| 243 | Memory controller, data storage device, and memory control method | JP2011289074 | 2011-12-28 | JP2013137708A | 2013-07-11 | SAKATA AKIHIRO; KIMURA YOSHINOBU |
| PROBLEM TO BE SOLVED: To provide a memory controller capable of performing an error detection of all routes from inputting data to outputting the data to a host.SOLUTION: The memory controller includes: a first error detection code generating unit that generates a first error detection code to data received from a host; a control unit that performs a control to writing data and the first error detection code in a memory, and when there is a read request, reads the data and the first error detection code from the memory; an error detection unit that performs error detection processing on the basis of the data and the first error detection code read from the memory; a second error detection code generating unit that generates a second error detection code on the basis of the data read from the memory; and an unconformity code generating unit that generates an unconformity code representing that there is an error in the data. The memory controller selects and adds at least one of the second error detection code and the unconformity code to data to be transmitted to the host, on the basis of the error detection result by the error detection processing. | ||||||
| 244 | 無線通信装置および無線通信方法 | JP2011534001 | 2009-09-30 | JPWO2011039862A1 | 2013-02-21 | 矢野 哲也; 哲也 矢野; 義博 河▲崎▼; 田中 良紀; 良紀 田中; 宮崎 俊治; 俊治 宮崎 |
| 複数の無線リソースから選択される処理対象の無線リソースを効率的に通信相手に通知できるようにする。無線通信装置(1)は、無線リソース(3a)で、無線リソース(3b,3c,3d)の何れかに対する処理に用いる信号#1と誤り検出に用いる信号#2とから生成される信号#3を送信する。無線通信装置(2)は、信号#3に基づいて無線リソース(3b,3c,3d)のうち対象リソースを検出し、対象リソースに対して信号#1を用いた処理を行う。対象リソースを識別する方法には、信号#3を対象リソースに応じた区間だけスクランブル処理する、対象リソースに応じたスクランブル系列を用いてスクランブル処理する、対象リソースに応じた入れ替え方法でビット順序を入れ替える、という方法が含まれる。 | ||||||
| 245 | Processing apparatus and method of turbo stream | JP2008536511 | 2006-10-20 | JP5116685B2 | 2013-01-09 | ユー，ジョン−ピル; パク，ウィ−ジュン; クォン，ヨン−シク; チャン，ヨン−ドク; ジョン，ヘ−ジュー; キム，ジュン−スー; ジョン，ジン−ヒ; ジ，クム−ラン; キム，ジョン−フン |
| 246 | Communication system and method | JP2012507813 | 2010-04-29 | JP2012525753A | 2012-10-22 | アイドゥンリック，モメット; ブディン，ダン |
| 直列連接復号化を実行するためのシステム、方法及び製造物が図示及び説明される。 復号化は、アウター復号化中に複数のデータブロックに行った訂正数の指標をモニタし、最適インナー復号化が適用されるときに直列連接復号化を実行するプロセッサが受ける計算負荷と比較して、次善インナー復号化の適用がプロセッサが受ける計算負荷を低減するか判断することを含む。 | ||||||
| 247 | Method and device for providing unequal error protection code of the design from the code of stochastically constant composition | JP2011538193 | 2010-02-15 | JP2012519982A | 2012-08-30 | コッシュネビス アーマッド; チョードリー サヤンタン; イン ジャンペン; エム．コワルスキー ジョン; ジェン リジョン; 公彦 今村 |
| エラーに対する異なるレベルのロバスト性を有するデータを符号化および復号化するために線形エンコーダおよび線形デコーダのような標準的なコーデックを用いる符号化の方法が記述されている。 ある構成においては、複数のエンコーダが利用されてもよく、上記エンコーダの１つは、符号の２進数表現における１および０の不均等分布を生成する非線形性を伴っているターボ符号のような標準的なエンコーダを用いてもよい。 他の構成においては、メッセージ出力を、データ順方向誤り訂正コーダにおける状態遷移（またはシンボルエラー）を生成する「通信路」として表すコーダが用いられてもよい。 データの符号化および復号化は、無線通信デバイスにより実行可能である。 | ||||||
| 248 | Interleaving method | JP2008507282 | 2006-03-24 | JP4846785B2 | 2011-12-28 | 隆彦 中村; 英夫 吉田 |
| 249 | Method for encoding and decoding side information for multimedia transmission, apparatus and system | JP2006507516 | 2004-03-23 | JP4814081B2 | 2011-11-09 | ガルダドリ、ハリナス; ラムチャンドラン、カンナン |
| 250 | Method and system for code combining at an external decoder on a communication system | JP2005501708 | 2003-10-24 | JP4805672B2 | 2011-11-02 | ウェイ、ヨンビン; チェン、タオ; ティーデマン、エドワード・ジー・ジュニア |
| 251 | Method and device for encoding of error correcting codes, and method and device for decoding of error correcting codes | JP2010006142 | 2010-01-14 | JP2011146932A | 2011-07-28 | MIYATA YOSHIKUNI; YOSHIDA HIDEO; KUBO KAZUO; MIZUOCHI TAKASHI |
| PROBLEM TO BE SOLVED: To improve processing throughput, and to enhance error correction capability. SOLUTION: A device for encoding of error correcting codes includes: an outer encoding circuit 33 for performing encoding processing for an outer code; and an inner encoding circuit 34 for performing encoding processing for an inner code, and further includes an inner-encoding input circuit 54 for performing interleaving processing in which a parallel input sequence is sorted into specific lanes, and a specific barrel shift is performed for each inner frame. By carrying out interleaving in which the parallel input sequence is sorted into the specific lanes, and the specific barrel shift is performed for each inner frame, allocation of an information sequence area and a parity sequence area is uniformized, to improve processing throughput and enhance error correction capability. COPYRIGHT: (C)2011,JPO&INPIT | ||||||
| 252 | Decoder, a method of data storage device and the data of the error correction | JP2005042272 | 2005-02-18 | JP4733403B2 | 2011-07-27 | ジャスティン・コラー; マット・ボール |
| 253 | Method and system for code combining at outer decoder on communication system | JP2010188410 | 2010-08-25 | JP2011024239A | 2011-02-03 | WEI YONGBIN; CHEN TAO; TIEDEMANN EDWARD G JR |
| PROBLEM TO BE SOLVED: To provide a method and system for code combining at an outer decoder on a communication system. SOLUTION: An outer encoder 612 and inner encoders 622, 632 encode subsets of information to be transmitted, to improve protection by adding redundancy. The redundancy permits decoding of the information from less than a complete encoded block of information. The use of a combiner 644 at an outer decoder 648 enables better outer decoding of symbols. COPYRIGHT: (C)2011,JPO&INPIT | ||||||
| 254 | Method of recording data, recording medium, and reproduction apparatus | JP2010194518 | 2010-08-31 | JP2011018436A | 2011-01-27 | TAKAGI YUJI; USUI MAKOTO; YABUNO HIROYUKI |
| PROBLEM TO BE SOLVED: To solve such a problem that in conventional data recording method in which two error correction codes and a synchronous signal are recorded by the prescribed interleave rule, reliability of a signal in which both sides are held between constitution symbols of a second error correction code of which the error detection capability is low is more inferior than a signal held between the synchronous signal and the second error correction code caused by difference of error detection performance, then, a whole reliability is limited by a signal of the lowest reliability.SOLUTION: Such data stream is constituted that it includes a first error correction code having first correction capability in which user data is encoded, a second error correction code having second correction capability which is higher than the first correction capability in which control information is encoded, and the synchronous signal, wherein the second error correction code and the synchronous signal are interleaved alternately for the first error correction code. | ||||||
| 255 | Error detection code calculation circuit, error detection code calculation method and a recording apparatus | JP2005226705 | 2005-08-04 | JP4620541B2 | 2011-01-26 | 剛生 有山 |
| 256 | Multi-dimensional block encoder with sub-block interleaver and deinterleaver | JP2007507287 | 2004-04-09 | JP4551445B2 | 2010-09-29 | リン，シャオトン |
| 257 | Encoding and decoding technology for packet recovery | JP2006182985 | 2006-07-03 | JP4392004B2 | 2009-12-24 | 大樹 中野; 泰尚 片山 |
| 258 | Transmission format detection method | JP2002504031 | 2000-06-21 | JP4350371B2 | 2009-10-21 | 誠 内島; 一央 大渕; 哲也 矢野 |
| 259 | ecc system to generate the crc syndrome against random data in the computer storage device | JP32462398 | 1998-11-16 | JP4346135B2 | 2009-10-21 | ゾック クリストファー |
| 260 | Semiconductor storage device, its control method, and error correction system | JP2008051419 | 2008-02-29 | JP2009211209A | 2009-09-17 | YAMAYA AKIRA |
| PROBLEM TO BE SOLVED: To provide a semiconductor device, its control method and an error correction system for reducing power consumption and a circuit scale without damaging any error correction capability. SOLUTION: The ECC circuit 40 of an SSD 100 performs first error correction on read data using a first error correction code (Hamming code), and further performs second error correction on the result of the first error correction using a second error correction code (BHC code). Furthermore, the ECC circuit performs third error correction on the result of the second error correction using a third error correction code (RS code). COPYRIGHT: (C)2009,JPO&INPIT | ||||||
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