序号 专利名 申请号 申请日 公开(公告)号 公开(公告)日 发明人
241 通信システムにおけるオブジェクトのブロックアグリゲーション JP2014241844 2014-11-28 JP2015084540A 2015-04-30 マイケル・ジー.・ルビー; マーク・ワトソン
【課題】FEC(順方向誤り訂正)復号を効率的に実行する方法を提供する。
【解決手段】ソースシンボルにm個の個々のオブジェクトをマッピングする際、m個の個々のオブジェクトをアグリゲートオブジェクトにアグリゲートする。順方向誤り訂正符号化のためにアグリゲートオブジェクトをZ個のソースブロックへと分割する。分割に際し、Z個のソースブロックの第1のソースブロック内の各個々のオブジェクトjのソースシンボルの第1の数NSS(j,k)を計算することと、Z個のソースブロックの第2のソースブロック内の各個々のオブジェクトjのソースシンボルの第2の数NSS(j,k)を計算すること、を含む。ここで、各個々のオブジェクトjについてのS(j)ソースシンボルは、NSS(j,k)>0についての最初のソースブロックから始まりNSS(j,k)>0の最後のソースブロックまでの、連続ソースブロックk内で連続的に並べられる。
【選択図】図2
242 通信システムにおけるオブジェクトのブロックアグリゲーション JP2012556247 2011-03-03 JP5694390B2 2015-04-01 ルビー、マイケル・ジー.; ワトソン、マーク
243 Optical transmission equipment and optical transmission method JP2009108876 2009-04-28 JP5502363B2 2014-05-28 和夫 久保; 隆司 水落; 英夫 吉田; 好邦 宮田
244 A system and method for transferring electronic information efficiently JP2009137205 2009-06-08 JP5476803B2 2014-04-23 カルピオ フレデリック; ゲオルギス ニコラオス; フレーザー ミルトン
245 Data conversion method, data conversion device and data conversion program JP2012147390 2012-06-29 JP2014010670A 2014-01-20 HANEDA MITSUMASA
PROBLEM TO BE SOLVED: To reduce an error rate of a recording medium.SOLUTION: A data conversion device 101 is configured to: receive write data 200 to be written to a recording medium 110 from a host 102; count the number of pieces of data on a bit pattern P included in a data group on the basis of the data group to which the received write data 200 is divided by a specific bit number unit; associate a bit pattern serving as a conversion source selected from bit patterns P1 to Pm in a descending order of a counted count result with a bit pattern serving as a conversion destination selected from the bit patterns P1 to Pm in a descending order of the number of 1; and for each bit pattern serving as the conversion source, convert data on the bit pattern serving as the conversion source included in data d1 to dn to data on the bit pattern serving as the conversion destination associated with the bit pattern serving as the conversion source.
246 The system and method of the queue-based data detection and decoding JP2009107302 2009-04-27 JP5384187B2 2014-01-08 ヤング シャオウア; ハオ,ゾング; タン ウェイジュン; ラウチメイヤー リチャード; シン リー ユアン
247 Encoder, decoder, encoding, and decoding method JP2012511758 2010-05-18 JP5377757B2 2013-12-25 ヒ−ウォン・ジュン; スン−グン・パク; ギ−サン・イ; ジュン−ホ・コ; サン−ムク・イ; セルゲイ・ジドコフ
An encoder includes: a precoder for encoding an input information object according to a preset encoding scheme and storing the encoded information object in a precoder buffer; a sample number/address generation unit for generating a sample number of each sample and an address, which corresponds to each bit of each sample and the address of the precoder buffer; a multiplexer for selecting a bit of the precoder buffer corresponding to the address generated by the sample number/address generation module; a sampling buffer for storing a bit of each sample output from the multiplexer; a control packet generation module for generating a control packet including information on the sample number generated by the sample number/address generation module; a packet assembling unit for assembling the sample stored in the sampling buffer with the control packet generated by the control data generation module; and a modulation module for modulating the packet output from the packet assembling unit into a sound signal according to a preset scheme.
248 Data processing equipment, and data processing method JP2009543805 2008-11-26 JP5359882B2 2013-12-04 峰志 横川; 真紀子 山本
The present invention relates to a data processing apparatus and a data processing method which can improve the tolerance to errors of code bits of an LDPC code such as burst errors or erasure. Where one symbol is formed from two or more code bits of an LDPC (Low Density Parity Check) code, a column twist interleaver 24 carries out a re-arrangement process of re-arranging the code bits of the LDPC code such that a plurality of code bits corresponding to the value 1 included in one arbitrary row of a parity check matrix are not mapped to one symbol. The present invention can be applied, for example, to a transmission apparatus which transmits an LDPC code.
249 Error-correcting code for storage capacity was increased in the multi-level memory device JP2010114819 2010-05-18 JP5229591B2 2013-07-03 アマート パオロ; カンパルド ジョバンニ
Embodiments of the present disclosure provide methods, systems, and apparatuses related to multilevel encoding with error correction. In some embodiments, data may be programmed and/or read from a matrix of nonvolatile memory cells with concatenated encoding/decoding schemes. In some embodiments, a calculation module may determine an actual bit per cell value of a given combination of parameters of a nonvolatile memory device. Still other embodiments may be described and claimed.
250 Method and apparatus for error management JP2008532898 2006-09-28 JP5226519B2 2013-07-03 アレクシッチ,ミリヴォイェ; ゴーマ,セルジュ
251 Digital broadcasting system and method JP2008536518 2006-10-23 JP5221363B2 2013-06-26 ユー,ジョン−ピル; パク,ウィ−ジュン; クォン,ヨン−シク; チャン,ヨン−ドク; ジョン,ヘ−ジュー; キム,ジュン−スー; ジョン,ジン−ヒ; ジ,クム−ラン; キム,ジョン−フン
A digital broadcasting system and method, where the digital broadcasting system includes: a transmission stream generator multiplexing a normal stream and a turbo stream to generate a dual transmission stream; a transmitter inserting an supplementary reference signal (SRS) into the dual transmission stream, processing the turbo stream to reconstitute the dual transmission stream, and outputting the reconstituted dual transmission stream; and a receiver receiving the reconstituted dual transmission stream, separately turbo decoding the turbo stream, inserting the turbo decode turbo stream into the dual transmission stream, and decoding the dual transmission stream into which the turbo decoded turbo stream has been inserted, to restore normal stream data and turbo stream data. Thus, reception sensitivity of a digital broadcasting signal can be efficiently improved.
252 Forward error correction coding for the compatible multi-link transmission and 64b / 66b scrambling JP2009535047 2007-10-08 JP5106538B2 2012-12-26 デル、ティモシー、ジェイ; グレース、ルネ
253 Delivery of dynamic stream interleaving and sub-stream-based JP2010504224 2008-04-16 JP5096560B2 2012-12-12 ルビー、マイケル; パクザド、パヤム; ワトソン、マーク; ビシサノ、ロレンゾ; クリシュ、ジョルダン・ジェイ.
A communications system can provide methods of dynamically interleaving streams, including methods for dynamically introducing greater amounts of interleaving as a stream is transmitted independently of any source block structure to spread out losses or errors in the channel over a much larger period of time within the original stream than if interleaving were not introduced, provide superior protection against packet loss or packet corruption when used with FEC coding, provide superior protection against network jitter, and allow content zapping time and the content transition time to be reduced to a minimum and minimal content transition times. Streams may be partitioned into sub-streams, delivering the sub-streams to receivers along different paths through a network and receiving concurrently different sub-streams at a receiver sent from potentially different servers. When used in conjunction with FEC encoding, the methods include delivering portions of an encoding of each source block from potentially different servers.
254 Encoder, decoder, encoding, and decoding method JP2012511758 2010-05-18 JP2012527815A 2012-11-08 ギ−サン・イ; サン−ムク・イ; ジュン−ホ・コ; スン−グン・パク; セルゲイ・ジドコフ; ヒ−ウォン・ジュン
An encoder includes: a precoder for encoding an input information object according to a preset encoding scheme and storing the encoded information object in a precoder buffer; a sample number/address generation unit for generating a sample number of each sample and an address, which corresponds to each bit of each sample and the address of the precoder buffer; a multiplexer for selecting a bit of the precoder buffer corresponding to the address generated by the sample number/address generation module; a sampling buffer for storing a bit of each sample output from the multiplexer; a control packet generation module for generating a control packet including information on the sample number generated by the sample number/address generation module; a packet assembling unit for assembling the sample stored in the sampling buffer with the control packet generated by the control data generation module; and a modulation module for modulating the packet output from the packet assembling unit into a sound signal according to a preset scheme.
255 無線通信装置及び無線通信方法 JP2011510155 2010-02-17 JPWO2010122699A1 2012-10-25 吉井 勇; 勇 吉井; 岸上 高明; 高明 岸上
変調データを複数のストリームにマッピングし、これら複数のストリームを送受信する際に、伝送データにおけるストリームマッピングの偏りを軽減する。無線通信装置において、複数のストリームへのマッピングを行うストリームマッパ14は、サブブロックインタリーブ等のチャネルインタリーブを行うチャネルインタリーバ12から出されるブロック毎に、変調器13の出力の変調シンボル列を順に複数のストリームに対してマッピングする。この際、ブロックサイズに応じた所定単位ごとに、例えばサブブロックインタリーブを行うサブブロック長の位置ごと、あるいは1/2サブブロック長の位置ごとに、ストリームマッピングの方法を変更する。
256 High re-writing efficiency for multi-track recording on the magnetic tape ecc / interleaving JP2011544819 2009-11-25 JP2012514823A 2012-06-28 エレフテリウ、エヴァンゲロス; シーガー、ポール; シデシヤン、ロイ、ダロン; ミッテルホルツァー、トーマス; 久人 松尾; 啓介 田中
For writing data to multi-track tape, a received data set is received and segmented into unencoded subdata sets, each comprising an array having K2 rows and K1 columns. For each unencoded subdata set, N1-K1 C1-parity bytes are generated for each row and N2-K2 C2-parity bytes are generated for each column. The C1 and C2 parity bytes are appended to the ends of the row and column, respectively, to form encoded C1 and C2 codewords, respectively. All of the C1 codewords per data set are endowed with a specific codeword header to form a plurality of partial codeword objects (PCOs). Each PCO is mapped onto a logical data track according to information within the header. On each logical data track, adjacent PCOs are merged to form COs which are modulation encoded and mapped into synchronized COs. Then T synchronized COs are written simultaneously to the data tape where T is the number of concurrent active tracks on the data tape.
257 Receiving apparatus and a receiving method JP2007039391 2007-02-20 JP4827766B2 2011-11-30 裕人 向井; 英邦 四方; 賢徳 國枝; 聖峰 小林; 豊 村上
A reception device includes reception antennas and an address generation unit that converts a write-in or read-out order of channel estimation values according to a rearrangement rule. A storage unit writes in or reads out channel estimation values in the converted order, and an address generation unit converts a data sequence write-in or read-out order according to the rearrangement rule. A signal storage unit writes in or reads out data sequences in the converted order, and a replica generation unit generates a replica signal by re-modulating the data sequence according to the channel estimation value. A cancel unit successively generates a stream signal in which a data sequence interference signal is cancelled, by using the channel estimation value, the data sequence, and the replica signal.
258 Method and apparatus for decoding multiword information JP2009043538 2009-02-26 JP4824784B2 2011-11-30 ウー ウェン−イー; シエ ジア−ホーン; リン リー−リエン
259 無線通信移動局装置およびリソースエレメント分散配置方法 JP2010512948 2009-05-22 JPWO2009142025A1 2011-09-29 中尾 正悟; 正悟 中尾; 鈴木 秀俊; 秀俊 鈴木; 西尾 昭彦; 昭彦 西尾; 謙一 栗
移動局が複数の通信方式に適応する場合でも、移動局の回路規模の増大を最小限に抑えつつ、各通信方式で同等のダイバーシチ効果を得ることができる移動局。SC−FDMA通信またはOFDMA通信のいずれかを行う移動局(100)であって、インタリーブ部(103)は、SC−FDMA通信およびOFDMA通信のいずれが行われる場合にも、複数のコードブロックに分割される複数のリソースエレメントを複数のコードブロック間においてインタリーブする。また、OFDMA通信が行われる場合にのみ、S/P変換部(107)は、データシンボルを並列に変換してOFDMシンボルを生成する。シフト部(108)は、S/P変換部(107)から入されるOFDMシンボルに対して、OFDMシンボル毎に異なる周波数シフトを与えることで、インタリーブ後の複数のコードブロック毎の複数のリソースエレメントを周波数領域に分散配置する。
260 System and method for modulation diversity JP2010264825 2010-11-29 JP2011091834A 2011-05-06 WANG MICHAEL MAO; LING FUYUN; MURALI RAMASWAMY; VIJAYAN RAJIV
<P>PROBLEM TO BE SOLVED: To provide a system and method for modulation diversity. <P>SOLUTION: The system and method for modulation diversity uses interleaving. Code bits are placed into groups and are then shuffled within each group. An interleaver uses a bit-interleaver solely to achieve m-ary modulation diversity and uses a two-dimension interleaved interlace table and a run-time slot-to-interlace mapping to achieve frequency diversity which provides better interleaving performance without the need for explicit symbol interleaving. <P>COPYRIGHT: (C)2011,JPO&INPIT
QQ群二维码
意见反馈