| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 1 | 功率放大器 | CN201110084367.2 | 2011-03-31 | CN102208899B | 2016-06-22 | 约翰·克里斯多佛·克利夫顿 |
| 本发明公开了一种功率放大器，其包括功率放大器装置的串联堆，功率放大器装置并联连接到用于接收RF输入信号的放大器输入端，并且功率放大器的输出端子串联连接到放大器输出端。中间耦合电容器在功率放大器装置的串联堆中连接在每个相邻功率放大器装置对之间，以用于所述功率放大器装置的DC隔离。这降低了所需的DC电源电压，并且允许响应于DC电源电压中的变化，将单独的功率放大器装置短路。 | ||||||
| 2 | 放大器、放大方法以及滤波器 | CN200780001329.8 | 2007-09-04 | CN101356725B | 2011-11-09 | 饭田幸生; 吉泽淳 |
| 本发明提供一种放大器，该放大器具备：第1可变静电电容元件，其静电电容可变；第2可变静电电容元件，其静电电容可变，与第1可变静电电容元件电气连接，相对于第1可变静电电容元件为逆导电型；以及第1输入部，其对第1可变静电电容元件和第2可变静电电容元件选择性地输入偏置电压和电压信号，在对第1可变静电电容元件和第2可变静电电容元件输入偏置电压和电压信号的情况下，将第1可变静电电容元件和第2可变静电电容元件的静电电容设为第1值，将第1可变静电电容元件和第2可变静电电容元件的静电电容设为小于第1值的第2值，从而对电压信号进行放大。 | ||||||
| 3 | 功率放大器 | CN201110084367.2 | 2011-03-31 | CN102208899A | 2011-10-05 | 约翰·克里斯多佛·克利夫顿 |
| 本发明公开了一种功率放大器，其包括功率放大器装置的串联堆，功率放大器装置并联连接到用于接收RF输入信号的放大器输入端，并且功率放大器的输出端子串联连接到放大器输出端。中间耦合电容器在功率放大器装置的串联堆中连接在每个相邻功率放大器装置对之间，以用于所述功率放大器装置的DC隔离。这降低了所需的DC电源电压，并且允许响应于DC电源电压中的变化，将单独的功率放大器装置短路。 | ||||||
| 4 | 放大器、放大方法以及滤波器 | CN200780001329.8 | 2007-09-04 | CN101356725A | 2009-01-28 | 饭田幸生; 吉泽淳 |
| 本发明提供一种放大器，该放大器具备：第1可变静电电容元件，其静电电容可变；第2可变静电电容元件，其静电电容可变，与第1可变静电电容元件电气连接，相对于第1可变静电电容元件为逆导电型；以及第1输入部，其对第1可变静电电容元件和第2可变静电电容元件选择性地输入偏置电压和电压信号，在对第1可变静电电容元件和第2可变静电电容元件输入偏置电压和电压信号的情况下，将第1可变静电电容元件和第2可变静电电容元件的静电电容设为第1值，将第1可变静电电容元件和第2可变静电电容元件的静电电容设为小于第1值的第2值，从而对电压信号进行放大。 | ||||||
| 5 | Source Switched Split LNA | US15917301 | 2018-03-09 | US20180302039A1 | 2018-10-18 | Emre Ayranci; Miles Sanner |
| A receiver front end capable of receiving and processing intraband non-contiguous carrier aggregate (CA) signals using multiple low noise amplifiers (LNAs) is disclosed herein. A cascode having a “common source” configured input FET and a “common gate” configured output FET can be turned on or off using the gate of the output FET. A first switch is provided that allows a connection to be either established or broken between the source terminal of the input FET of each LNA. Further switches used for switching degeneration inductors, gate capacitors and gate to ground caps for each legs can be used to further improve the matching performance of the invention. | ||||||
| 6 | Integrated Circuit Arrangement for a Microphone, Microphone System and Method for Adjusting One or More Circuit Parameters of the Microphone System | US15548371 | 2015-02-27 | US20180034431A1 | 2018-02-01 | Gino Rocca; Tomasz Hanzlik |
| An integrated circuit arrangement for a microphone, a microphone system and a method for adjusting circuit parameters of the microphone are disclosed. In an embodiment an integrated circuit includes an amplifier circuit with a first switchable network circuit for adjusting an amplifier current of the amplifier circuit, the first switchable network circuit comprising a plurality of switches (SW1, . . . ,SWx) each coupled with a first control port of the first switchable network circuit and a control unit coupled with the first control port of the first switchable network circuit and configured to control a setting of the respective switches (SW1, . . . ,SWx) of the first switchable network circuit. | ||||||
| 7 | Amplifier with actively clamped load | US718053 | 1991-06-20 | US5206550A | 1993-04-27 | Aswin N. Mehta |
| An amplifier is arranged with an actively clamped load. In a differential amplifier, a pair of emitter-coupled transistors has loads connected between the collectors and a voltage supply. Separate clamping transistors have their collector-emitter paths connected across respective ones of the loads. A clamping control circuit, responsive to an input signal, produces a variable control signal to clamp output signal swings across the loads. A similar clamping control circuit can be used with a single-ended amplifier. Such an amplifier having an actively clamped load is useful in sense amplifier circuit arrangements in semiconductor memory arrangements used in data processing systems. | ||||||
| 8 | AMPLIFIER, AMPLIFYING METHOD AND FILTER | EP07806651.1 | 2007-09-04 | EP1944865A1 | 2008-07-16 | IIDA, Sachio; YOSHIZAWA, Atsushi |
An amplifier is provided which includes: a first variable capacitance device of which capacitance is variable, a second variable capacitance device of which capacitance is variable, electrically connected to the first variable capacitance device, and of an inverse conductivity type from the first variable capacitance device, and a first input unit for selectively inputting a bias voltage and a voltage signal to the first variable capacitance device and the second variable capacitance device, wherein, in the event that the bias voltage and the voltage signal are input to the first variable capacitance device and the second variable capacitance device, the capacitance of the first variable capacitance device and the second variable capacitance device is taken as a first value, and wherein the voltage signal is amplified with the capacitance of the first variable capacitance device and the second variable capacitance device as a second value smaller than the first value. |
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| 9 | Source switched split LNA | US15342016 | 2016-11-02 | US09973149B2 | 2018-05-15 | Emre Ayranci; Miles Sanner |
| A receiver front end capable of receiving and processing intraband non-contiguous carrier aggregate (CA) signals using multiple low noise amplifiers (LNAs) is disclosed herein. A cascode having a “common source” configured input FET and a “common gate” configured output FET can be turned on or off using the gate of the output FET. A first switch is provided that allows a connection to be either established or broken between the source terminal of the input FET of each LNA. Further switches used for switching degeneration inductors, gate capacitors and gate to ground caps for each legs can be used to further improve the matching performance of the invention. | ||||||
| 10 | Source Switched Split LNA | US15342016 | 2016-11-02 | US20180019710A1 | 2018-01-18 | Emre Ayranci; Miles Sanner |
| A receiver front end capable of receiving and processing intraband non-contiguous carrier aggregate (CA) signals using multiple low noise amplifiers (LNAs) is disclosed herein. A cascode having a “common source” configured input FET and a “common gate” configured output FET can be turned on or off using the gate of the output FET. A first switch is provided that allows a connection to be either established or broken between the source terminal of the input FET of each LNA. Further switches used for switching degeneration inductors, gate capacitors and gate to ground caps for each legs can be used to further improve the matching performance of the invention. | ||||||
| 11 | Accurate sample latch offset compensation scheme | US14818091 | 2015-08-04 | US09614502B2 | 2017-04-04 | Minhan Chen; Kenneth Luis Arcudia |
| A receiver according to one aspect comprises a latch configured to sample a data signal according to a sampling clock signal, and a plurality of offset-compensation segments, wherein each of the segments is coupled to an internal node of the latch. Each of the segments comprises a compensation transistor, and a step-adjustment transistor coupled in series with the compensation transistor. The receiver further comprises an offset controller configured to selectively turn on one or more of the compensations transistors to reduce an offset voltage of the latch, and a bias circuit configured to apply a bias voltage to a gate of each of one or more of the step-adjustment transistors. | ||||||
| 12 | ACCURATE SAMPLE LATCH OFFSET COMPENSATION SCHEME | US14818091 | 2015-08-04 | US20170040983A1 | 2017-02-09 | Minhan Chen; Kenneth Luis Arcudia |
| A receiver according to one aspect comprises a latch configured to sample a data signal according to a sampling clock signal, and a plurality of offset-compensation segments, wherein each of the segments is coupled to an internal node of the latch. Each of the segments comprises a compensation transistor, and a step-adjustment transistor coupled in series with the compensation transistor. The receiver further comprises an offset controller configured to selectively turn on one or more of the compensations transistors to reduce an offset voltage of the latch, and a bias circuit configured to apply a bias voltage to a gate of each of one or more of the step-adjustment transistors. | ||||||
| 13 | Power amplifier | US13015024 | 2011-01-27 | US08253485B2 | 2012-08-28 | John Christopher Clifton |
| A power amplifier comprises a series stack of power amplifier devices, connected in parallel to the amplifier input for receiving an RF input signal, and having output terminals being connected in series to the amplifier output. An intermediate coupling capacitor is connected between each adjacent pair of power amplifier devices in the series stack of power amplifier devices for DC isolation of said power amplifier devices. This reduces the required DC supply voltage, as well as allowing shorting of individual power amplifier devices in response to variation in the DC supply voltage. | ||||||
| 14 | AMPLIFIER, AMPLIFYING METHOD, AND FILTER | US12093207 | 2007-09-04 | US20090219086A1 | 2009-09-03 | Sachio Iida; Atsushi Yoshizawa |
| An amplifier is provided which includes: a first variable capacitance device of which capacitance is variable, a second variable capacitance device of which capacitance is variable, electrically connected to the first variable capacitance device, and of an inverse conductivity type from the first variable capacitance device, and a first input unit for selectively inputting a bias voltage and a voltage signal to the first variable capacitance device and the second variable capacitance device, wherein, in the event that the bias voltage and the voltage signal are input to the first variable capacitance device and the second variable capacitance device, the capacitance of the first variable capacitance device and the second variable capacitance device is taken as a first value, and wherein the voltage signal is amplified with the capacitance of the first variable capacitance device and the second variable capacitance device as a second value smaller than the first value. | ||||||
| 15 | 正確なサンプルラッチオフセット補償スキーム | JP2018505676 | 2016-07-05 | JP2018526896A | 2018-09-13 | チェン、ミンハン; アルクディア、ケネス・ルイス |
| 1つの態様による受信機は、サンプリングクロック信号にしたがってデータ信号をサンプリングするように構成されたラッチと、複数のオフセット補償セグメントと、を備え、セグメントの各々はラッチの内部ノードに結合されている。セグメントの各々は、補償トランジスタと、補償トランジスタと直列に結合されたステップ調整トランジスタと、を備える。受信機は、さらに、ラッチのオフセット電圧を低減するために補償トランジスタのうちの1つまたは複数を選択的にオンにするように構成されたオフセット制御器と、ステップ調整トランジスタのうちの1つまたは複数の各々のゲートにバイアス電圧を印加するように構成されたバイアス回路と、を備える。 | ||||||
| 16 | マイクロフォン用の集積回路構成体、マイクロフォンシステム、およびマイクロフォンシステムの１つ以上の回路パラメータを調整するための方法 | JP2017545292 | 2015-02-27 | JP2018511219A | 2018-04-19 | ロッカ, ギノ; ハンスリック, トマシュ |
| マイクロフォン(12)用の1つの集積回路構成体(20)は、1つの増幅器回路(22)および1つの制御ユニット(30)を備える。この増幅器回路(22)は、この増幅器回路(22)の増幅器電流を調整するための1つの第1の切り替え可能なネットワーク回路(26)を備える。この第1の切り替え可能なネットワーク回路(26)は、複数のスイッチ(SW1, ...,SWx)を備え、各々のスイッチはこの第1の切り替え可能なネットワーク回路(26)の1つの第1の制御ポートにカップリングされている。この制御ユニット(30)は、この第1の切り替え可能なネットワーク回路(26)の第1の制御ポートにカップリングされており、この第1の切り替え可能なネットワーク回路(26)のそれぞれのスイッチ(SW1, ...,SWx)の設定を制御するように構成されている。【選択図】図1 | ||||||
| 17 | COMMUNICATIONS DEVICE WITH RECEIVER CHAIN OF REDUCED SIZE | US15968927 | 2018-05-02 | US20180323821A1 | 2018-11-08 | Laurent CHABERT; Raphael PAULIN |
| A communications device includes a transmission chain coupled to an antenna a receiver chain coupled to the antenna. The receiver chain includes an amplifier device having an input coupled to the antenna. A controlled switching circuit is included in the amplifier device and is operable to selectively disconnect conduction terminals of an amplifying transistor from power supply terminals when the transmission chain is operating to pass a transmit signal to the antenna. | ||||||
| 18 | DYNAMIC AMPLIFIER AND CHIP USING THE SAME | US15830355 | 2017-12-04 | US20180183394A1 | 2018-06-28 | Chun-Cheng Liu |
| A dynamic amplifier with a bypass design. An input pair of transistors receives a pair of differential inputs Vip and Vin and further provides first, second and third terminals. A load circuit provides a pair of differential outputs Vop and Von with the load circuit connected at a common mode terminal. In an amplification phase, a driver for amplification is coupled to the first terminal and the load circuit is coupled to the second and third terminals. A bypassing circuit is specifically provided. The bypassing circuit is coupled to the second and third terminals during a bypass period within the amplification phase. | ||||||
| 19 | Switching circuit | US15195707 | 2016-06-28 | US09748951B2 | 2017-08-29 | Xiaoqiang Zhang; Mark Ingels |
| A conversion circuit is disclosed. In one aspect, the conversion circuit includes a first input terminal for receiving a digital signal. The conversion circuit includes a second input terminal for receiving a bias voltage signal. The conversion circuit includes an output terminal for outputting a current. The conversion circuit includes a first and a second switch transistor connected to the first input terminal for receiving the digital signal. The conversion circuit includes a first and a second current source transistor connected to the second input terminal for receiving the bias voltage signal. The conversion circuit further includes a first branch, wherein the first switch transistor is connected to the output terminal via the first current source transistor. The conversion circuit further includes a second branch, wherein the second current source transistor is connected to the output terminal via the second switch transistor. | ||||||
| 20 | SWITCHING CIRCUIT | US15195707 | 2016-06-28 | US20170005654A1 | 2017-01-05 | Xiaoqiang Zhang; Mark Ingels |
| A conversion circuit is disclosed. In one aspect, the conversion circuit includes a first input terminal for receiving a digital signal. The conversion circuit includes a second input terminal for receiving a bias voltage signal. The conversion circuit includes an output terminal for outputting a current. The conversion circuit includes a first and a second switch transistor connected to the first input terminal for receiving the digital signal. The conversion circuit includes a first and a second current source transistor connected to the second input terminal for receiving the bias voltage signal. The conversion circuit further includes a first branch, wherein the first switch transistor is connected to the output terminal via the first current source transistor. The conversion circuit further includes a second branch, wherein the second current source transistor is connected to the output terminal via the second switch transistor. | ||||||
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