| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 21 | Montage à faible bruit d'un amplificateur | EP97410113.1 | 1997-10-08 | EP0836272B1 | 2005-02-23 | Compagne, Eric |
| 22 | Schaltungsanordnung mit einem Multiplexer | EP95112054.2 | 1995-07-29 | EP0757436B1 | 1999-12-08 | Becher, Erwin, Dipl.-Ing. (FH) |
| 23 | Differential audio line receiver | JP52001896 | 1995-12-22 | JP4310383B2 | 2009-08-05 | イー． ホイトロック，ウィリアム |
| 24 | Circuit arrangement comprising a multiplexer | JP19805796 | 1996-07-26 | JP3091138B2 | 2000-09-25 | ベーヒャー エルヴィン |
| 25 | Low noise arrangement for amplifier | JP29056197 | 1997-10-08 | JPH10190364A | 1998-07-21 | COMPAGNE ERIC |
| PROBLEM TO BE SOLVED: To provide an integration arrangement realized from an amplifier which suppresses the influence of an output signal against noise to a minimum and has a high gain by containing main amplifiers and a means for generating floating reference voltage for adding an input signal to the first input terminal of the main amplifier and making reference voltage to arrangement which is servo-controlled by the equivalent input noise of the main amplifier. SOLUTION: The main amplifiers 1 and 1' and the means 5 for generating floating reference voltage VG for adding one input signal V' to one first input terminal E- or E in the main amplifiers in a prescribed period are contained. The reference voltage VG is arranged so that it is servo-controlled by the equivalent input noise V n of the main amplifier 1. The number of cascade-type transistor stages constituting the main amplifier 1 is suppressed to a minimum and the high open loop gain can be obtained. Noise V n depending on the number of the transistors of the main amplifier 1 is suppressed to a minimum and minimum supply voltage required for the operation of the arrangement can be dropped. COPYRIGHT: (C)1998,JPO | ||||||
| 26 | DIFFERENTIAL AUDIO LINE RECEIVER | EP94915853.9 | 1994-04-22 | EP0700597B1 | 2003-03-12 | WHITLOCK, William E. |
| An audio line receiver which tolerates a wide range of balanced and unbalanced source impedances with a minimal deterioration of the line receiver's common-mode rejection ratio. The line receiver includes a differential amplifier (50) with input amplifiers (52, 54) on each input of the differential amplifier. The input amplifiers are typically operational amplifiers (A8 or A9) connected for unity gain, but also having two bias resistors (R17 and R19, or R18 and R20) connected in series between the input terminals of the input amplifiers and ground. A capacitor (C1 or C2) connected from the output of the operational amplifier to a node between the two series connected bias resistors prevents the low impedance of the bias resistors from significantly degrading the line receiver's common-mode rejection ratio. | ||||||
| 27 | DIFFERENTIAL AUDIO LINE RECEIVER | EP95944208.0 | 1995-12-22 | EP0799524A1 | 1997-10-08 | WHITLOCK, William E. |
| A bootstrapped audio line receiver that receives a differential-mode input signal from first and second differential lines and outputs a single-ended signal on an output line. The line receiver includes a differential amplifier and an input amplifier having differential output terminals and differential input terminals. The input amplifier is connected between the differential lines and the differential amplifier. The input amplifier provides a dc current path to a ground terminal while maintaining a high input impedance to ac signals at audio frequencies. The input amplifier also includes an rf filter that removes rf noise without adversely affecting the line receiver's common-mode noise rejection at audio frequencies. In one embodiment, the input amplifier includes two operational amplifiers connected for unity gain and having two bias resistors connected in series between each input terminals of the input amplifier and a ground terminal. A capacitor is connected from the output of each operational amplifier to a node between each set of series connected bias resistors and prevents the low impedance of the bias resistors from significantly degrading the line receiver's common-mode rejection ratio. Thus, the line receiver tolerates a wide range of balanced and unbalanced source impedances with a minimal deterioration of the line receiver's common-mode rejection ratio. | ||||||
| 28 | Schaltungsanordnung mit einem Multiplexer | EP95112054.2 | 1995-07-29 | EP0757436A1 | 1997-02-05 | Becher, Erwin, Dipl.-Ing. (FH) |
Zur einpoligen Durchschaltung eines von N jeweils eine Signal-Leitung (L1, L2, LN) und jeweils eine Kanalnullpunkt-Leitung (N1, N2, NN) aufweisenden Signalkanälen (K1, K2, KN), wobei N größer als eins ist, auf einen Eingang eines (Differenz-)Verstärkers (1), dessen Schaltung auf einen zugeordneten Schaltungsnullpunkt (SN) bezogen ist, ist ein Eins-aus-N-Multiplexers (2) mit 3N Schaltstrecken (S11, S21, S31, S12, S22, S32, S1N, S2N, S3N) vorgesehen, von denen ein erster Schaltstrecken-Satz (S11, S12, S1N) der Durchschaltung der N Signal-Leitungen (L1, L2, LN) und ein zweiter Schaltstrecken-Satz (S21, S22, S2N) der Weiterschaltung der N Kanalnullpunkt-Leitungen (N1, N2, NN) dient, der jeweilige Eingang der Schaltstrecken eines dritten Schaltstrecken-Satzes (S31, S32, S3N) mit dem jeweiligen Eingang der Schaltstrecken des zweiten Schaltstrecken-Satzes (S21, S22, S2N) verbunden ist, die Ausgänge der letzteren gemeinsam an einem Eingang eines Hilfs-(Differenz-)Verstärkers (3) und die Ausgänge des dritten Schaltstrecken-Satzes (S31, S32, S3N) gemeinsam am Ausgang des Hilfs-(Differenz-)Verstärkers liegen, dessen Schaltung auf den Schaltungsnullpunkt (SN) bezogen ist. |
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| 29 | 리액턴스 성분을 보상한 연결 구조를 갖는 전력소자 | KR1020060041854 | 2006-05-10 | KR1020070061074A | 2007-06-13 | 장우진; 문재경; 김해천; 임종원; 지홍구; 안호균 |
| A power device having a connective structure for compensating a reactance element is provided to improve attenuation of gain and output power due to degradation of a transistor. A plurality of transmission lines have parallel-trapezoidal structure and include input transmission lines(101-108) and output transmission lines(121-128) facing edges in a diagonal direction. A plurality of transistors(110,113,116,119) are connected in parallel to each other by the transmission lines. A plurality of via holes(109,111,112,114,115,117,118,120) are formed at both sides of the transistors to radiate the heat of the transistors to the outside. | ||||||
| 30 | An integrated circuit device having a self-biased, single pin radio frequency signal input | EP00120633.3 | 2000-09-21 | EP1087522B1 | 2008-01-02 | Marneweck, Willem; Schieke, Peter; Smit, Willem |
| 31 | DIFFERENTIAL AUDIO LINE RECEIVER | EP95944208.8 | 1995-12-22 | EP0799524B1 | 2003-04-16 | WHITLOCK, William E. |
| A bootstrapped audio line receiver that receives a differential-mode input signal from first and second differential lines and outputs a single-ended signal on an output line. The line receiver includes a differential amplifier and an input amplifier having differential output terminals and differential input terminals. The input amplifier is connected between the differential lines and the differential amplifier. The input amplifier provides a dc current path to a ground terminal while maintaining a high input impedance to ac signals at audio frequencies. The input amplifier also includes an rf filter that removes rf noise without adversely affecting the line receiver's common-mode noise rejection at audio frequencies. In one embodiment, the input amplifier includes two operational amplifiers connected for unity gain and having two bias resistors connected in series between each input terminals of the input amplifier and a ground terminal. A capacitor is connected from the output of each operational amplifier to a node between each set of series connected bias resistors and prevents the low impedance of the bias resistors from significantly degrading the line receiver's common-mode rejection ratio. Thus, the line receiver tolerates a wide range of balanced and unbalanced source impedances with a minimal deterioration of the line receiver's common-mode rejection ratio. | ||||||
| 32 | An integrated circuit device having a self-biased, single pin radio frequency signal input | EP00120633.3 | 2000-09-21 | EP1087522A3 | 2003-04-02 | Marneweck, Willem; Schieke, Peter; Smit, Willem |
A radio frequency transponder device in an integrated circuit package requires only one dedicated pin for connection to a parallel resonant tuned circuit for receiving a remote signal. The one dedicated pin has a capacitor which blocks direct current (DC) flow and allows independent DC biasing of a radio frequency amplifier for increased signal amplification gain. Another package pin used for common power or ground connections supplies the second connection to the resonant tuned circuit. Multiple transponder inputs may be implemented in a single integrated circuit package using only one dedicated pin per input plus one common pin which may be used for another purpose, such as a power or a ground connection. |
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| 33 | An integrated circuit device having a self-biased, single pin radio frequency signal input | EP00120633.3 | 2000-09-21 | EP1087522A2 | 2001-03-28 | Marneweck, Willem; Schieke, Peter; Smit, Willem |
A radio frequency transponder device in an integrated circuit package requires only one dedicated pin for connection to a parallel resonant tuned circuit for receiving a remote signal. The one dedicated pin has a capacitor which blocks direct current (DC) flow and allows independent DC biasing of a radio frequency amplifier for increased signal amplification gain. Another package pin used for common power or ground connections supplies the second connection to the resonant tuned circuit. Multiple transponder inputs may be implemented in a single integrated circuit package using only one dedicated pin per input plus one common pin which may be used for another purpose, such as a power or a ground connection. |
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| 34 | DIFFERENTIAL AUDIO LINE RECEIVER | EP94915853 | 1994-04-22 | EP0700597A4 | 1998-11-18 | WHITLOCK WILLIAM E |
| An audio line receiver which tolerates a wide range of balanced and unbalanced source impedances with a minimal deterioration of the line receiver's common-mode rejection ratio. The line receiver includes a differential amplifier (50) with input amplifiers (52, 54) on each input of the differential amplifier. The input amplifiers are typically operational amplifiers (A8 or A9) connected for unity gain, but also having two bias resistors (R17 and R19, or R18 and R20) connected in series between the input terminals of the input amplifiers and ground. A capacitor (C1 or C2) connected from the output of the operational amplifier to a node between the two series connected bias resistors prevents the low impedance of the bias resistors from significantly degrading the line receiver's common-mode rejection ratio. | ||||||
| 35 | Montage à faible bruit d'un amplificateur | EP97410113.1 | 1997-10-08 | EP0836272A1 | 1998-04-15 | Compagne, Eric |
L'invention concerne un montage comportant un amplificateur principal (1, 10) et un moyen (5) pour créer, au moins pendant certaines périodes, un potentiel de référence flottant (VG) d'application d'au moins un signal (V') d'entrée sur au moins une première borne d'entrée (E-) de l'amplificateur principal, ce potentiel de référence étant asservi sur le bruit (Vn') de l'amplificateur principal ramené sur son entrée. |
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| 36 | DIFFERENTIAL AUDIO LINE RECEIVER | EP94915853.0 | 1994-04-22 | EP0700597A1 | 1996-03-13 | WHITLOCK, William E. |
| An audio line receiver which tolerates a wide range of balanced and unbalanced source impedances with a minimal deterioration of the line receiver's common-mode rejection ratio. The line receiver includes a differential amplifier (50) with input amplifiers (52, 54) on each input of the differential amplifier. The input amplifiers are typically operational amplifiers (A8 or A9) connected for unity gain, but also having two bias resistors (R17 and R19, or R18 and R20) connected in series between the input terminals of the input amplifiers and ground. A capacitor (C1 or C2) connected from the output of the operational amplifier to a node between the two series connected bias resistors prevents the low impedance of the bias resistors from significantly degrading the line receiver's common-mode rejection ratio. | ||||||
| 37 | 가상 접지 노드를 이용한 증폭기 | KR1020090120738 | 2009-12-07 | KR1020110064235A | 2011-06-15 | 박창근 |
| PURPOSE: An amplifying apparatus using a virtual ground node is provided to simplify a structure of a circuit by skipping an additional coupler for detecting power. CONSTITUTION: An output power of an amplifier is estimated by using power of a secondary harmonic signal occurring at a node(202). The size of the power of the secondary harmonic signal is increased according as a size of a final output signal is increased. An inductor is added between a ground and a virtual ground node. The inductor is used in order to increase the power of the secondary harmonic component at the node. | ||||||
| 38 | 자기 바이어스된, 단일 핀 고주파 신호 입력을 갖는집적회로 장치 | KR1020000056261 | 2000-09-25 | KR1020010050637A | 2001-06-15 | 마네웩,윌리엄; 취이크,피터; 스미트,윌리엄 |
| PURPOSE: To provide a wireless frequency transponder that effectively and skillfully utilizes an input output pin to connect a parallel resonance circuit on an integrated circuit package to a transponder circuit of the integrated circuit. CONSTITUTION: The wireless frequency transponder includes a wireless frequency tuning circuit having 1st and 2nd terminals and the integrated circuit having a 1st capacitor, a wireless frequency amplifier, 1st and 2nd current sources, and a bias control circuit. The 1st and 2nd current sources are connected to the wireless Frequency amplifier and generate the bias level of the amplifier and control The gain of the amplifier. The bias control circuit generate a bias level and is connected to the 1st and 2nd current sources, the integrated circuit has signal connection and common connection terminals and the input of the wireless frequency amplifier is connected to the signal connection terminal. The 1st capacitor is connected between the 1st terminal of the wireless frequency tuning circuit and the signal connection terminal and the 2nd terminal of the wireless frequency tuning circuit is connected to the common connection terminal. | ||||||
