| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 161 | An Amplification Circuit | EP13178990.1 | 2013-08-01 | EP2833547A1 | 2015-02-04 | Geurts, Marcellinus Johannes Maria; Praamsma, Louis; Groenewegen, Michel Wilhelmus Arnoldus; Breunisse, Rainier; van Straten, Freek Egbert; Buytenhuijs, Robert |
An amplification circuit (100) comprising a first filter (102) and an LNA (110). The first filter (102) comprising an input (104) for receiving an input signal; a first differential output (106); and a second differential output (108). The first filter (102) has a differential mode of operation for frequencies in its pass-band (706, 806) and a common mode of operation for frequencies outside its pass-band (706, 806), and may be an acoustic wave filter. The LNA (110) comprising a first differential input (112) connected to the first differential output (106) of the first filter (102); a second differential input (114) connected to the second differential output (108) of the first filter (102); and an output (116) for providing an amplified output signal.
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| 162 | NEURON RECORDING SYSTEM | EP12801854 | 2012-06-19 | EP2720611A4 | 2014-12-03 | LO YI-KAI; LIU WENTAI |
| 163 | Semiconductor device and adjustment method of filter circuit | EP13197247.3 | 2013-12-13 | EP2750291A2 | 2014-07-02 | Kihara, Takao; Sano, Tomohiro |
A filter circuit which can pass a desired signal component of a high-frequency signal input and can attenuate a harmonic component of an integral multiple of the desired signal over a wide range is provided. The filter circuit is a notch filter which passes the desired signal component of a high-frequency signal inputted and attenuates a threefold higher frequency or a third harmonic component of the desired signal. The notch filter is provided with a first inductor (L1) and a second inductor (L2) coupled in series between a signal line transmitting a high-frequency signal and a power supply line, a first variable capacitor (C1) coupled between the power supply line and a node of the first inductor and the second inductor, and a second variable capacitor (C2) coupled between the signal line and the power supply line. The frequency of the desired signal component is adjusted by capacitance values of the first variable capacitor and the second variable capacitor, and the frequency of the third harmonic component is adjusted by a capacitance value of the first variable capacitor. The filter may be coupled between a quadrature modulator and a transmission amplifier (PGA).
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| 164 | TUNABLE RADIO FRONT END AND METHODS | EP11820747 | 2011-08-26 | EP2609686A4 | 2014-04-30 | MORRIS ARTHUR S III |
| Tunable radio front end systems and methods are disclosed in which the tunable radio front end includes a first tunable impedance matching network, a second tunable impedance matching network, a transmission signal path, and a reception signal path. The transmission signal path can include a first tunable filter in communication with the first tunable impedance matching network, a tunable power amplifier connected to the first tunable filter, and a radio transmitter connected to the tunable power amplifier. The reception signal path can include a second tunable filter in communication with the second tunable impedance matching network, a tunable low-noise amplifier connected to the second tunable filter, and a radio receiver connected to the tunable low-noise amplifier. | ||||||
| 165 | Amplifier current consumption control | EP10196153.0 | 2010-12-21 | EP2469708B1 | 2013-11-27 | Pfaffinger, Gerhard; Lorenz, Franz; Zuckmantel, Stefan; Christoph, Markus |
| 166 | ADJUSTABLE CIRCUIT ARCHITECTURE | EP09849712 | 2009-09-22 | EP2481150A4 | 2013-11-20 | KALTIOKALLIO MIKKO; RYYNAENEN JUSSI |
| An amplifier circuitry having adjustable parameters is presented. The present amplifier circuitry includes a feed-back loop, wherein the feedback loop converts (26) a signal to another frequency, filters (20) the signal in the other frequency, and restores (24) the filtered signal back to the original frequency for inputting the signal to an input of the amplifier (22). The feed-back loop implements a band-stop filter (20) having an adjustable stopband causing the amplifier circuitry to have an adjustable band-pass response. A passband of the amplifier circuitry is changed from one operating frequency to another operating frequency by changing frequency conversion parameters of the feedback loop. | ||||||
| 167 | BOOSTER CIRCUIT | EP07808287 | 2007-09-18 | EP2052537A4 | 2011-03-16 | CHOI SEOK DONG |
| 168 | BOOSTER CIRCUIT | EP07808287.2 | 2007-09-18 | EP2052537A1 | 2009-04-29 | CHOI, Seok Dong |
| A booster circuit comprises a rejection filter for filtering a signal, which has a frequency band higher than a preset frequency band, among input signals, and a booster for receiving and amplifying a signal output from the rejection filter. | ||||||
| 169 | A METHOD OF CONTROLLING A LINEAR POWER AMPLIFIER | EP05777545.4 | 2005-08-23 | EP1782532B1 | 2008-07-02 | ALTHAM, Andrew; DOMOKOS, John |
| A method of controlling a linear power amplifier (15) comprises inputting an instantaneous input signal (2); filtering the instantaneous input signal to generate a filtered input signal (5); combining the instantaneous input signal (2) and filtered input signal (5) to generate a modified drain source voltage V?ds#191 waveform (12); and modulating a switched mode power supply (14) to the linear power amplifier in accordance with the modified V?ds#191 waveform. | ||||||
| 170 | A METHOD OF CONTROLLING A LINEAR POWER AMPLIFIER | EP05777545.4 | 2005-08-23 | EP1782532A1 | 2007-05-09 | ALTHAM, Andrew; DOMOKOS, John |
| A method of controlling a linear power amplifier (15) comprises inputting an instantaneous input signal (2); filtering the instantaneous input signal to generate a filtered input signal (5); combining the instantaneous input signal (2) and filtered input signal (5) to generate a modified drain source voltage V?ds#191 waveform (12); and modulating a switched mode power supply (14) to the linear power amplifier in accordance with the modified V?ds#191 waveform. | ||||||
| 171 | TRANSMITTER PREDISTORTION CIRCUIT AND METHOD THEREFOR | EP05711985.1 | 2005-01-24 | EP1709729A1 | 2006-10-11 | MCCALLISTER, Ronald, D. |
| A digital communications transmitter (100) includes a digital linear-and-nonlinear predistortion section (200, 1800, 2800) to compensate for linear and nonlinear distortion introduced by transmitter-analog components (120). A direct-digital-downconversion section (300) generates a complex digital return-data stream (254) from the analog components (120) without introducing quadrature imbalance. A relatively low resolution exhibited by the return-data stream (254) is effectively increased through arithmetic processing. Distortion introduced by an analog-to-digital converter (304) may be compensated using a variety of adaptive techniques. Linear distortion is compensated using adaptive techniques with an equalizer (246) positioned in the forward-data stream (112). Nonlinear distortion is then compensated using adaptive techniques with a plurality of equalizers (226) that filter a plurality of orthogonal, higher-ordered-basis functions (214) generated from the forward-data stream (112). The filtered-basis functions are combined together and subtracted from the forward-data stream (112). | ||||||
| 172 | RF power amplifier | EP92109071.8 | 1992-05-29 | EP0516134B1 | 1998-02-11 | Fujita, Noriyuki, c/o NEC Corporation |
| 173 | DIGITAL CLASS-D AMPLIFIER AND DIGITAL SIGNAL PROCESSING METHOD | EP12780732.9 | 2012-10-30 | EP2781020B1 | 2018-12-12 | CRIPPA, Carlo; BASSOLI, Rossella |
| A digital class D amplifier (10) is disclosed, comprising a pulse width modulator (PW Mod) comprising: a digital loop filter (Loop F) adapted to receive an input signal (x[n]) and a feedback signal (fb[n]), the digital loop filter (Loop_F) being adapted to process at a clock frequency (f_s) said input and feedback signals for providing as output a filtered digital signal (w[n]); a PWM conversion module (PW_CM) having an input (24) for receiving the filtered digital signal (w[n]) and having a first output (25) connected to the digital loop filter (Loop F), the PWM conversion module being adapted for processing the filtered digital signal (w[n]) and providing at said first output (25) the feedback signal (fb[n]). The PWM conversion module (PW_CM) comprises: a first comparator (CMP_N) adapted to compare the filtered digital signal (w[n]) with a first reference triangular waveform (VTn[n]) for providing as output a first PWM signal (yn[n]), the first reference triangular waveform having a frequency (f_osc) much lower than said clock frequency (f.s); a second comparator (CMP_P) adapted to compare the filtered digital signal (w[n]) with a second reference triangular waveform (VTp[n]) for providing as output a second PWM signal (yp[n]), the second reference triangular waveform (VTp[n]) being the inverse of the first triangular waveform (VTn[n]), said first (yn[n]) and second (yp[n]) PWM signals representing a differential output pulse width modulated signal (yn[n],yp[n]). | ||||||
| 174 | ELECTRONIC DEVICE AND ANTENNA CONTROL METHOD THEREOF | EP16173817.4 | 2016-06-09 | EP3104531B1 | 2018-11-14 | KIM, Sung-Soo; PAIK, Min-Chull; LEE, Jong-In; JANG, Chang-Won; LEE, Seung-Min; CHA, Jae-Min |
| An electronic device is provided. The electronic device includes a first antenna, a second antenna, a transmission/reception path unit, a first reception path unit, a second reception path unit including a low noise amplifier (LNA), a signal path selection unit configured to connect each of the first antenna and the second antenna to the transmission/reception path unit, the first reception path unit, or the second reception path unit, and a radio frequency integrated circuit (RFIC) module or a processor including the RFIC module configured to control the signal path selection unit to have a first state in which the first antenna is connected to the transmission/reception path unit and the second antenna is connected to the second reception path unit or control the signal path selection unit to have a second state in which the first antenna is connected to the first reception path unit and the second antenna is connected to the transmission/reception path unit. | ||||||
| 175 | RECEIVER CIRCUIT | EP15175944.6 | 2015-07-08 | EP3116127B1 | 2018-09-12 | Peter, Matthias; Thalheim, Jan |
| A data communications receiver (102) including a receiver coil, a first amplification stage (110) coupled to the receiver coil, the first amplification circuitry to differentially amplify at least part of signal received (104) by the receiver coil relative to a threshold, a second amplification stage (112) coupled to receive the differentially amplified signal (U1) from the first amplification stage (110), the second amplification stage (112) comprising a current mirror, and hysteretic level shifting circuitry to shift a level of part of the signal received by the receiver coil, the threshold or part of the signal received by the receiver coil and the threshold such that, in response to the at least part of the signal received by the receiver coil having crossed the threshold, a threshold crossing in the other direction is delayed. | ||||||
| 176 | FORWARDED CLOCK JITTER REDUCTION | EP11878713.4 | 2011-12-30 | EP2798742B1 | 2018-09-05 | ROYTMAN, Eduard, Edi; NAGARAJAN, Mahalingam, Mali; VEMPADA, Pradeep, R. |
| In some embodiments, a differential amplifier with duty cycle correction is provided. | ||||||
| 177 | CLASS AB AMPLIFIER HAVING CASCODE STAGE WITH FILTER FOR IMPROVING LINEARITY | EP18150897.9 | 2018-01-09 | EP3355471A1 | 2018-08-01 | HSU, Jui-Yu; LYU, Yuan-Fu; CHEN, Sheng-Hao |
The present invention provides a class AB amplifier (100), wherein the class AB amplifier (100) includes a cascode stage with a filter (120_1) and an output stage (130_1). The cascode stage with the filter (120_1) is arranged for receiving an input signal to generate a first driving signal and a second driving signal, wherein the filter (222) filters the input signal to generate an filtered input signal, and at least one of the first driving signal and the second driving signal is generated according to the filtered input signal. The output stage (130_1) is coupled to the cascode stage (120_1), and is arranged for generating an output signal according to the first driving signal and the second driving signal.
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| 178 | DETECTION OF EXCESSIVELY HIGH INTERFERENCE SIGNAL LEVELS DURING RECEPTION OF GLOBAL NAVIGATION SATELLITE SYSTEM SIGNALS | EP14907358 | 2014-12-04 | EP3228000A4 | 2018-07-18 | SOKOLOV ANDREY MIKHAILOVICH; TATARNIKOV DMITRY VITALIEVICH; BACHMANOV KONSTANTIN MIKHAILOVICH; YUSUPOV RIFAT KHAIDAROVICH |
| A high-linear amplifier receives, from an input bandpass filter, input signals including weak process signals and strong interference signals, amplifies the input signals, and transmits the amplified signals to an output bandpass filter. The high-linear amplifier includes a transistor and a feedback circuit that stabilizes the operating current of the transistor. The operating current includes the direct-current and low-frequency output signal currents of the transistor. The feedback circuit includes an interference detector that rectifies a portion of the high-frequency output signals of the transistor and extends the linear range of the high-linear amplifier. An interference indicator unit alerts an operator to the presence of excessively high levels of interference before the high-linear amplifier enters the non-linear mode. Amplified signals rejected by the output bandpass filter are reflected back to the high-linear amplifier stage. A directional coupler prevents the reflected signals from disrupting the operation of the interference detector. | ||||||
| 179 | BASEBAND PROCESSING CIRCUITRY | EP14781362.0 | 2014-09-19 | EP3050211B1 | 2018-05-30 | CHANG, Li-Chung; GUPTA, Bindu; GATHMAN, Timothy Donald; CHAMAS, Ibrahim Ramez |
| Techniques for designing baseband processing circuitry for radio IC's. In an aspect, techniques for differential-to-single-ended conversion in a baseband portion of the IC are disclosed to reduce the pin count and package size for RF IC's. In another aspect, the converter includes selectable narrowband and wideband amplifiers, wherein the wideband amplifiers may be implemented using transistor devices having smaller area than corresponding transistor devices of narrowband amplifiers. Further techniques for bypassing one or more elements, and for implementing a low-pass filter of the converter using an R-C filter network, are described. | ||||||
| 180 | SUPPRESSION OF SPURIOUS HARMONICS GENERATED IN TX DRIVER AMPLIFIERS | EP14750265.2 | 2014-07-18 | EP3025425B1 | 2017-08-23 | VORA, Sameer Vasantlal; LAU, Wing Fat Andy |
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