子分类：
| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 181 | Low frequency precision oscillator | US14978837 | 2015-12-22 | US09823687B2 | 2017-11-21 | Arup Mukherji; John M. Khoury |
| A technique includes using a first oscillator to clock operations of a radio of an integrated circuit (IC). The technique includes intermittently using the first oscillator to frequency tune a second oscillator of the IC. | ||||||
| 182 | Semiconductor device | US15247995 | 2016-08-26 | US09806107B2 | 2017-10-31 | Atsushi Umezaki |
| Provided is a semiconductor device exemplified by an inverter circuit and a shift register circuit, which is characterized by a reduced number of transistors. The semiconductor device includes a first transistor, a second transistor, and a capacitor. One of a source and a drain of the first transistor is electrically connected to a first wiring, and the other thereof is electrically connected to a second wiring. One of a source and a drain of the second transistor is electrically connected to the first wiring, a gate of the second transistor is electrically connected to a gate of the first transistor, and the other of the source and the drain of the second transistor is electrically connected to one electrode of the capacitor, while the other electrode of the capacitor is electrically connected to a third wiring. The first and second transistors have the same conductivity type. | ||||||
| 183 | COMPENSATION FOR DIGITALLY CONTROLLED OSCILLATOR APPARATUS AND METHOD | US15583835 | 2017-05-01 | US20170264306A1 | 2017-09-14 | Shenggao Li |
| Automatic digital sensing and compensation of frequency drift caused by temperature, aging, and/or other effects may be provided by including a compensation capacitor array and a sensing logic. The sensing logic may be configured to detect a drift in a first control signal and to provide the compensation capacitor array with a second control signal. The second control signal is configured to cause an adjustment of capacitance in the compensation capacitor array based on the detected drift in the first control signal. | ||||||
| 184 | LOW FREQUENCY PRECISION OSCILLATOR | US14978837 | 2015-12-22 | US20170177020A1 | 2017-06-22 | ARUP MUKHERJI; JOHN M. KHOURY |
| A technique includes using a first oscillator to clock operations of a radio of an integrated circuit (IC). The technique includes intermittently using the first oscillator to frequency tune a second oscillator of the IC. | ||||||
| 185 | Stable oscillator for use in an electronic circuit | US15061976 | 2016-03-04 | US09602052B2 | 2017-03-21 | Yuji Satoh |
| An oscillator includes first, second, and third current sources, a resistor having first and second terminals, first and second capacitors each having first and second terminals, a switch circuit through which each of the current sources is connectable to the first terminal of one of the resistor and the two capacitors to supply current thereto, a comparator, and switch controller configured to generate control signals for the switch circuit and an oscillation output signal for each of multiple periods based on an output signal from the comparator. During one of the periods, the switch circuit is controlled to connect the first current source to the first terminal of the first capacitor, the second current source to the first terminal of the resistor, the first terminal of the resistor to a first input of the comparator, and the first terminal of the first capacitor to a second input of the comparator. | ||||||
| 186 | SEMICONDUCTOR DEVICE | US15247995 | 2016-08-26 | US20170053952A1 | 2017-02-23 | Atsushi UMEZAKI |
| Provided is a semiconductor device exemplified by an inverter circuit and a shift register circuit, which is characterized by a reduced number of transistors. The semiconductor device includes a first transistor, a second transistor, and a capacitor. One of a source and a drain of the first transistor is electrically connected to a first wiring, and the other thereof is electrically connected to a second wiring. One of a source and a drain of the second transistor is electrically connected to the first wiring, a gate of the second transistor is electrically connected to a gate of the first transistor, and the other of the source and the drain of the second transistor is electrically connected to one electrode of the capacitor, while the other electrode of the capacitor is electrically connected to a third wiring. The first and second transistors have the same conductivity type. | ||||||
| 187 | OSCILLATOR | US15061976 | 2016-03-04 | US20170040944A1 | 2017-02-09 | Yuji SATOH |
| An oscillator includes first, second, and third current sources, a resistor having first and second terminals, first and second capacitors each having first and second terminals, a switch circuit through which each of the current sources is connectable to the first terminal of one of the resistor and the two capacitors to supply current thereto, a comparator, and switch controller configured to generate control signals for the switch circuit and an oscillation output signal for each of multiple periods based on an output signal from the comparator. During one of the periods, the switch circuit is controlled to connect the first current source to the first terminal of the first capacitor, the second current source to the first terminal of the resistor, the first terminal of the resistor to a first input of the comparator, and the first terminal of the first capacitor to a second input of the comparator. | ||||||
| 188 | System and method for a voltage controlled oscillator | US14808867 | 2015-07-24 | US09537447B2 | 2017-01-03 | Saverio Trotta |
| In accordance with an embodiment, a voltage controlled oscillator (VCO) includes a VCO core having a plurality of transistors, a bias resistor coupled between collector terminals of the VCO core and a first supply node, and a varactor circuit coupled to emitter terminals of the VCO core. The bias resistor is configured to limit a self-bias condition of the VCO core. | ||||||
| 189 | Method for re-centering a VCO, integrated circuit and wireless device | US14606492 | 2015-01-27 | US09515666B2 | 2016-12-06 | Cristian Pavao-Moreira; Birama Goumballa; Yi Yin |
| A method of re-centering a voltage controlled oscillator of a wireless device comprising a phase locked loop circuit is described. The method comprises receiving an input frequency signal at a phase detector of the phase locked loop circuit from a frequency source; generating an oscillator signal based on the received frequency signal; selectably opening a feedback loop of the phase locked loop circuit when in a calibration mode of operation, performing coarse frequency tuning of the oscillator output signal; performing fine frequency tuning of a coarsely adjusted oscillator output signal; and closing the feedback loop. | ||||||
| 190 | Fractional-N all digital phase locked loop incorporating look ahead time to digital converter | US14831781 | 2015-08-20 | US09455667B2 | 2016-09-27 | Gerasimos S. Vlachogiannakis; Augusto Ronchini Ximenes; Robert Bogdan Staszewski |
| A novel and useful look-ahead time to digital converter (TDC) that is applied to an all digital phase locked loop (ADPLL) as the fractional phase error detector. The deterministic nature of the phase error during frequency/phase lock is exploited to achieve a reduction in power consumption of the TDC. The look-ahead TDC circuit is used to construct a cyclic DTC-TDC pair which functions to reduce fractional spurs of the output spectrum in near-integer channels by randomly rotating the cyclic DTC-TDC structure so that it starts from a different point every reference clock thereby averaging out the mismatch of the elements. Associated rotation and dithering methods are also presented. The ADPLL is achieved using the look-ahead TDC and/or cyclic DTC-TDC pair circuit. | ||||||
| 191 | PHASE NOISE REDUCTION IN VOLTAGE CONTROLLED OSCILLATORS | US15093169 | 2016-04-07 | US20160226441A1 | 2016-08-04 | Alberto Valdes-Garcia; Bodhisatwa Sadhu |
| A voltage controlled oscillator (VCO), a method of designing a voltage controlled oscillator, and a design structure comprising a semiconductor substrate including a voltage controlled oscillator are disclosed. In one embodiment, the VCO comprises an LC tank circuit for generating an oscillator output at an oscillator frequency, and an oscillator core including cross-coupled semiconductor devices to provide feedback to the tank circuit. The VCO further comprises a supply node, a tail node, and a noise by-pass circuit connected to the supply and tail nodes, in parallel with the tank circuit and the oscillator core. The by-pass circuit forms a low-impedance path at a frequency approximately twice the oscillator frequency to at least partially immunize the oscillator core from external noise and to reduce noise contribution from the cross-coupled semiconductor devices. | ||||||
| 192 | System and Method for a Voltage Controlled Oscillator | US14592415 | 2015-01-08 | US20160204740A1 | 2016-07-14 | Saverio Trotta |
| In accordance with an embodiment, a voltage controlled oscillator (VCO) includes a VCO core having a plurality of transistors and a varactor circuit that has a first end coupled to emitter terminals of the VCO core and a second end coupled to a tuning terminal. The varactor circuit includes a capacitance that increases with increasing voltage applied to the tuning terminal with respect to the emitter terminals of the VCO core. | ||||||
| 193 | Apparatus and Method for Providing Oscillator Signals | US14580952 | 2014-12-23 | US20160156310A1 | 2016-06-02 | Harald Pretl; Guenther Haberpeuntner; Volker Neubauer; Svetozar Broussev; Andreas Mayer; Andreas Puerstinger |
| An apparatus for providing oscillator signals includes an oscillator circuit configured to generate a first oscillator signal with a first oscillator signal frequency for a frequency conversion of a first signal to be converted and to generate a second oscillator signal with a second oscillator signal frequency for a frequency conversion of a second signal to be converted. The oscillator circuit is configured to enable the generation of the first oscillator signal with the first oscillator signal frequency and the second oscillator signal with the second oscillator signal frequency based on at least two different possible oscillator circuit configurations. The control circuit is configured to select, based on the first oscillator signal frequency and the second oscillator signal frequency, one of the possible oscillator circuit configurations of the oscillator circuit for generating the first oscillator signal and the second oscillator signal. | ||||||
| 194 | Clock generator using free-running oscillator and method therefor | US14339113 | 2014-07-23 | US09356606B2 | 2016-05-31 | Aaron J. Caffee; Brian G. Drost; Hendricus de Ruijter |
| A clock generator comprises a free-running oscillator and a tunable frequency synthesizer. The free-running oscillator has an output for providing an oscillator clock signal. The tunable frequency synthesizer is coupled to the free-running oscillator and provides a clock output signal in response to the oscillator clock signal and a frequency control signal. The frequency control signal corresponds to a measured characteristic of the free-running oscillator. | ||||||
| 195 | Method and Apparatus of Synchronizing Oscillators | US14942425 | 2015-11-16 | US20160072436A1 | 2016-03-10 | Chewn-Pu Jou; Huan-Neng Chen |
| A circuit includes a first oscillator and a second oscillator. The first oscillator includes an inductive device, a capacitive device, and an active feedback device configured to output a first output signal having a predetermined frequency according to electrical characteristics of the inductive device of the first oscillator and electrical characteristics of the capacitive device of the first oscillator. The second oscillator includes an inductive device, a capacitive device, and an active feedback device configured to output a second output signal having the predetermined frequency according to electrical characteristics of the inductive device of the second oscillator and electrical characteristics of the capacitive device of the second oscillator. The inductive device of the first oscillator and the inductive device of the second oscillator are magnetically coupled. | ||||||
| 196 | SEMICONDUCTOR DEVICE | US14627621 | 2015-02-20 | US20160071566A1 | 2016-03-10 | Hiromi NORO; Shintaro SAKAI |
| According to one embodiment, a semiconductor device includes a first pad in a first region between a memory region of a semiconductor chip and a first end portion of the semiconductor chip; a second pad in a second region between the memory region and a second end portion of the semiconductor chip, the second end portion being opposite to the first end portion; an output circuit coupled to the second pad; and a calibration circuit which is coupled to the first pad and regulates an impedance of the output circuit, the calibration circuit including a first circuit in the first region and a second circuit in the second region. | ||||||
| 197 | ADJUSTING THE MAGNITUDE OF A CAPACITANCE OF A DIGITALLY CONTROLLED CIRCUIT | US14617507 | 2015-02-09 | US20160065227A1 | 2016-03-03 | Herschel A. Ainspan; Mark A. Ferriss; Daniel J. Friedman; Alexander V. Rylyakov; Bodhisatwa Sadhu; Alberto Valdes-Garcia |
| An apparatus comprises a digitally controlled circuit having a variable capacitance and a controller configured to adjust a magnitude of the variable capacitance of the digitally controlled circuit. The digitally controlled circuit comprises a plurality of gain elements, the plurality of gain elements comprising one or more positive voltage-to-frequency gain elements and one or more negative voltage-to-frequency gain elements. The controller is configured to adjust the magnitude of the capacitance by adjusting the gain provided by respective ones of the gain elements in an alternating sequence of the positive voltage-to-frequency gain elements and the negative voltage-to-frequency gain elements. | ||||||
| 198 | Fractional-N Frequency Synthesizer Incorporating Cyclic Digital-To-Time And Time-To-Digital Circuit Pair | US14831784 | 2015-08-20 | US20160056827A1 | 2016-02-25 | Gerasimos S. Vlachogiannakis; Augusto Ronchini Ximenes; Robert Bogdan Staszewski |
| A novel and useful look-ahead time to digital converter (TDC) that is applied to an all digital phase locked loop (ADPLL) as the fractional phase error detector. The deterministic nature of the phase error during frequency/phase lock is exploited to achieve a reduction in power consumption of the TDC. The look-ahead TDC circuit is used to construct a cyclic DTC-TDC pair which functions to reduce fractional spurs of the output spectrum in near-integer channels by randomly rotating the cyclic DTC-TDC structure so that it starts from a different point every reference clock thereby averaging out the mismatch of the elements. Associated rotation and dithering methods are also presented. The ADPLL is achieved using the look-ahead TDC and/or cyclic DTC-TDC pair circuit. | ||||||
| 199 | Fractional-N All Digital Phase Locked Loop Incorporating Look Ahead Time To Digital Converter | US14831781 | 2015-08-20 | US20160056825A1 | 2016-02-25 | Gerasimos S. Vlachogiannakis; Augusto Ronchini Ximenes; Robert Bogdan Staszewski |
| A novel and useful look-ahead time to digital converter (TDC) that is applied to an all digital phase locked loop (ADPLL) as the fractional phase error detector. The deterministic nature of the phase error during frequency/phase lock is exploited to achieve a reduction in power consumption of the TDC. The look-ahead TDC circuit is used to construct a cyclic DTC-TDC pair which functions to reduce fractional spurs of the output spectrum in near-integer channels by randomly rotating the cyclic DTC-TDC structure so that it starts from a different point every reference clock thereby averaging out the mismatch of the elements. Associated rotation and dithering methods are also presented. The ADPLL is achieved using the look-ahead TDC and/or cyclic DTC-TDC pair circuit. | ||||||
| 200 | DC-Coupled Buffer Circuit For High Speed Oscillators | US14831119 | 2015-08-20 | US20160056799A1 | 2016-02-25 | Augusto Ronchini Ximenes; Robert Bogdan Staszewski |
| A novel and useful LC-tank digitally controlled oscillator (DCO) incorporating a split transformer configuration. The LC-tank oscillator exhibits a significant reduction in area such that it is comparable in size to conventional ring oscillators (ROs) while still retaining its salient features of excellent phase noise and low sensitivity to supply variations. The oscillator incorporates an ultra-compact split transformer topology that is less susceptible to common-mode electromagnetic interference than regular high-Q LC tanks which is highly desirable in SoC environments. The oscillator, together with a novel dc-coupled buffer, can be incorporated within a wide range of circuit applications, including clock generators and an all-digital phase-locked loop (ADPLL) intended for wireline applications. | ||||||
QQ群二维码
意见反馈
意见反馈