1. A CIRCUIT ARRANGEMENT FOR MODIFYING A SERIES OR SEQUENCE OF BITS OF INFORMATION SO AS TO FREE SAID SEQUENCE FROM POSSIBLE ERRORS, THE INFORMATION CONTENT OF WHICH IS CONTAINED IN BLOCKS INCLUDING SEVERAL SUCCESSIVE SYMBOLS OF BINARY DIGITS COMPRISING IN COMBINATION: A SHIFT REGISTER HAVING AN INPUT AND INCLUDING A CHAIN OF BISTABLE ELEMENTS TO WHICH THE SEQUENCE OF BINARY DIGITS IS FED; AND A LOGICAL NETWORK INCLUDING AT LEAST ONE THRESHOLD ELEMENT CONNECTED WITH THE OUTPUTS OF AT LEAST TWO CONSECUTIVE BISTABLE ELEMENTS AND FOR EXCITING ITS OUTPUT WHEN A PREDETERMINED NUMBER OF ITS INPUTS, WHICH IS LESS THAN THE TOTAL NUMBER OF INPUTS, IS EXCITED, SAID LOGICAL NETWORK HAVING A SINGLE OUTPUT FOR DELIVERING AN OUTPUT SEQUENCE OF BITS OF INFORMATION WHICH CORRESPONDS ESSENTIALLY TO THE SEQUENCE INITIALLY APPLIED TO THE REGISTER INPUT AND DEPENDENT UPON THE POSSIBLE ERRORS CONTAINED THEREIN.