| Document | Document Title |
|---|---|
| US09654421B2 |
Providing real-time interrupts over ethernet
In one embodiment, a method includes sending a request to one or more distributed fabric protocol (DFP) system members in order to retrieve one or more events from the one or more DFP system members, receiving one or more acknowledgements to the request from the one or more DFP system members at a local network switch of a DFP system master, upon receipt of at least one packet in which the one or more events are encapsulated as data: decoding the at least one packet to retrieve details of the one or more events using a dedicated processor of the DFP system master, creating and sending a message signaled interrupt (MSI) comprising the details of the one or more events to a local processor of the DFP system master using the dedicated processor, and reading the MSI using the local processor of the DFP system master. |
| US09654415B2 |
Information processing system, management server group, and server management program
This invention includes an application server for executing an application and transmitting the execution results to a terminal or other such device connected to a network, and a management server for allocating the application and data on an application server and a storage device, respectively, wherein the management server reallocates the application execution site using: a procedure for obtaining device location information from a device via an application server and selecting, from the location information, an application server that will be the application migration destination; a procedure for indicating the migration-destination application server to the migration-source application server; and a procedure for migrating the application and the data between the application servers. |
| US09654413B2 |
Method, device, and system for implementing network access, and network system
Disclosed are a method, device, and system for implementing network access, and a network system. The method comprises: in the case that a terminal requests to access a webpage, a server determining content of the webpage that the terminal requests to access; and the server searching for a webpage, used as a reference webpage, with relevant content matching the content of the webpage, and providing information of the found reference webpage for the terminal. The present invention can enable a user terminal to obtain multiple associated access results by performing webpage access once. Even though the terminal cannot for some reason access a webpage originally expected to be accessed, or content of a webpage originally expected to be accessed cannot meet a user requirement, has a bad display effect, or even cannot be displayed, other webpages with associated or same content can be provided for the terminal, so that a webpage that comprises sufficient information, has a better display effect, and is securer is provided for the terminal, thereby avoiding an additional access operation of the terminal and improving the browsing efficiency and experience of a user. |
| US09654411B2 |
Virtual machine deployment and management engine
A virtual machine deployment and management engine deploys virtual machines to physical host computers based on a deployment time matrix. The deployment time matrix specifies approximate amounts of time used to clone or deploy a virtual machine from every host computer to every other host computer. The virtual machine deployment and management engine selects a deployment path based on the deployment times and executes the clone or deploy operations. |
| US09654407B2 |
Communication systems and methods having reduced frame duration
A transmitter arrangement using randomization is disclosed. The arrangement includes one or more randomizers, a measure component and a frame select component. The one or more randomizers are configured to generate one or more randomized frames from an original frame. The measure component is configured to measure a criterion for the original frame and the one or more randomized frames. The frame select component is configured to select a frame for transmission from the one or more randomized frames and the original frame. The selection is performed according to the measured criteria, such as frame duration. |
| US09654405B2 |
Effective intra-frame refresh in multimedia communications over packet networks
Systems and methods of performing intra-frame refresh in multimedia communications over lossy packet networks, in which a video receiver can provide packet loss feedback information to a video transmitter, and the video transmitter can respond to the feedback information, in a manner that makes efficient use of available bandwidth. By providing one or more PLI messages from the video receiver to the video transmitter based on criteria related to the detection of an eventual missing video packet and/or the determination that the quality of a current reference frame is bad, and by pausing the providing of GNACK messages from the video receiver to the video transmitter while the PLI messages are being provided to the video transmitter, the total number of video packets required for transmission/retransmission can be reduced, thereby limiting the impact of the transmitted/retransmitted video packets on the available bandwidth while enhancing the video QoE of system users. |
| US09654402B2 |
Telecommunication quality of service control
Different quality of service policies are enforced for packets from traffic streams of different type in a communication network, according to the type of traffic types of traffic. A learning phase and an operation phase are provided. The learning phase teaching by example of characteristics that must be used to distinguish the different types of traffic. In the learning phase, an indication is received of a quality of service policy that is required for user applications of a selected type. An indication is provided indicating execution of a user application of said type in a user domain and characteristics of packet traffic are derived from inspection of packets transmitted through the communication network to and/or from the user domain during the indicated execution. In the operation phase packet traffic in the network to and/or from the user domain is inspected. It is detected whether observed characteristics of the packet traffic match the derived characteristics. When a match is detected, enforcement of the quality of service policy in the network to packet traffic of the selected type of user application is triggered. |
| US09654399B2 |
Methods and devices in an IP network for congestion control
The invention relates to a method 30 in a packet forwarding device 2 in an Internet Protocol, IP, network 10 for congestion control. The method 30 comprises: receiving 31 an IP packet 20 originating from a first network node 11 and addressed to a second network node 3; determining 32 a congestion status on a network path from the second network node 13 to the first network node 11; and entering 33, for a congestion status indicating congestion, congestion information into a header 21, 22 of the IP packet 20, the congestion status congestion information notifying the second network node 13 about congestion present on the network path. The invention also relates to a packet forwarding device 12, a computer program 43 and computer program product 44. |
| US09654384B2 |
Asymmetrical link aggregation
According to one embodiment, a method for asymmetrical link aggregation includes detecting a link change corresponding to a previously selected port of a first set of ports used to forward frames to one of a plurality of aggregation switches connected via the first set of ports to an access switch. The method also includes re-selecting, using the access switch, a port of the first set of ports according to a distribution algorithm that ensures that all frames with a given source address are forwarded using a single port and causes frames with different source addresses to be distributed uniformly among the first set of ports in response to detecting the link change. Also, the method includes generating and sending a fake reverse address resolution protocol (RARP) frame including the given source address of the frame from the re-selected port in response to detecting the link change. |
| US09654381B2 |
Differentiated routing system and method
A differentiated routing system is provided for routing a communication service according to an access point of a subscriber terminal to a first network domain. The system includes a computing system executing a core routing engine (CRE) that receives a request for a communication service from the subscriber terminal. When the communication service is to be routed to a second network domain, the CRE identifies an access point at which the subscriber terminal accesses the first network domain, includes a tag in the request according to the identified access point. The tag includes information to be used by the second network domain for routing the communication service. The CRE then transmits the request to the second network domain. |
| US09654378B2 |
Link addition to a network of linked nodes
A method of adding a link to a network of linked nodes is provided. Received scoring information includes a first node identifier, a second node identifier, and a link value. The link value is determined using an analytic model. A first anchored network record for which a first node associated with the first node identifier is an anchor is identified. A first link record is added to the identified first anchored network record using the first node identifier, the second node identifier, and the link value. A first node record associated with the second node identifier is added to the identified first anchored network record. A node record is identified for the first node in the identified anchored network record. A network score value included in the identified node record is computed based on the link value. The identified node record is updated with the computed network score value. |
| US09654377B2 |
Per port ethernet packet processing mode by device type
A method and apparatus for enabling software processing are described including receiving a dynamic host configuration protocol request form a client device, determining if the client device has a vendor specific identifier, determining a switch port to which the client device is connected, increasing a count of devices connected to the switch port, determining if the count is greater than a predetermined threshold and if the switch port is not already in software mode, placing the switch port in software mode if the count is greater than the predetermined threshold and if the switch port is not already in the software mode and saving the media access control address and the switch port to which the client device is connected. |
| US09654374B2 |
Method and system for stream testing by using switching hub
The present invention provides a method for stream testing by a switching hub including the steps of generation a test data stream by the switching hub and testing a plurality of DUTs by using the test data stream. A first port of the switching hub transmits port mirroring to a second port of the switching hub. A packet is transmitted through a physical cable from the first port. The first port and the second port are added to a first virtual local area (VLAN) in a native manner. The second port receives a test packet in a self-loop mode. The test data stream is created by repeatedly transmitting the test packet from the second port. In addition, the present invention further provides a system for stream testing by a switching hub. |
| US09654373B2 |
Method and system for interference detection and mitigation
In a method for adjusting the modulation of information onto subcarriers transmitted on a network, a first modulation profile of a network node on the network is set a first density. A plurality of messages in support of a link maintenance operation (LMO) on the network are monitored. The first modulation profile of the network node is updated to a second modulation profile having a second density. The updating is based on the monitored messages. Interference is detected by determining that a link between the first network node and a second network node on the network is not conveying a predetermined class of messages correctly. The first network node is set to a third modulation profile more robust than the first and second modulation profiles in response to the detected interference. The third modulation profile is common to each network node on the network. |
| US09654371B2 |
Determination of system performance parameters in heterogeneous network environments
A method of determining system performance parameters, such as delay, present in a network where the network is one of a plurality of heterogeneous networks in a communication system. The communication comprises a first network and a first node, both controlled by a first network operator, and a second network controlled by a second network operator. The first node is located in the second network. The method comprises the steps of: the first node communicating with at least one other node; the first node obtaining system-related information as a result of this communication; the system-related information being used to derive the system performance parameters of the second network. |
| US09654369B2 |
Mobile terminal network port management method and device
Disclosed is a mobile terminal network port management method and device. The method includes: after PPPOE dial up completes, scanning current mobile network equipment port numbers and acquiring currently occupied mobile network ports; detecting and analyzing whether the currently occupied mobile network ports are virtually occupied ports or not; if yes, releasing said virtually occupied ports. The abovementioned technical solution solves an existing problem of possible virtual occupancy of network ports after a PPPOE connection is established, thereby greatly enhancing availability of the mobile terminal and improving the user experience on the terminal. |
| US09654365B2 |
Selection of message passing collectives in presence of system noise
Consideration of system jitter in selecting a “message passing collectives algorithm” used in a message passing interface. A set of multiple message passing collectives algorithms are ranked against each other with at least some consideration of relative jitter-related performance as between the algorithms. The consideration of jitter includes consideration of “system jitter” (OS jitter and/or network jitter). In some embodiments, multiple rankings are performed for different levels of system jitter. |
| US09654361B2 |
Dynamic collection of network metrics for predictive analytics
In one embodiment, data is received at a device regarding a network-monitoring process in which one or more nodes in a network export network metrics to one or more collector nodes. A change to the network-monitoring process is determined based on the received data. The device also adjusts the network-monitoring process to implement the determined change. |
| US09654360B1 |
Coordinating analytics between media player and server
A method includes receiving a client report including an identifier and client analytics data, the client report received from a client device and the client analytics data associated with a media stream received by the client device from a streaming server. The method further includes receiving a server report including the identifier and server analytics data, the server report received from the streaming server. The method further includes, based on determining that the client report and the server report include the identifier, determining that the client analytics data and the server analytics data are correlated. |
| US09654357B2 |
Telecommunication networks
A mobile telecommunications network includes a core and a radio access network having a radio for wireless communication with mobile terminals registered with the network. The radio access network includes a controller operable to control the use of network resources by the mobile terminals. The controller may include an application programming interface, API, which provides a consistent interface to a multiplicity of applications hosted on the control mean. The controller may be provided at an access node site and/or a gateway site. |
| US09654354B2 |
Framework supporting content delivery with delivery services network
A framework supporting content delivery includes a plurality of devices, each device configured to run at least one content delivery (CD) service of a plurality of CD services. The plurality of CD services include delivery services forming one or more delivery service networks. |
| US09654348B2 |
User interface for managing and viewing synchronization settings in a synchronization system
In a synchronization system, the present invention provides an improved user interface through which a user can view and manage settings associated with the user's account in the synchronization system. In the preferred embodiment, a column is displayed for each electronic device associated with the user's account in the synchronization system. In each column is a visual representation of items (e.g., folders) that are (1) backed up, remotely accessible and/or synchronized in the synchronization system and (2) located on the electronic device associated with such column. For each item that is synchronized across multiple devices, all the visual representations of such item in the columns are aligned across a single row in the interface. In the preferred embodiment, there is an arrow, or other visual indicator, between the visual representations of such items to indicate that the items are synchronized. |
| US09654345B2 |
Analyzing data communication in a process control or substation automation system
A method, an engineering tool, and a computer program element for analyzing a communication of secondary devices in a Substation Automation System for a substation are disclosed. The secondary devices are connected to a communication network for controlling an industrial process, which industrial process can include a plurality of operational aspects of primary devices. Sender secondary devices are configured to send data packets, which can include a multitude of data objects, to predetermined receiver secondary devices via the communication network, wherein the data packets transmitted via the communication network are captured, a functional interrelation or operational aspect of the secondary devices and the primary devices is retrieved from an SCD-file representing the formal configuration of the substation is retrieved, and the secondary devices are grouped according to the retrieved operational aspect and a time sorted graphical representation of the data objects, the secondary devices and the operational aspects is generated. |
| US09654342B2 |
Bandwidth configurable IO connector
Systems and methods of interconnecting devices may include an input/output (IO) interface having one or more device-side data lanes and transceiver logic to receive a bandwidth configuration command. The transceiver logic may also configure a transmit bandwidth of the one or more device-side data lanes based on the bandwidth configuration command. Additionally, the transceiver logic can configure a receive bandwidth of the one or more device-side data lanes based on the bandwidth configuration command. |
| US09654331B1 |
System and method for recovery of customer premise equipment information on an access concentrator
A method is provided in one example and includes determining that an access concentrator has lost customer premise equipment information. The method also includes obtaining the customer premise equipment information that is lost by evaluating Neighbor Discovery data and dynamic host configuration protocol version six (DHCPv6) query data. In more specific implementations, the method may include communicating a Bulk Leasequery message; receiving a response to the Bulk Leasequery message; and filtering out cable modem identifiers from the response to the Bulk Leasequery message. |
| US09654328B2 |
Methods and systems for implementing a cache model in a prefetching system
The present invention relates to systems and methods of enhancing prefetch operations. One potential method comprises fetching an object from a page on a web server. The method may further include storing, at a proxy server, caching instructions for the fetched object. The proxy server may be connected with the client and the object is cached at the client. Furthermore, the method may include identifying a prefetchable reference to the fetched object in a subsequent web page and using the caching instructions stored on the proxy server to determine if a fresh copy of the object will be requested by the client. Further, the method may include, based on the determination that the object will be requested, sending a prefetch request for the object using an If-Modified-Since directive, and transmitting a response to the If-Modified-Since directive prefetch request to a proxy client. The proxy client may then either serve the response to the client or a copy of the object stored at the proxy client, depending on the request for the object from the client. |
| US09654325B2 |
Method of reception and receiver for single-carrier cyclic waveform coded serial digital transmission
The invention relates to a method of receiving digital data transmitted on a coded serial digital transmission modulated on a noisy channel with non-stationary equalization attenuation. Digital data are stored associating a value of quality of transmission with the information elements received, and a mutual information value Ik is computed for each value of the quality of transmission. The value of quality of transmission consists of an equivalent signal/noise plus interference ratio calculated as a function of the method of equalization on the basis of various signal/channel noise ratio values measured for the various temporal symbols of information elements received of the signal received corresponding to one and the same information element and according to interference due to the waveform. |
| US09654324B2 |
System and method for grassmannian signaling in a broadband network
An embodiment method includes determining, by a first network device, an equivalent coherence time of a narrowband network corresponding to the broadband network in accordance with a channel coherence time and a coherence bandwidth of the broadband network. The method further includes structuring, by the first network device, a Grassmannian symbol in accordance with the equivalent coherence time, generating, by the first network device, Grassmannian symbol sections by partitioning the Grassmannian symbol in accordance with the coherence bandwidth, and transmitting, by the first network device to a second network device, the Grassmannian symbol sections on subchannels within the coherence bandwidth. |
| US09654323B2 |
Data routing for OFDM transmission based on observed node capacities
Methods and systems are described for causing orthogonal frequency division multiplexing (OFDM) transmission of various portions of data via various nodes. For example, a first portion of the data may be transmitted, via a first node and using OFDM, to at least a second node. Based on one or more observed capacities associated with one or more nodes (such as the first node and/or another node), it may be determined that a second portion of the data is to be routed via a different node (such as a third node) for transmission. The second portion of the data may be transmitted, via the third node and using OFDM, to at least the second node. |
| US09654317B2 |
Modulating system adapted to generate a multi-level quadrature amplitude modulation
A modulating system (14) adapted to generate a multi-level quadrature amplitude modulation, includes: a first number of first optical channels (24_1), each of the first optical channels (24_1) including a modulating device (28), and a second number of first optical channels (24_1) each including a first phase shifting unit capable of introducing a phase shift of π, and a first number of second optical channels (24_2), each of the second optical channels (24_2) being associated bijectively with one of the first optical channels (24_1), each of the second optical channels (24_2) including the same elements as the first optical channel (24_1) with which the second optical channel (24_2) is associated and a second phase shifting unit able to introduce a phase shift of π/2. |
| US09654316B2 |
Transmission method, transmitter, reception method, and receiver
In order to transmit a codeword that is generated based on a quasi-cyclic low-density parity-check coding scheme and consists of N cyclic blocks each consisting of Q bits, a bit permutation is applied to the bits of the codeword, a plurality of constellation blocks each consisting of G×M bits are generated, and a block permutation is applied to the constellation blocks. The bit permutation is adopted for each of N/M sections each consisting M cyclic blocks such that the constellation blocks each consist of G×M bits from M distinct cyclic blocks of the associated section. The block permutation is equivalent to writing the constellation blocks into a matrix with R rows and (Q/(k×G)) columns and reading out the constellation blocks column by column from the matrix, where R is k×(N/M), and k is a positive integer. |
| US09654314B2 |
Joint transmitter and receiver map algorithm for enhancing filtering tolerance in a bandwidth-limited system
A system for optimizing signal quality in an optical communication system is provided including a transmitter for converting digital signals to optical signals, the transmitter including a transmitter digital signal processing chip including a pre-distortion logic and a transmitter look-up table (LUT). A receiver is operatively coupled to the transmitter for receiving and converting the optical signals from the transmitter to digital signals. The receiver includes a receiver digital signal processing chip including a correction logic and a receiver look-up table (LUT). The transmitter LUT is constructed by scaling the receiver LUT by a weight factor and is iteratively updated based on a weighted sum of the receiver LUT. |
| US09654311B2 |
PAM data communication with reflection cancellation
The present invention is directed to data communication systems and methods. More specifically, embodiments of the present invention provide a communication system that removes reflection signals. A digital data stream is processed through both tentative path and the main path. The tentative path uses a first DFE device and a reflection cancellation circuit to generate a correction signal for removing reflection signal from the digital data stream. A second DFE device removes ISI and other noises from the corrected digital data stream. There are other embodiments as well. |
| US09654310B1 |
Analog delay cell and tapped delay line comprising the analog delay cell
An analog delay cell is provided that includes a transconductance-capacitance stage and an inductive transimpedance amplifier stage that provides an all-pass transfer function. In another embodiment, an adaptive analog delay cell including a transconductance (gm) plus capacitance (C) stage and an inductive-capacitance transimpedance amplifier (TIA) stage with digitally programmable phase-shift is provided. The adaptive analog delay cell increases the phase-shift by incorporating an LC network in the feedback path of the transimpedance stage. The disclosed analog delay cells can be used to provide delays in a tapped delay line. Also, the disclosed analog delay cells may be used to perform the multiplier and summation functions of a tapped delay line in addition to providing the delays. In another embodiment, the transimpedance amplifier stage includes an inductive-capacitive transimpedance amplifier stage. |
| US09654307B1 |
Communication apparatus
A communication apparatus for correcting a situation of a spectrum inverted signal includes a channel estimation module and an equalization module. The channel estimation module determines a channel estimation parameter, and receives at least one frame signal to generate a convolution restored frame signal corresponding to the frame signal. The equalization module includes a first computation circuit and a second computation circuit. The first computation circuit receives the channel estimation parameter and the convolution restored frame signal to generate a transformation channel estimation parameter and a transformed convolution restored frame signal. The second computation circuit receives the transformed channel estimation parameter and the transformed convolution restored frame signal to generate an original frame signal corresponding to the frame signal. The first computation circuit further feeds back a transient original frame signal to the channel estimation module to update the channel estimation parameter. |
| US09654306B1 |
System and method for multi-source channel estimation
A method for associating signal sources and paths includes determining secondary paths of a signal received at a reception point, wherein the signal reflects off one or more reflective surfaces before being received at the reception point, determining mirror sources of the secondary paths in accordance with locations of the one or more reflective surfaces and a main source of the signal, determining associations between the secondary paths and the mirror sources based on cross points at which the signal reflected off the one or more reflective surfaces, thereby obtaining path-source associations, and instructing use of the path-source associations in multi-source channel estimation. |
| US09654304B2 |
Method and apparatus for sending transparent interconnection of lots of links data frame
A method for sending a Transparent Interconnection of Lots of Links (TRILL) data frame, comprising acquiring a user virtual local area network (VLAN) or a combination of a user VLAN and a user multicast medium access control (MAC) address in a first protocol packet, and a first port identifier; storing a correspondence there-between in a forwarding table; searching, according to the user VLAN or the combination of the user VLAN and the user multicast MAC address in a TRILL data frame received, the forwarding table for a second port identifier corresponding to the VLAN or the combination of the user VLAN and the user multicast MAC address in the TRILL data frame, and forwarding the TRILL data frame from a pseudo wire (PW) port corresponding to the second port identifier. |
| US09654302B2 |
Enhanced carrier sense multiple access (CSMA) protocols
Power Line Communications (PLC) device for enhanced carrier sense multiple access (CSMA) protocols are described. The PLC device includes a modem, an AC interface and a PLC engine. The engine is configured for transmitting PLC packets over a plurality of electrical wires using a particular channel. Transmitting a normal priority packet may include attempting to access a communications channel to transmit a frame after a backoff time proportional to a randomly generated number within a contention window (CW), the CW having an initial value carried over from a previous transmission of a different frame. Additionally or alternatively, some of techniques described herein may facilitate the spreading of the time over which devices attempt to transmit packets, thereby reducing the probability of collisions using, for example, Additive Decrease Multiplicative Increase (ADMI) mechanisms. |
| US09654298B2 |
Signature # efficient real time credentials for OCSP and distributed OCSP
Providing information about digital certificate validity includes ascertaining digital certificate validity status for each of a plurality of digital certificates in a set of digital certificates, generating a plurality of artificially pre-computed messages about the validity status of at least a subset of the set of digital certificate of the plurality of digital certificates, where at least one of the messages indicates validity status of more than one digital certificate and digitally signing the artificially pre-computed messages to provide OCSP format responses that respond to OCSP queries about specific digital certificates in the set of digital certificates, where at least one digital signature is used in connection with an OCSP format response for more than one digital certificate. Generating and digitally signing may occur prior to any OCSP queries that are answered by any of the OCSP format responses. Ascertaining digital certificate validity status may include obtaining authenticated information about digital certificates. |
| US09654292B2 |
Secure password management systems, methods and apparatuses
The systems, methods and apparatuses described herein provide a computing environment for authenticating a user. An apparatus according to the present disclosure may comprise a non-volatile storage, a user interface, and a password engine. The password engine is configured to retrieve two or more predetermined prompts from the non-volatile storage, present the two or more predetermined prompts on the user interface to a user in a random order, receive a first set of input(s) in response to the two or more predetermined prompts, create an encryption keyword from the received first set of input(s) according to an original order of the two or more predetermined prompts stored in the non-volatile storage, and use the encryption keyword to authenticate the user. |
| US09654289B2 |
Method for generating a pseudorandom sequence, and method for coding or decoding a data stream
The present invention relates to a method for coding a first data stream and a method for decoding a second data stream wherein the coding is the result of comparing the first data stream with a third data stream formed by a pseudorandom sequence by means of an exclusive comparison operation (XOR). Specifically, the invention relates to the methods based on hyperchaotic coding methods for generating the pseudorandom sequences used in coding and decoding. |
| US09654288B1 |
Securing group communications
The secure messaging app described herein allows a user to create a secure social feed in order to share content with just a few friends or thousands of recipients. The user encrypts their content and then publishes the encrypted content to the secure social feed. Accordingly, only authorized recipients can decrypt and view the content. Furthermore, the user may administer the secure social feed to manage the addition and/or removal of users from the secure social feed. Further, the user periodically updates the parameters of the secure social feed to manage users' access to the feed. |
| US09654287B2 |
Mobile secret communications method based on quantum key distribution network
A mobile secret communications method based on a quantum key distribution network, comprises the following steps: a mobile terminal registering to access the network and establishing a binding relationship with a certain centralized control station in the quantum key distribution network; after a communication service is initiated, the mobile terminals participating in the current communication applying for service keys from the quantum key distribution network; the quantum key distribution network obtaining addresses of the centralized control stations participating in service key distribution during the current communication, designating a service key generation centralized control station according to a current state indicator of each centralized control station; the service key generation centralized control station generating service keys required in the current communication and distributing the keys to the mobile terminals participating in the current communication. |
| US09654286B2 |
Content gathering using shared key
The gathering of content (such as a file) from a variety of different sources. Rather than provide the whole content, a given one of the sources instead provides only a portion of the information represented by the content. The source also provides a share of, but not the entirety of, the shared secret that will be used to decode. For instance, in one embodiment, the source might encode only a portion of the content using the shared key, and then transmit the encoded portion. As an alternative, the source might encode the entire content, and then transmit a portion of that encoded content. Thus, the transmitter has security with their private content, while still allowing widely available content to be transferred for the benefit of the greater whole. |
| US09654272B2 |
Method for multi-input multi-output communication in large-scale antenna system
Disclosed is a method for multi-input multi-output transmission of a base station in a wireless communication system. The method includes obtaining channel information of one or more terminals, classifying the one or more terminals into one or more classes and one or more groups dependent on the class based on the channel information, determining a group beamforming matrix for each of the one or more groups, performing group beamforming transmission on terminals belonging to each of the one or more groups based on the group beamforming matrix, obtaining single user-channel quality indicator (SU-CQI) information and interference signal information of each of the terminals belonging to each of the one or more groups, and scheduling the terminals based on the SU-CQI information and the interference signal information. |
| US09654269B2 |
Methods and arrangements for an acknowledgement in wireless networks
Embodiments may comprise physical layer logic to implement a new, short acknowledgement. Embodiments may store the short acknowledgement on a machine-accessible medium. Some embodiments may determine and transmit a communication with the short acknowledgement. Further embodiments may receive and detect communications with the short acknowledgement. The short acknowledgement may reduce power consumption and reduce on-the-air time. |
| US09654266B2 |
Method for transreceiving downlink control information in wireless access system and apparatus for same
In the present invention, disclosed are a method for transreceiving downlink control information in a wireless access system supporting an enhanced physical downlink control channel (E-PDCCH), and an apparatus for same. More particularly, the method comprises the steps of: transmitting through a physical broadcast channel (PBCH) information with respect to a resource region of a search space that is set inside a physical downlink shared channel (PDSCH) or the enhanced physical downlink control channel (E-PDCCH); and transmitting the downlink control information to a user equipment through the search space. |
| US09654264B2 |
Beam forming using a dual polarized antenna arrangement
There is provided beam forming using a dual polarized antenna array. A first set of reference signals for acquiring channel state information is alternatingly transmitted using a dual polarized antenna array in a first polarization direction and in a second polarization direction, respectively. Quantized channel information based on the first set of reference signals is received from a radio transceiver device. Angular information relating to the radio transceiver device is determined based on the quantized channel information. Transmission beams for transmission to the radio transceiver device are determined. The transmission comprises precoder vectors and have relative orthogonal polarizations for beam forming according to the angular information. |
| US09654261B2 |
Method and a system for beam coordination between base stations in wireless cellular systems and computer program thereof
A method involving coordinating resources between a victim and an aggressor base station in massive MIMO systems, whereby only those specific beams involved in the interference scenario are coordinated in time and/or frequency domains without affecting other resources committed to other users as well as legacy users. Also disclosed is a system and computer program configured to implement the method. |
| US09654238B2 |
Method and system for remote television replay control
A method, system, computer medium, and other embodiments for integrating unrelated web hosted services with stand-alone media-based devices are provided. Users can access and control the media-based device conveniently with a web-browser through various portals on the Internet. In one embodiment, users access the media-based device through one or more unrelated web portals, so as to control and to program the media-based device in a single web session, and to see information both stored on the media-based device and originating from third-party online sources of information and services in a single integrated presentation. |
| US09654237B2 |
Broadcast method and system
A method and system for airing broadcast signals is disclosed. Preferably, the system includes a production truck interface panel receiving a broadcast signal. A transmission relay circuit relays the signal from the interface panel to a broadcast network, and preferably including a broadcast signal detection circuit, and a signal processing circuit. The detection circuit determines a signal type of the broadcast signal, and the signal processing circuit processes the determined signal type. The system preferably further includes an operations control station displaying the determined type of broadcast signal. The method for airing broadcast signals over the broadcast network preferably includes the steps of providing the broadcast signal to the transmission relay circuit, detecting the broadcast signal type with the broadcast signal sensing and discerning circuit; and reconfiguring the signal processing circuit when the configuration of the signal processing circuit does not support transmission of the determined broadcast signal type. |
| US09654236B2 |
Method and apparatus for configuring configuration information at user equipment in a mobile communication system
A method for configuring configuration information with a user equipment in a mobile communication system is provided. The method includes determining, upon receipt of a Physical Uplink Control Channel/Sounding Reference Signal (PUCCH/SRS) release request from a lower layer, whether configuration information required for a transmission mode supporting Coordinated Multi-Point (CoMP) has been configured, and if the configuration information has been configured, reconfiguring a setting state of the configuration information. |
| US09654235B1 |
Wireless carrier signal analytic system
A method, device, computer-readable storage medium, and system for determining key performance indicators of a wireless RF signal received by an antenna from a signal source. A diagnostic device may receive signal of a carrier network from a primary antenna. The diagnostic device may transmit the signal to a mobile device that is registered on the carrier network. A mobile device may receive the signal from the diagnostic device, demodulate the signal, and determine key performance indicators of the signal. The key performance indicators may be displayed in real-time. This allows a technician to orient the primary antenna so that it receives a signal from the signal source with the highest quality key performance indicators it can receive. |
| US09654234B2 |
System and method for automatically time labeling repetitive data
An exercise assistance system labels sensor signals received from a movement measurement device to identify repetitions within the sensor signals. The movement measurement device can transmit motion data describing the user's movement to the exercise assistance system, and includes the sensor signals generated by one or more sensors in the movement measurement device. The exercise assistance system generates a combination signal from the received sensor signals and passes the combination signal through a low pass filter to generate a labeling signal. The exercise assistance system can generate three types of labels for the labeling signal identifying different parts of repetitions. The exercise assistance system labels the sensor signals using the generated labels and can identify repetitions in the labeled sensor signals using a classification model. |
| US09654231B1 |
Dynamically mitigating external interference in multi-band antenna systems
A device, method, and computer-readable medium are provided for mitigating signal interference at a base station. Signal interference can be generated from subcomponent levels at a base station (e.g., electronic antenna motors) due to non-optimal designs or electric ground interferences. Generally, when power is provided to such subcomponent(s), a noise or harmonic can be inadvertently generated, falling into one of the operating bands of the base station, and negatively impacting system performance. As such, embodiments can be configured to dynamically ascertain a noise baseline associated with the base station, determine that one or more of the subcomponents are at fault for interfering with the base station operating band(s), and mitigate the interfering signal for a period that least impacts system performance. |
| US09654226B1 |
Method and apparatus for characterization and compensation of optical impairments in InP-based optical transmitter
A method and apparatus for characterizing and compensating optical impairments in an optical transmitter includes operating an optical transmitter comprising a first and second parent MZ, each comprising a plurality of child MZ modulators that are biased at respective initial operating points. An electro-optic RF transfer function is generated for each of the plurality of child MZ modulators. Curve fitting parameters are determined for each of the plurality of electro-optic RF transfer functions and operating points of each child MZ modulator are determined using the curve fitting parameters. An IQ power imbalance is determined using the curve fitting parameters. Initial RF drive power levels are determined that compensate for the determined IQ power imbalance. The XY power imbalance is determined for initial RF drive power levels using the curve fitting parameters. The operating RF drive powers are determined that at least partially compensate for the first and second IQ power imbalances and for the XY power imbalance for the optical transmitter. |
| US09654221B1 |
Driver module for Mach Zehnder modulator
A single chip dual-channel driver for two independent traveling wave modulators. The driver includes two differential pairs inputs per channel respectively configured to receive two digital differential pair signals. The driver further includes a two-bit DAC per channel coupled to the two differential pairs inputs to produce a single analog differential pair PAM signal at a differential pair output for driving a traveling wave modulator. Additionally, the driver includes a control block having internal voltage/current signal generators respective coupled to each input and the 2-bit DAC for providing a bias voltage, a tail current, a dither signal to assist modulation control per channel. Furthermore, the driver includes an internal I2C communication block coupled to a high-speed clock generator to generate control signals to the control block and coupled to host via an I2C digital communication interface. |
| US09654220B2 |
High speed signal generator
A high-speed signal generator. A digital signal processing (DSP) block generates a set of N (where N is an integer and N≧2) parallel digital sub-band signals, each digital sub-band signal having frequency components within a spectral range between 0 Hz and ±Fs/2. A respective Digital-to-Analog Converter (DAC) processes each digital sub-band signal to generate a corresponding analog sub-band signal, each DAC having a sample rate of Fs. A combiner combines the analog sub-band signals to generate an output analog signal having frequency components within a spectral range between 0 Hz and ±NFs/2. |
| US09654216B2 |
Optical transmitter and waveform distortion correction method
An optical transmitter includes: a mapper configured to generate an electric-field-information signal from transmission data; a training-signal-generation section configured to generate a training signal; a training-signal-insertion section configured to insert the training signal into the electric-field-information signal; a driver configured to generate a drive signal from the electric-field-information signal into which the training signal is inserted; a modulator configured to generate an optical-modulation signal based on the drive signal; an optical receiver configured to generate an intensity signal indicating intensity of the optical-modulation signal; a training-signal-extraction section configured to extract an intensity-training signal corresponding to the training signal, from the intensity signal; a coder configured to generate a coded-training signal by coding the intensity-training signal extracted by the training-signal-extraction section using the training signal generated by the training-signal-generation section; and a distortion detection section configured to detect waveform distortion of the optical-modulation signal, based on the coded-training signal. |
| US09654211B2 |
Estimation apparatus and method for nonlinear distortion and receiver
Embodiments of the present disclosure provide an estimation apparatus and method for nonlinear distortion and a receiver. The estimation method for nonlinear distortion includes: sampling a band-limited analog signal to obtain a sampling sequence; calculating a nonlinear perturbation coefficient in nonlinear distortion estimation based on a Nyquist pulse; calculating a nonlinear perturbation term superimposed on a signal by using the nonlinear perturbation coefficient and the sampling sequence; and calculating a nonlinear distortion waveform by using the nonlinear perturbation term. With the embodiments of the present disclosure, not only any modulation formats are compatible, but also advantages of high precision and good adaptability may be achieved. |
| US09654206B1 |
Hub enabled single hop transport forward access
A satellite system is configured to receive and allow direct forwarding of traffic on a time slot by time slot basis without demodulation or decoding. The satellite system may be configured to receive waveforms and configured to separate a waveform of data from a waveform of control information. The satellite system may be configured to switch the waveform of data toward one or more terminals and configured to switch the waveform of control information toward a satellite control unit without demodulation or decoding of the waveforms. A method for satellite communication is also provided. |
| US09654203B2 |
Satellite system architecture for coverage areas of disparate demand
Disclosed is a satellite communication system that allocates bandwidth to maximize the capacity of the communication system while providing service to geographical areas having different demands. A smaller portion of the frequency spectrum can be allocated for subscriber beams that supply service to low demand areas. A larger portion of the frequency spectrum can be provided to subscriber beams that provide access to high demand areas. Allocation of bandwidth can be determined by the amount of demand in low demand areas versus the amount of demand in high demand areas. High demand gateways are physically located in low demand subscriber beams, while low demand gateways are physically located in high demand subscriber beams, which prevents interference. |
| US09654192B2 |
Apparatus and method for channel feedback in multiple input multiple output system
A method and apparatus for a channel feedback by a signal transmitting device in a Multiple Input Multiple Output (MIMO) system are provided. The method includes transmitting a pilot in which a compression rate is reflected to a signal receiving device; receiving channel related information on a compressed channel from the signal receiving device; and performing a precoding based on the channel related information. The apparatus includes a transmitting unit configured to transmit a pilot to which a compression rate is reflected to a signal receiving device; a receiving unit configured to receive channel related information on a compressed channel from the signal receiving device; and a precoding unit configured to perform a precoding based on the channel related information. |
| US09654187B2 |
Efficient uplink transmission of channel state information
A User Equipment in a wireless communication network includes a multiplicity of antennas, from which a subset of antennas is selected using a selection scheme synchronized to the network. A set of sub-carriers is selected from a plurality of sub-carriers using a selection scheme synchronized to the network. The UE receives a plurality of known reference symbols over the selected set of sub-carriers and through the selected subset of antennas. A frequency response for each selected sub-carrier is estimated over only the selected subset of antennas. The results are quantized and transmitted to the network on an uplink control channel. |
| US09654184B2 |
Transmitter to receiver communication link in a wireless power system
A method and system for establishing a communication link in a wireless power system from a wireless power transmitter (WPT) to a wireless power receiver (WPR) is provided. A flux modulator is operably disposed in the WPT for dynamically changing the WPT's impedance so as to modulate a magnetic field produced on the transmitter coil when a primary voltage applied to the WPT. A flux demodulator is operably disposed in the WPR for receiving and demodulating a secondary voltage induced on a receiver coil due to the modulated magnetic field on the transmitter coil. The induction of the secondary voltage on the receiver coil due to the modulated magnetic field on the transmitter coil establishes the communication link from the WPT to the WPR. The flux demodulator is configured as an analog signal processing chain or a digital signal processing block for decoding information obtained from the WPT. |
| US09654183B2 |
System and method for transferring power to intrabody instruments
A system and method for transferring power includes a power transmitting unit for transmitting power and a power receiving unit for receiving power from the power transmitting unit. The power transmitting unit may be positioned outside a human body and the power receiving unit is located on an intrabody instrument adapted to be movable from the outside of the human body to inside the human body. The intrabody instrument may be a medical instrument connected to or incorporated within a robotic arm. The power transmitting unit may wirelessly transfer power to the power receiving unit in a continuous, non-interrupted manner. |
| US09654181B1 |
Dynamic transmitter signal envelope shaping control for NFC or RFID devices
Transmitter (TX) modulation envelope parameters are defined in RF standards (e.g., ISO 14443, NFC Forum, EMVCo). These envelope parameters include rise/fall times, modulation index, etc. For standards compliancy, these envelope parameters must be within the respective limits. For example, shaping parameters are influenced by detuning the antenna with a counterpart device like a card or mobile phone, or by thermal influences on the matching network. This disclosure describes an NFC or RFID device that is able to detect and measure the detuning on the antenna and/or the matching network change. With this information, the NFC or RFID device can dynamically control the shaping parameters of the envelope, instead of relying on one single static configuration setting for the transmitter. In particular, changes in the Q (quality) factor are used for dynamically controlling the transmitter signal envelope shape for compensating the effect of antenna detuning and/or matching network variation. |
| US09654180B2 |
NFC-enable mobile device, NFC reader and NFC system for supporting a plurality of proximity services
According to an aspect of the invention, an NFC-enabled mobile device for supporting a plurality of proximity services is conceived, wherein each supported proximity service corresponds to a specific operating system running on a specific secure element comprised in the NFC-enabled mobile device, wherein the NFC-enabled mobile device comprises a plurality of data sets and each data set corresponds to a supported proximity service, wherein the NFC-enabled mobile device is arranged to determine whether it supports an advertised proximity service, upon receipt of a service advertisement message comprising a unique identifier of the advertised proximity service from an NFC reader, by searching for the advertised proximity service in said data sets. |
| US09654179B2 |
Method and apparatus for forming associations and communicating between devices
The present invention relates to the field of proximity communications and especially methods for establishing associations, transferring power and communicating data between devices. Devices are proposed to interact with each other, initially by being brought into close proximity to initiate transfer of data that enables the device to communicate with other devices similarly brought together. The devices can be used as a controller or an appliance or both. There is also provided a power transfer mechanism for controller and appliance devices which do not have locally available power at the time the initial proximity action is taking place, so that the processes associated with the data transfer can take place regardless. There is also described a two part device, one part of which provides the proximity communications capability the other part does not have. |
| US09654178B2 |
Communication device
An MFP establishes a first communication link L1 by receiving an activation command and sending an OK command. The MFP receives first target data from a portable device by using the first communication link. The MFP generates second target data by processing the first target data. After receiving the first target data, the MFP disconnects the first communication link. The MFP establishes a second communication link by receiving the activation command and sending the OK command. The MFP sends the second target data to the portable device by using the second communication link. |
| US09654175B1 |
System and method for remote alert triggering
Systems and methods for triggering generation of an alert for delivery to a remote device are disclosed herein. The system can include memory having: a user profile database; and a content library database. The system can include a recipient user device and a supervisor device. The system can include a content management server that can: receive an electrical signal from the recipient user device, which electrical signal includes a request for initiation of a delivery sequence; trigger an incrementing timer based on receipt of the electrical signal; sequentially deliver the set of delivery data packets; automatically send a proposed time for communicatively coupling the recipient user and supervisor devices; and generate and send an alert. |
| US09654173B2 |
Apparatus for powering a communication device and methods thereof
Aspects of the subject disclosure may include, for example, a waveguide system for transmitting first electromagnetic waves via a coupler located in proximity to a transmission medium to generate second electromagnetic waves that propagate on an outer surface of the transmission medium, the transmission medium further providing a first power signal having a first operating frequency and a second power signal having a second operating frequency that differs from the first operating frequency. The waveguide system can further obtain energy from the first power signal for powering the waveguide system. Other embodiments are disclosed. |
| US09654171B2 |
Apparatus and method for jointly selecting the tap values and delays of the fingers for a rake receiver of two carriers
The present disclosure concerns receivers for use in nodes or devices that participate in wireless communications. In one exemplary embodiment, the receiver receives a first signal attributable to a first carrier and a second signal attributable to a second carrier. A first path searcher detects taps in the first signal attributable to the first carrier. A second path searcher detects taps in the second signal attributable to the second carrier. A channel tap selector selects, based on received energy values for taps detected by the first path searcher and the second path searcher, which tap values are to be used for taps of the receiver for both the first carrier and the second carrier. |
| US09654170B2 |
Method and apparatus for an adaptive filter architecture
A system that incorporates teachings of the subject disclosure may include, for example, a method for scanning a radio frequency spectrum for an available frequency band, selecting an available frequency band in the radio frequency spectrum even if the available frequency band is affected by radio frequency interference, measuring a signal strength in portions of the available frequency band, correlating the signal strength of each portion to generate a correlation factor, detecting radio frequency interference in the available frequency band according to the correlation factor, and generating tuning coefficient data to cause the filter apparatus to substantially suppress the radio frequency interference in the available frequency band. Other embodiments are disclosed. |
| US09654169B2 |
Apparatus and methods for multi-band radio frequency signal routing
Apparatus and methods for multi-band RF signal routing are provided herein. In certain configurations, a mobile device includes an antenna switch module, a diversity module, and one or more diversity antennas. The diversity module is electrically coupled to the one or more diversity antennas, and processes diversity signals received on the one or more diversity antennas to generate a high band (HB) signal, a mid band (MB) signal, and a low band (LB) signal. Additionally, the diversity module generates a combined LB/HB signal based on combining the LB signal and the HB signal, and provides the MB signal and the combined LB/HB signal to the antenna switch module. |
| US09654165B2 |
Accessory device and electronic device including the same
An accessory device is provided that covers an electronic device. The accessory device includes a plurality of members which are connected to each other to be pivoted with respect to each other. The plurality of members may be pivoted to maintain a viewing angle of the electronic device on a surface. |
| US09654161B2 |
Process for testing a compressor or a combustor of a gas turbine engine using a large compressed air storage reservoir
A process for testing a turbine of a gas turbine engine at high altitudes, where a large volume of compressed air is stored in a large reservoir of at least 10,000 m3 such as an underground storage cavern, compressed air from the storage reservoir is passed through heat exchanger to preheat the compressed air to a temperature that would normally be discharged from a compressor, the preheated compressed air is burned with a fuel in the combustor, and additional compressed air from the reservoir is passed through an injector located downstream from the turbine to produce a decreased pressure such that a low atmospheric condition at the turbine exit is simulated. |
| US09654160B2 |
Method and apparatus for processing signal interference
Embodiments of the present invention relate to a method and an apparatus for processing signal interference, including: splitting a first self-interference signal into at least two same sub self-interference signals, adjusting amplitudes and phases of the sub self-interference signals to obtain adjusted sub-signals, superposing the adjusted sub-signals and received signals, to obtain superposed sub-signals, filtering the superposed sub-signals by using filters of corresponding channels, to obtain wanted sub-signals, and merging each of the wanted sub-signals to obtain a complete wanted signal. Because received signals are separately filtered by using n different channels, it can be implemented that a self-interference signal can be effectively filtered out on each frequency band. |
| US09654159B2 |
Systems for and methods of using a mirrored wideband baseband current for automatic gain control of an RF receiver
Disclosed herein are systems for and methods of using a mirrored wideband baseband current for automatic gain control of an RF receiver. In an embodiment, a system includes an RF receiver having an adjustable gain and being configured to direct convert a received wideband RF signal to a wideband baseband current signal. The system further includes a current replicator coupled to the receiver and configured to generate a mirrored current of the wideband baseband current signal. The system further includes a wideband signal-level detector configured to receive the mirrored current from the current replicator, and to measure and output a signal-level value of the mirrored current. The system further includes an automatic gain-control circuit configured to receive the signal-level value from the wideband signal-level detector, and to adjust the gain of the receiver based at least in part on the received signal-level value. |
| US09654155B2 |
Cascode amplifier segmentation for enhanced thermal ruggedness
According to some implementation, a power amplifier includes a plurality of pairs of transistors, each pair of transistors including a common emitter transistor and a common base transistor arranged in a cascode configuration. The power amplifier further includes electrical connections implemented to connect the plurality of pairs in a parallel configuration between an input node and an output node. According to some implementations, the electrical connections are configured to distribute a collector current to all of the common base transistors to thereby reduce likelihood of damage to one or more common base transistors during a thermal run-away event. |
| US09654154B2 |
Radio frequency adaptive voltage shaping power amplifier systems and methods
Systems and method for improving operation of a radio frequency system are provided. One embodiment includes instructions to execute a coarse calibration to associate a first output power with a first operational parameter set; instruct the radio frequency system to transmit a signal based at least in part on the first operational parameter set and a base detrough function; determine performance metrics resulting from transmission of the signal; determine changes in the performance metrics resulting from operating the radio frequency based at least in part on the first operational parameter set and each of a plurality of augmented detrough functions; and associate a second operational parameter set with a second output power, in which the second operational parameter set includes one of the plurality of augmented detrough functions selected based at least in part on the changes that reduce margin between the performance metrics and performance metric thresholds. |
| US09654152B2 |
Service provider adaptive vehicle antenna
A vehicle may include a plurality of antennas each associated with a different radio frequency; and a modem including a radio-frequency transceiver and an antenna control processor configured to selectively connect a selected one or more of the plurality of antennas having a radio frequency matching at least one frequency associated with a desired service provider to the transceiver. The vehicle may also determine whether a service-provider-recommended alternate frequency is available, responsive to service provider signal strength being below a predefined signal strength; and if so, direct the modem to switch to an antenna associated with the alternate frequency, and otherwise, cycle to a next available antenna frequency. |
| US09654149B2 |
Multiple radio instances using software defined radio
In a first aspect an exemplary embodiment of the invention provides a method that includes instantiating a plurality of radio protocols, operating the plurality of radio protocols with an underlying physical layer, where each instantiation of a same radio protocol is embodied in a same code module and where each instantiation has associated data stored in a memory. The operating of the plurality of radio protocols comprises executing each instantiation of the radio protocols so that a portion of resources are shared between different instantiations of the radio protocols and different instantiations of radio protocols do not interfere with each other. |
| US09654146B2 |
Bi-directional parity bit generator circuit
A parity bit generator module is disclosed that operates in a first direction or a second direction. In the first direction, the parity bit generator module generates parity bits for a first input datastream having information bits and combines these parity bits with the information bits of the input datastream to provide a first output datastream. Otherwise in a second direction, the parity bit generator module separates information bits from a second input datastream and generates parity bits from the information bits of the second input datastream to provide a second output datastream having the parity bits. In various exemplary embodiments, the bi-directional parity bit generator is implemented as part of an encoding/decoding module and/or an error-correcting code (ECC) data storage device. |
| US09654144B2 |
Progressive effort decoder architecture
A memory device may include memory components to store data. The memory device may also include a processor that may decode a codeword associated with the data. The processor may receive the codeword and determine whether the codeword is independently decodable using a BCH decoder. The processor may then decode the codeword using the BCH decoder when the codeword is determined to be independently decodable using the BCH decoder. Otherwise, the processor may decode the codeword using a second decoder and the BCH decoder when the codeword is not determined to be independently decodable using the BCH decoder. |
| US09654140B1 |
Multi-dimensional run-length encoding
Methods and systems for multi-dimensional run-length encoding of data are provided. In one embodiment, a method for multi-dimensional run-length encoding of an unprocessed data file is provided. The method includes obtaining an admission key and determining a traversal path within a virtual multi-dimensional shape based on the admission key. The method also includes transforming unprocessed data of the unprocessed data file into a plurality of compressed data segments. Also, the method includes plotting the plurality of compressed data segments onto a plurality of data points along the traversal path to obtain a plurality of secured data segments. Further, the method includes generically sorting the plurality of secured data segments to obtain a plurality of generically sorted data segments, and writing the plurality of generically sorted data segments into a processed data file. |
| US09654139B2 |
High throughput binarization (HTB) method for CABAC in HEVC
Provided is an electronic device configured for high throughput binarization mode. The electronic device includes a processor and instructions stored in memory that is in electronic communication with the processor. The electronic device obtains a block of transformed and quantized coefficients (TCQs). The electronic device determines whether a high throughput binarization mode condition is met. If the condition is met, the electronic device uses the high throughput binarization mode to process the block. If the condition is not met, the electronic device does not use the high throughput binarization mode to process the block. The electronic device transmits the generated first or second bitstream to a decoder. |
| US09654135B2 |
AD converter including a capacitive DAC
An AD converter converts an analogue input voltage into a digital value including a most significant bit to a least significant bit. The AD converter includes: a common node; a capacitive DAC; a comparator; a successive approximation controller; and an integrator. The integrator includes first to Xth integrating circuits connected in a cascade arrangement, where X is an integer greater than or equal to two, and at least one feedforward path that each samples a residual voltage and outputs the sampled residual voltage to one of the second to Xth integrating circuits. |
| US09654132B2 |
Hybrid charge-sharing charge-redistribution DAC for successive approximation analog-to-digital converters
A hybrid D/A converter is provided including first and second D/A converters. The first D/A converter receives a digital signal having an input voltage and converts a first most-significant-bit of the digital signal to be converted to an analog signal. The first D/A converter includes first capacitors, which are charged by the input voltage and reference voltages during a sampling phase of the digital signal. Charges of the first capacitors are shared during successive approximations of first bits of the digital input signal received by the hybrid D/A converter. The second D/A converter converts a first least-significant-bit of the digital input signal. The second D/A converter includes second capacitors, which are charged based on a common mode voltage during the sampling phase. The second D/A converter performs charge redistribution by connecting the second capacitors to receive the reference voltages during successive approximations of second bits of the digital signal. |
| US09654130B2 |
Analog-to-digital converters for successive approximation incorporating delta sigma analog-to-digital converters and hybrid digital-to-analog with charge-sharing and charge redistribution
An A/D converter including a sample and hold circuit, first and second A/D converters and a combination circuit. The sample and hold circuit samples an analog input signal to generate bits. The first A/D converter generate a first digital signal based on the analog input signal and includes charge-sharing and charge-redistribution D/A converters that convert respectively a most-significant-bit and a first least significant bit. The first digital signal is generated based on outputs of the charge-sharing and charge redistribution D/A converters. The second A/D converter generates a second digital signal based on an output of the first A/D converter and includes a delta sigma D/A converter, which converts a second least significant bit. The second digital signal is generated based on an output of the delta sigma D/A converter. The second A/D converter is a fine conversion A/D converter relative to the first A/D converter. |
| US09654128B2 |
Multi-mode sampling/quantization converters
Provided are, among other things, systems, methods and techniques for converting a continuous-time, continuously variable signal into a sampled and quantized signal. According to one implementation, an apparatus includes multiple processing branches, each including: a bandpass noise-shaping circuit, a sampling/quantization circuit, and a digital bandpass filter. A combining circuit then combines signals at the processing branch outputs into a final output signal. The bandpass noise-shaping circuits include adjustable circuit components for changing their quantization-noise frequency-response minimum, and the digital bandpass filters include adjustable parameters for changing their frequency passbands. |
| US09654127B1 |
Method for adaptively regulating coding mode and digital correction circuit thereof
A method for adaptively regulating a coding mode and a digital correction circuit thereof are provided. The method is for a successive-approximation-register analog-to-digital converter (SAR ADC). In the method, whether to regulate a binary weight corresponding to each of digital bits is determined according to the number of completed comparison cycles to provide a first coding sequence. The first coding sequence is directly compensated according to uncompleted comparison cycles to provide a correct digital output code. |
| US09654124B1 |
Coherent signal source
An apparatus, a signal source, and a method for operating the same are disclosed. The apparatus includes a first signal source, a port, controller, signal synthesizer, and a first timestamp register. The port is adapted to receive a first clock signal that includes a sequence of pulses at a constant clock frequency. The signal synthesizer generates an output signal in response to inputs from the controller, the output signal having a first frequency. The first timestamp register counts pulses from the first clock signal. The controller is adapted to receive a command to change the output signal frequency from the first frequency to a second frequency, the controller causing the signal synthesizer to change the output signal frequency to the second frequency and to generate a frequency change timestamp from the timestamp register indicating a time at which the output signal changed from the first frequency to the second frequency. |
| US09654120B2 |
System and method of determining an oscillator gain
A method includes generating a first signal based on a difference between a first frequency of a first voltage controlled oscillator (VCO) and a second frequency of a second VCO. The method further includes determining a gain of the first VCO at least partially based on the first signal. |
| US09654114B2 |
Transmission circuit, integrated circuit, and parallel-to-serial conversion method
A transmission circuit includes: a shift register configured to shift, in synchronization with a first clock signal, input parallel data within a plurality of flip-flop circuits; a control circuit configured to output a second clock signal of a phase in accordance with a phase of the first clock signal; a selector configured to select any one of the input parallel data and pieces of output parallel data of the plurality of flip-flop circuits; and a conversion circuit configured to convert, in synchronization with the second clock signal, the parallel data selected by the selector into pieces of serial data, in which the control circuit outputs a selection signal to the selector, in accordance with a deviation amount of the detected phase of the first clock signal. |
| US09654113B2 |
Control device for clock generation circuit, control method for clock generation circuit, and clock generation circuit
A control device for a clock generation circuit that generates a clock signal based on a reference signal from an outside, the control device includes: a storage device that stores frequency correction information for the clock signal according to a temperature condition of the clock generation circuit; and a processor that controls a frequency of the clock signal generated by the clock generation circuit under a second temperature condition, based on first and second frequency correction information according to a first temperature condition at first and second time points in the storage device. |
| US09654112B2 |
Signal inverting device, power transmission device, and negative-voltage generating circuit
A signal inverting device generates an inverted signal of an input signal. The device includes a normally-on transistor, a negative-voltage generating unit that generates a negative voltage, and an output terminal. A first terminal of the normally-on transistor is connected to a current source. The output terminal is connected between the first terminal of the normally-on transistor and the current source. The normally-on transistor is turned on/off, by an input of a drive signal to a conduction control terminal of the normally-on transistor. The drive signal is a signal obtained by a synthesis of the input signal and the negative voltage. The inverted signal is output from the output terminal in accordance with the on/off operation of the normally-on transistor. The negative-voltage generating unit generates the negative voltage by rectifying a high-frequency power. |
| US09654109B2 |
Hardened programmable devices
Hardened programmable logic devices are provided with programmable circuitry. The programmable circuitry may be hardwired to implement a custom logic circuit. Generic fabrication masks may be used to form the programmable circuitry and may be used in manufacturing a product family of hardened programmable logic devices, each of which may implement a different custom logic circuit. Custom fabrication masks may be used to hardwire the programmable circuitry to implement a specific custom logic circuit. The programmable circuitry may be hardwired in such a way that signal timing characteristics of a hardened programmable logic device that implements a custom logic circuit may match the signal timing characteristics of a programmable logic device that implements the same custom logic circuit using configuration data. |
| US09654108B2 |
Apparatus and method having reduced flicker noise
One embodiment described is an apparatus that includes an active device structured in a semiconductor body. The semiconductor body may include a gate terminal to receive a switched bias signal, and a bulk terminal to receive a forward body-bias signal. A first circuit portion may be coupled to the gate terminal to provide the switched bias signal, and a second circuit portion may be coupled to the bulk terminal to provide the forward body-bias signal. |
| US09654107B2 |
Programmable LSI
An object is to achieve both suppression of operation delay and reduction in power consumption of a programmable LSI. A compiler generates, from source code, configuration data needed in a programmable LSI and a time schedule that shows a timing of using the data in the programmable LSI (a timing at which the data is held in a configuration memory) and a timing of storing the data in the programmable LSI before the data is used. Supply of new configuration data to the programmable LSI from the outside (storage of new configuration data) and data rewrite in the configuration memory in the programmable LSI (circuit reconfiguration) are performed independently and concurrently on the basis of the time schedule. |
| US09654105B2 |
On-die termination enable signal generator, semiconductor apparatus, and semiconductor system
A semiconductor apparatus may include an on-die termination (ODT) enable signal generator configured to enable an ODT enable signal in response to a data strobe signal, or enable the ODT enable signal in response to a command latch enable signal and an address latch enable signal. The semiconductor apparatus may include an ODT circuit configured to perform an ODT operation in response to the ODT enable signal. |
| US09654102B2 |
Hybrid direct-current circuit breaker
A circuit breaking system includes a first branch including at least one solid-state snubber; a second branch coupled in parallel to the first branch and including a superconductor and a cryogenic contactor coupled in series; and a controller operatively coupled to the at least one solid-state snubber and the cryogenic contactor and programmed to, when a fault occurs in the load circuit, activate the at least one solid-state snubber for migrating flow of the electrical current from the second branch to the first branch, and, when the fault is cleared in the load circuit, activate the cryogenic contactor for migrating the flow of the electrical current from the first branch to the second branch. |
| US09654098B2 |
Signal reception circuit and isolated signal transmission device
A signal reception circuit according to an aspect of the present disclosure includes: an input terminal; an input reference terminal; an output terminal; an output reference terminal; a normally-on type transistor that includes a first terminal connected to the output terminal, a second terminal connected to the output reference terminal, and a control terminal; a first detector circuit that detects an input signal applied between the input terminal and the input reference terminal, to apply an output signal between the output terminal and the output reference terminal; and a second detector circuit that detects the input signal, to apply a negative voltage pulse to the control terminal of the transistor with the output reference terminal as a reference. |
| US09654093B2 |
Electronic device having a delay locked loop, and memory device having the same
An electronic device includes a first duty cycle correction circuit, a delay line, a second duty cycle correction circuit, and a delay control circuit. The first duty cycle correction circuit is configured to detect a duty cycle error of a clock signal by performing time-to-digital conversion on the clock signal, and to generate a corrected clock signal by adjusting a duty cycle of the clock signal based on the duty cycle error of the clock signal. The delay line is configured to generate a delayed corrected clock signal by delaying the corrected clock signal based on a delay control code The second duty cycle correction circuit is configured to detect a duty cycle error of a first output clock signal received through a feedback loop, and to generate a second output clock signal by adjusting duty cycle of the delayed corrected clock signal based on the duty cycle error of the first output clock signal. The delay control circuit is configured to generate the delay control code based on the clock signal and the first output clock signal. |
| US09654092B1 |
High speed gain stage with analog input and determinable digital output using regenerative feedback
A high speed gain stage including regenerative feedback that forces one output high and one output low providing a two-state output. A differential pair of input transistors of a first conductivity type have respective current terminals coupled between a source node and first and second output nodes and have respective control terminals that receive the analog input voltages. A current source provides source current to the source node. The gain stage includes a differential pair of bias transistors of a second conductivity type having respective current terminals coupled between the first and second output nodes and a reference voltage and having respective control terminals coupled to a bias node. A pair of current-driven transistors of the second conductivity type are cross-coupled at the outputs and to a common node to provide the regenerative feedback. Another transistor is coupled between the common node and the reference voltage to increase switching speed. |
| US09654087B1 |
Level shifter circuit
Techniques are disclosed for a level shifter configured to adjust current flow in response to measured current fluctuations due to common mode noise in the level shifter. For example, the level shifter includes a low-side control circuit configured to adjust a first current flowing into a first low-side terminal of an active high voltage level shifter device in response to a difference between the first low-side current and a second low-side current flowing into a second low-side terminal of an inactive high voltage level shifter device. The level shifter further includes a high-side receiver circuit configured to detect a difference between a first high-side current flowing into a first high-side terminal of the active high voltage level shifter device and a second high-side current flowing into a second high-side terminal of the inactive high voltage level shifter device. |
| US09654079B2 |
Composite electronic component and a board for mounting the same
A composite electronic component may include: a composite body including a capacitor formed of a ceramic body in which a plurality of dielectric layers and first and second internal electrodes are laminated, and an inductor formed of a magnetic body including a coil; an input terminal disposed on a first end surface of the composite body; output terminals including a first output terminal disposed on a second end surface of the composite body and a second output terminal disposed on the second end surface of the composite body; and a ground terminal disposed on one or more of upper and lower surfaces and the first end surface of the capacitor of the composite body. The capacitor is adjacent to the inductor. |
| US09654078B1 |
Technique for designing acoustic microwave filters using LCR-based resonator models
A method of designing an acoustic microwave filter in accordance with frequency response requirements comprises generating a modeled filter circuit design having a plurality of circuit elements comprising an acoustic resonant element defined by an electrical circuit model that comprises a parallel static branch, a parallel motional branch, and one or both of a parallel Bragg Band branch that models an upper Bragg Band discontinuity and a parallel bulk mode function that models an acoustic bulk mode loss. The method further comprises optimizing the modeled filter circuit design to generate an optimized filter circuit design, comparing a frequency response of the optimized filter circuit design to the frequency response requirements, and constructing the acoustic microwave filter from the optimized filter circuit design based on the comparison. |
| US09654076B2 |
Metadata for ducking control
An audio encoding device and an audio decoding device are described herein. The audio encoding device may examine a set of audio channels/channel groups representing a piece of sound program content and produce a set of ducking values to associate with one of the channels/channel groups. During playback of the piece of sound program content, the ducking values may be applied to all other channels/channel groups. Application of these ducking values may cause (1) the reduction in dynamic range of ducked channels/channel groups and/or (2) movement of channels/channel groups in the sound field. This ducking may improve intelligibility of audio in the non-ducked channel/channel group. For instance, a narration channel/channel group may be more clearly heard by listeners through the use of selective ducking of other channels/channel groups during playback. |
| US09654075B2 |
Power amplification module
Provided is a power amplification module that includes: a first transistor, a first signal being inputted to a base thereof; a second transistor, the first signal being inputted to a base thereof and a collector thereof being connected to a collector of the first transistor; a first resistor, a first bias current being supplied to one end thereof and another end thereof being connected to the base of the first transistor; a second resistor, one end thereof being connected to the one end of the first resistor and another end thereof being connected to the base of the second transistor; and a third resistor, a second bias current being supplied to one end thereof and another end thereof being connected to the base of the second transistor. |
| US09654074B2 |
Variable gain amplifier circuit, controller of main amplifier and associated control method
A variable gain amplifier circuit comprises a main amplifier, a current sensing circuit, a variable loading and a control amplifier. The main amplifier is configured for amplifying an input signal to generate an output signal. The current sensing circuit is coupled to the main amplifier, and is configured for generating a sensed current related to a current flowing through the main amplifier. The variable loading is coupled to the current mirror via a node, wherein the sensed current flows through the node and the variable loading. The control amplifier is coupled to the node and the main amplifier, and is configured for receiving a control voltage and a voltage of the node to generate an adjustment signal to control a gain of the main amplifier, wherein a resistance of the variable loading has a nonlinear relationship with the control voltage. |
| US09654073B2 |
Group volume control
Embodiments are provided for controlling playback volumes of a group of one or more playback zones in a network media system via a user interface provided on a touch screen display. For instance, touch inputs may be provided to the user interface via the touch screen to move a volume indicator along a graphical representation of a volume scale on the user interface to adjust a particular playback volume level of a playback zone or the group of the one or more playback zones. Further, touch inputs such as a dwell touch input or a swipe touch input may be configured to cause the particular playback volume level to be applied to other playback zones in the network media system, such that each playback zone the playback volume level is applied to has a respective playback volume level matching, or substantially matching the particular playback volume level. |
| US09654071B2 |
Preamplifier circuit for a microelectromechanical capacitive acoustic transducer
Described herein is a preamplifier circuit for a capacitive acoustic transducer provided with a MEMS detection structure that generates a capacitive variation as a function of an acoustic signal to be detected, starting from a capacitance at rest; the preamplifier circuit is provided with an amplification stage that generates a differential output signal correlated to the capacitive variation. In particular, the amplification stage is an input stage of the preamplifier circuit and has a fully differential amplifier having a first differential input (INP) directly connected to the MEMS detection structure and a second differential input (INN) connected to a reference capacitive element, which has a value of capacitance equal to the capacitance at rest of the MEMS detection structure and fixed with respect to the acoustic signal to be detected; the fully differential amplifier amplifies the capacitive variation and generates the differential output signal. |
| US09654070B2 |
Method for stabilizing the gain of a discrete-state automatic gain control circuit
An automatic gain controller comprises an amplifier including a variable gain. A resonant low-pass filter includes an input coupled to an output of the amplifier. The resonant low-pass filter is a second order low-pass filter. The second order low-pass filter includes a Sallen-Key topology. The Sallen-Key topology comprises a quality factor between 1.4 and 1.6. A threshold detection circuit includes an input coupled to an output of the second order low-pass filter to compare an output signal of the second order low-pass filter to a threshold and an output of the threshold detection circuit coupled to control the variable gain of the amplifier. A state machine is coupled between the output of the threshold detection circuit and the amplifier. The state machine is configured to transition based on a current state of the state machine. The resonant low-pass filter exhibits overshoot to trigger a hysteresis of the threshold detection circuit. |
| US09654068B2 |
Quaternary/ternary modulation selecting circuit and associated method
A quaternary/ternary modulation selecting method of an audio amplifier includes: generating a ternary signal and a quaternary signal; generating a plurality of pulses with limited duty cycles; and selecting one of the quaternary signal, the ternary signal and the plurality of pulses for an output stage of the audio amplifier. |
| US09654065B2 |
Digital amplitude modulation device and digital amplitude modulation method
A digital amplitude modulation device includes power amplifiers, a compositor, a filter, a measurement unit, a protection unit, and a controller. The power amplifiers are arranged in parallel and amplify an input signal in accordance with ON control and stop output in accordance with OFF control. The filter suppresses an unnecessary component to generate an AM signal. The measurement unit measures a measurement value between the filter and a signal output terminal and output the AM signal generated by the filter. The protection unit includes a calculator and a first processing unit. The calculator is formed from an analog circuit and calculates an evaluation value based on the measurement value. The first processing unit is formed from an analog circuit and generates a first control signal by referring to the evaluation value. Upon receiving the first control signal, the controller OFF-controls the power amplifiers. |
| US09654058B2 |
Apparatus and method for digital pre-distortion in wireless communication system
Provided is a Digital Pre-Distortion (DPD) apparatus and method for processing a signal that is input to a power amplifier in a wireless communication system. The DPD apparatus includes a DPD unit configured to pre-distort an input signal that is input to the power amplifier, using DPD information; and a signal processor configured to capture signals for estimation of the DPD information from each of an input terminal and an output terminal of the power amplifier, detect peak signals of the captured signals, separate the detected peak signals into a plurality of intervals depending on a power level, separately store the detected peak signals, estimate the DPD information using the peak signals stored for each interval, and provide the estimated DPD information to the DPD unit. |
| US09654053B2 |
Solar module support structure
Described herein are solar energy collection systems, devices, and methods for harvesting solar energy. In some embodiments, the devices, systems, and methods described herein comprise a bifacial photovoltaic module, a reflector, a rod and a support structure. |
| US09654052B2 |
Method for installing a solar structure in an area on the ground
A method for installing a solar structure includes the steps of: a) planting at least two anchoring feet in an area on the ground (S); b) arranging a pivot support having a pivot axis (X) on the free end that extends above the area of ground of each of the anchoring feet; c) aligning the pivot axes of the pivot supports with each other; d) attaching the pivot supports to the respective anchoring foot thereof; and e) positioning the solar structure on the pivot supports. |
| US09654051B2 |
Control circuit for controlling cooling fan of data center
A control circuit for controlling a cooling fan is defined in a data center. The control circuit includes a cooling fan, a controller, a switch unit, and a control unit. The controller is configured to generate a first pulse width modulation (PWM) signal for controlling the cooling fan to rotate at a first speed and the control unit is configured to generate a second PWM signal for controlling the cooling fan to rotate at a second speed. The switch unit is configured to output the first PWM signal to the cooling fan when the data center is in an active mode and configured to output the second PWM signal to the cooling fan when the data center is in a standby mode. |
| US09654047B2 |
Drive device
A drive device for controlling an electric motor, including a processor, and a non-transitory storage medium containing program instructions, execution of which by the process causes the drive device to provide functions of a customization unit and a core unit. The customization unit receives, from an external device, a command value designating an operating state of the electric motor, converts the command value using a predetermined reference value, and outputs the converted command value. The core unit receives the converted command value from the customization unit, recovers a physical quantity from the received converted command value, and controls the electric motor in accordance with the recovered physical quantity. |
| US09654040B2 |
Drive circuit of stepping motor, integrated circuit thereof, and electronic equipment including same, and method for controlling drive circuit of stepping motor
A drive circuit of a stepping motor includes a D/A converter, a current controller having a comparing unit, and an abnormality detecting unit. The DAC generates a target voltage indicating a target value for an excitation current determined based on a reference voltage indicating an upper limit value of the excitation current flowing into the stepping motor. The current controller controls the excitation current based on this target voltage. The comparing unit compares a voltage corresponding to the excitation current and the target voltage. The abnormality detecting unit detects an abnormality of the wire between the drive circuit and the stepping motor based on an output signal from the comparing unit and a control signal indicating a polarity of the excitation current. |
| US09654035B1 |
High-temperature brushless DC motor controller
A motor control system for deployment in high temperature environments includes a controller; a first half-bridge circuit that includes a first high-side switching element and a first low-side switching element; a second half-bridge circuit that includes a second high-side switching element and a second low-side switching element; and a third half-bridge circuit that includes a third high-side switching element and a third; low-side switching element. The motor controller is arranged to apply a pulse width modulation (PWM) scheme to switch the first half-bridge circuit, second half-bridge circuit, and third half-bridge circuit to power a motor. |
| US09654027B2 |
Semiconductor device and power converter using the same
A semiconductor device is provided that can prevent a current from being concentrated into a specific chip, and can reduce loss as well as noise. The semiconductor device according to the present invention includes: a switching element; a main diode that is connected in parallel to the switching element; and an auxiliary diode that is connected in parallel to the switching element and has a different structure from that of the main diode, wherein in a conductive state a current flowing through the auxiliary diode is smaller than that through the main diode, and in a transition period from the conductive state to a non-conductive state a current flowing through the auxiliary diode is larger than that through the main diode. |
| US09654025B2 |
Method for designing cascaded multi-level inverter with minimized large-scale voltage distortion
A method for designing cascaded multi-level inverters with minimization of large-scale voltage distortion, based on KKT (Karush-Kuhn-Tucker) conditions and with simplified computation of conduction angles, simplifies the computation process, and is conducive to on-line calculation. Meanwhile, its fundamental voltage is adaptive, minimization of total harmonic is realized for cascaded multi-level inverters at high-voltage, and voltage power quality at grid connected nodes is improved. |
| US09654024B2 |
AC-DC converter having soft-switched totem-pole output
An AC-DC converter has a totem-pole output circuit having first and second semiconductor switches, each having a channel coupled to a switching node and having a parasitic capacitance associated with the channel. An inductor has one terminal thereof connected to a switching node. First and second bypass devices are coupled to a second terminal of the inductor and operable during at least a portion of an input voltage to allow reverse current from an output of the converter to generate soft-switching of the first semiconductor switch. An asymmetrical shunt for measuring current in a first direction and bypassing current in a second direction opposite the first direction allows accurate measurement of reverse current. |
| US09654021B2 |
Multifunction power converter with option for integrated magnetics
Power converter modules and parallel conversion systems are presented in which the modules are provided in a rollable enclosure having AC and DC electrical connections, and an interior including a switching circuit with switching devices individually connected between a corresponding AC node and a corresponding DC node for operation as either a rectifier or an inverter and an internal filter circuit with inductors individually connected between a corresponding AC node of the switching circuit and a corresponding AC electrical connection, with a built-in blower or fan to cool the filter circuit during operation. |
| US09654017B2 |
Structural frame cooling manifold
A variable speed drive includes a converter connected to an AC power source, a DC link connected to the converter, and an inverter connected to the DC link. The inverter converts DC voltage into an output AC power having a variable voltage and frequency. The inverter includes at least one power electronics module and associated control circuitry; a heat sink in thermal communication with the power electronics module and in fluid communication with a manifold. The manifold includes a tubular member having at least one vertical member portion and at least one horizontal member portion in fluid communication. A plurality of ports conduct cooling fluid into and out of the manifold. A bracket attaches the manifold to a structural frame. Brackets are provided for attachment of power electronics modules to the manifold. |
| US09654016B2 |
Step-up or step-down converter comprising a bypass capacitor
A converter includes a converter inductor, a converter diode, and a converter switch, wherein the converter inductor, the converter diode and the converter switch operate together to receive an input voltage and generate a converted output voltage. The converter further includes a bypass circuit that is connected in parallel with the converter switch; the bypass circuit includes a bypass capacitor connected in series with a diode, wherein a forward direction of the diode is the same as a regular direction of current flow through the converter switch. The converter also includes a discharge circuit configured to discharge the bypass capacitor, wherein the discharge circuit includes an inductor. The inductor of the discharge circuit is magnetically coupled to the converter inductor. |
| US09654014B1 |
Adaptive leading edge blanking time generation for current-mode switch-mode power supplies
A current-mode switch-mode power supply controller includes a switch controller, a falling edge detector, and leading edge blanking (LEB) time logic. The switch controller is arranged to control regulation of an output signal via current-mode regulation by turning a primary switch on and off based on a current sense (CS) signal and an LEB signal, such that the switch controller is arranged to cause the primary switch to remain on while the LEB time signal is asserted. The falling edge detector is arranged to detect a falling edge in the CS signal. The LEB time logic is arranged to provide the LEB time signal such that the assertion of the LEB time signal begins when a gate signal is asserted, and such that the assertion of the LEB time signal ends when the falling edge detector detects the falling edge in the CS signal. |
| US09654012B2 |
Converter and method for controlling the same using an overcurrent protection switch
A converter may include a transformer, an overcurrent protection switch configured to be installed at a primary side of the transformer to prevent an overcurrent, a comparator configured to detect a voltage of the overcurrent protection switch to convert the detected voltage into an output current sensing value and compare the output current sensing value with a reference value, and a protection controller configured to normally operate or forcibly turn off the overcurrent protection switch depending on a comparison result of the comparator. |
| US09654011B2 |
Control circuit and method of a power converter
A feedback signal stabilized by a capacitor and related to an output voltage of a power converter is used to acquire the output power information of the power converter, and a control circuit uses a second clock not related to the switching frequency of the power converter to count a duration time of the feedback signal being higher than a threshold. When the duration time is higher than a preset time, an abnormal output power of the power converter is distinguished and the power converter will be turned off. The feedback signal will not vary severely even if the output terminal of the power converter is interfered, and the counted duration time will not be influenced when the switching frequency is changing caused by a load changing. |
| US09654009B2 |
High efficiency DC-to-DC converter
A power converter is described herein. The power converter may be configured to enable a high-side switch when a resonating voltage at a switching net coupled between the high-side switch and a low-side switch reaches a maximum voltage while the power converter operates in a discontinuous current mode. The power converter may sample the resonating voltage at the switching net at a time when the high-side switch is enabled and compare the sampled voltage with a previously-sampled voltage of the switching net. A frequency of an oscillating signal that drives the activation of the high-side switch is periodically adjusted based on the comparison, which causes the high-side switch to be enabled at different times with respect to the resonating voltage. The frequency of the oscillating signal is continuously adjusted such that the high-side switch is enabled at time(s) where the resonating voltage reaches (or is near) its maximum voltage. |
| US09654008B2 |
Regulator circuit and method of operating regulator circuit
A regulator circuit includes a regulator output node, at least (N+1) regulator control circuits, and N drivers. N is an integer greater than 1. Each one of the N drivers includes a multiplexer, a driver stage, and a pre-driver stage. The multiplexer includes an input port and an output port, where the input port of the multiplexer is coupled with output nodes of the at least (N+1) regulator control circuits. The driver stage is coupled with the regulator output node. The pre-driver stage is configured to control the driver stage based on a signal on the output port of the multiplexer. |
| US09654004B1 |
3D integrated DC-DC power converters
Techniques for integrating DC-DC power converters with other on-chip circuitry are provided. In one aspect, an integrated DC-DC power converter includes: a GaN transistor chip having at least one GaN switch formed thereon; an interposer chip, bonded to the GaN transistor chip, having at least one power driver transistor formed thereon; TSVs present in the interposer chip adjacent to the power driver transistor and which connect the power driver transistor to the GaN switch; and an on-chip magnetic inductor formed either on the GaN transistor chip or on the interposer chip. A method of forming a fully integrated DC-DC power converter is also provided. |
| US09654001B2 |
Semiconductor device
A semiconductor device includes a semiconductor layer laminate disposed on a semiconductor substrate, a first and a second low-side transistors, and a first and a second high-side transistors. Each of the transistors is disposed on the semiconductor layer laminate, and includes a gate electrode, a source electrode, and a drain electrode. The second low-side transistor is disposed between the first low-side transistor and the first high-side transistor, and the first high-side transistor is disposed between the second low-side transistor and the second high-side transistor. The source electrodes of the first and the second low-side transistors are combined into one source electrode, the drain electrodes of the first and the second high-side transistors are combined into one drain electrode, and the drain electrode of the second low-side transistor and the source electrode of the first high-side transistor are combined into one first electrode. |
| US09653996B2 |
Adaptive off time control scheme for semi-resonant and hybrid converters
In one implementation, a voltage converter includes a high side power switch, and first and second low side power switches. The voltage converter also includes a driver stage for driving the high side power switch and the first and second low side power switches, and an adaptive OFF-time control circuit coupled to the driver stage. The adaptive OFF-time control circuit is configured to sense a current through one of the first and second low side switches, and to determine an adaptive off time for the high side power switch based on the sensed current. |
| US09653995B2 |
Control device and method for regulating a multiphase DC-DC converter
The invention relates to a control device for regulating a multiphase dc-dc converter having at least one first converter branch and one second converter branch connected in parallel to the first converter branch. The control device comprises a switching signal generation device that is designed to determine measurement values for the current in the converter branches, to compare, for a first of the converter branches, the determined measurement value of the current in the first converter branch to a first upper threshold current value and a first lower threshold current value and, on the basis of the comparisons, to generate a first control signal for switching devices of the first converter branch, and for a second of the converter branches, to compare the determined measurement value of the current in the second converter branch to a second upper threshold current value and a second lower threshold current value and, on the basis of the comparisons, to generate a second control signal for switching devices of the second converter branch. The control device further comprises a threshold value generator, which is coupled to the switching signal generation device and is designed to generate upper and lower threshold current values for the switching signal generation device, to determine an actual current phase offset of the control signals for the switching devices in the first and second converter branches, and on the basis of the determined phase offset, to temporarily modify the second upper current threshold value and/or the second lower current threshold value. |
| US09653994B2 |
Power supply circuit and apparatus including the circuit
A power supply device supplying power to a device via a power line is provided, where the power supply device includes a first voltage generation unit configured to generate and supply a first direct voltage to the power line, a second voltage generation unit configured to generate and supply a second direct voltage lower than the first direct voltage to the power line, a measurement unit configured to measure a voltage of the power line, a control unit configured to control supply of the first direct voltage with the first voltage generation unit after starting supply of the second direct voltage with the second voltage generation unit, and a determination unit configured to determine a state of the power supply device based on the measured voltage and a first threshold value after starting the supply of the second direct voltage. |
| US09653991B2 |
Power converter and driving method for the same
A power converter may include an inductor, a switch turned on or turned off according to a control signal to control the flow of a current flowing through the inductor, and a control unit for outputting the control signal to turn on or turn off the switch by integrating a current flowing through the switch to compare the integrated current with the size of a preset reference voltage. The power converter and a driving method for the same may reduce errors of current control and have a simple structure. |
| US09653986B2 |
Multi-level step-up converter topologies, control and soft start systems and methods
A multi-level, step-up converter circuit includes an inductor including one terminal in communication with an input voltage supply. N transistor pairs are connected in series, where N is an integer greater than one. First and second transistors of a first pair of the N transistor pairs are connected together at a node. The node is in communication with another terminal of the inductor. Third and fourth transistors of a second pair of the N transistor pairs are connected to the first and second transistors, respectively. (N−1) capacitors have terminals connected between the N transistor pairs, respectively. An output capacitor has a terminal in communication with at least one transistor of the N transistor pair. |
| US09653985B2 |
Resonant converter and controlling method thereof
A resonant converter and its controlling method are provided. The resonant converter includes a bridge switching circuit receiving a DC input voltage through its power terminal, a resonant and transforming circuit, a rectifying and filtering circuit, and an over-current protecting circuit. The resonant and transforming circuit has at least one resonant capacitor charged/discharged in response to the switching of the bridge switching circuit. The rectifying and filtering circuit rectifies and filters outputs of the resonant and transforming circuit, and generates a driving voltage accordingly. The over-current protecting circuit is coupled to the power terminal and crosses over the resonant capacitor to form a clamp path. The over-current protecting circuit detects a current flowing through the resonant and transforming circuit or a load and determines whether to conduct/cut off the clamp path according to the detection result to limit a cross voltage of the resonant capacitor within a first voltage range. |
| US09653981B2 |
Linear actuator
A linear actuator with a high holding force providing good irreversibility, has a high efficiency, low friction screw mechanism and a stepper motor with high magnetic detent torque but a low output torque ripple. The phase torque is modified to minimize the effect of the detent torque on the output. torque. Preferably, the motor has asymmetric phases to compensate for the detent torque. |
| US09653978B2 |
Permanent magnet, and electric machine comprising same, and a method for producing the electric machine
Permanent magnet (10), containing at least one metal component (13) from the group of the rare earth metals, comprising a first coating film (20), which forms a cathodic protection against corrosion for the permanent magnet (10), the first coating film (20) containing a metal (23) which is more electronegative in the electrochemical series than the metal component (13) of the permanent magnet (10), wherein a second coating film (30), which is embodied in an electrically insulating fashion, is applied on the first coating film (20). |
| US09653973B1 |
Thermally enhanced hub motor
Apparatuses and methods relating to hub motors having enhanced thermal characteristics may include a hub motor having a stator comprising steel and a central axle (e.g., a mandrel and shaft) comprising a material with a substantially higher thermal conductivity than the stator (e.g., aluminum). Heat may be transferred from the stator through the axle of the motor to an outside heat sink. Manufacturing of thermally enhanced hub motors may include extrusion and/or cryogenic fitting methods relating to the central mandrel and shaft. |
| US09653964B2 |
Linear actuator
[Problem] To reduce the size of a linear actuator motor without increasing the operating noise thereof, and to thereby achieve a quieter, more compact linear actuator. [Solution] A linear actuator including: a shaft that is rotated in the forward and reverse directions by a motor via a double start worm and a worm wheel; a screw nut that is screwed and mounted to the shaft; and a piston tube that is fixed to the screw nut and that advances or retreats in accordance with the rotation of the shaft. The motor includes: a four-pole magnet; an armature formed by lap winding an armature coil; a commutator; brushes that are vertically arranged at positions offset by approximately 90°; and an equalizer for connecting coils in the armature coil that are to undergo potential equalization. |
| US09653961B2 |
Stator sleeve with integrated cooling for hybrid/electric drive motor
A hybrid system includes an electric motor/generator or eMachine with a stator received in a cooling sleeve. The stator is pressed into the cooling sleeve to form a press-fit connection. The press fit connection has sufficient strength to carry the complete torque generated by the eMachine, so the stator will never move relative to the sleeve through the life of the hybrid system. |
| US09653952B2 |
Half permanent magnet motor
A motor includes a rotor and a stator. The rotor includes a plurality of magnets, which function as first magnetic poles, and salient poles, which function as second magnetic poles. A ratio X1:X2 of a quantity X1 of magnetic pole portions of the rotor, which is the sum of the quantity of the magnets and the quantity of the salient poles, and the quantity X2 of slots is 2n:3n (n being a natural number). The sum of a magnetic pole occupying angle θ1 of the magnet and a magnetic pole occupying angle θ2 of the salient pole is 360°. The magnetic pole occupying angle θ1 is set in a range of 180°<θ1≦230°. |
| US09653950B2 |
Wireless power transmitting device and method for controlling to transmit wireless power signal in wireless power transmitting device
There is provided a wireless power transmitting device including a transmission coil configured to transmit a wireless power signal to a wireless power receiving device; a driving driver configured to generate a wireless power driving signal which is a driving signal for the wireless power signal; an alternating current sensor configured to detect an alternating current signal of the transmission coil which is generated by a wireless power receiving signal including wireless power receiving information of a wireless power receiving device; an alternating voltage sensor configured to detect an alternating voltage signal of the transmission coil, the alternating current signal being generated by the wireless power receiving signal from the wireless power receiving device; a signal processing unit configured to process the alternating current signal and the alternating voltage signal from the alternating current sensor and the alternating voltage sensor; and a wireless power transmitting controller that, when the alternating current signal and the alternating voltage signal of the transmission coil are detected and signal processing is normally performed on at least one of the alternating current signal and the alternating voltage signal, obtains the wireless power receiving information through the signal on which the signal processing is performed and controls the driving driver on the basis of the wireless power receiving information. Further, there is provided a method for controlling to transmit a wireless power signal in the wireless power transmitting device. |
| US09653946B2 |
Power distribution system
A power distribution system includes at least one server and a power distribution unit coupled to the at least one server. The power distribution unit includes a power distribution controller and a power input unit, a battery and a power switcher coupled to the power distribution controller. The power distribution controller detects a voltage of an alternating current (AC) received from power source by the power input unit. If the voltage is greater than a first threshold and smaller than a second threshold, the power distribution controller switches the power switcher to be coupled to the power input unit, and provides the alternating current (AC) to the at least one server. Conversely, the power distribution controller switches the power switcher to be coupled to the battery, and provides a direct current (DC) to the at least one server. Accordingly, power consumption and waste during power supply may be effectively reduced. |
| US09653938B2 |
Method and apparatus for improving electronics devices wireless charging using inertial sensors
In accordance with an example embodiment of the present invention, a method comprises: monitoring a motion of a handset from a wireless charger to detect a presence of the handset on the wireless charger (312); initiating a wireless charging when the presence of the handset is detected on the wireless charger and transmitting a charging notification to an end user (318); sending a battery full message for notifying the end user when the wireless charging is complete and terminating the wireless charging (316); setting the handset to a standby mode and initializing inertial sensor(s) to provide an interrupt signal (330); entering a maintenance charging mode of a battery of the handset when it is below a recharging threshold without notifying the end user (336); and continuing the maintenance charging mode of the wireless charging device until the battery is full (342) or the wireless charging device is removed from the wireless charger transmitter (340). |
| US09653937B2 |
Power supplying apparatus, power receiving apparatus, electrical vehicle, charging system, and charging method
It is an object of the present invention to provide a power supplying apparatus, a power receiving apparatus, an electrical vehicle, a charging system, and a charging method, the power feeding apparatus improving reliability by suppressing any decrease in charging efficiency and making charging control communication more resistant to high-frequency noise of a switching element. A power supplying apparatus for feeding power to an external apparatus, wherein the power supplying apparatus is characterized in having a power conversion unit, a power supplying unit, a control unit, and a communication unit. The power conversion unit includes a power conversion switching element capable of changing the a switching waveform of the switching element. The power supplying unit supplies power to the external apparatus, the power being generated in the power conversion unit. The communication unit communicates with the external apparatus. The control unit conducts a control so as to adjust the switching waveform of the switching element in the power conversion unit during a period in which the communication unit communicates with the external apparatus. |
| US09653930B2 |
Emergency system for power failures
An emergency system for power failures includes a single-cell or multiple-cell rechargeable battery selected from the group consisting of NiMH, NiCd, NiZn, Ag2O/Zn or lithium-ion, and a charging electronics system that charges the battery, wherein the charging electronics system provides a charging voltage at which the battery does not overcharge at a temperature of up to 80° C., and wherein the charging electronics system supplies a charging voltage at which the battery is transferred into a charging state and/or is kept in a charging state, in which the battery is charged to 5% to 30%. |
| US09653926B2 |
Physical property sensor with active electronic circuit and wireless power and data transmission
Wireless sensors configured to sense, record and transmit data are provided herein. In one aspect, the wireless sensor has a power harvesting unit; a transducing A-to-D converter unit, a microcontroller unit, and a transmitting coil. The power harvesting unit is configured to receive an external energizing magnetic field generated by an external interrogator and store the energy generated thereby. The transducing A-to-D converter unit has a passive electrical transducer configured to respond to variations in a physical property and a converter configured to measure a characteristic value of the passive electrical transducer and provide a digital signal that is indicative of the measured characteristic value. The microcontroller unit is electrically coupled to the power harvesting unit and the transducing A-to-D converter unit and is configured to receive the digital signal from the transducing A-to-D converter unit. The transmitting coil is configured to receive the digital signal and to transmit the digital signal to the external interrogator. Upon receiving a start signal, the transducing A-to-D converter unit charges a current through the passive electrical transducer until a reference voltage is reached and, upon reaching the reference voltage, the microcontroller unit receives the digital signal. |
| US09653924B2 |
Battery system
A battery system includes a power supply device which supplies power, a battery device in which a plurality of substantially identical battery units are connected in parallel, and a control device including a storage unit which stores information about a reference power value corresponding to predetermined conversion efficiency of the power conversion unit, an acquisition unit which acquires information about a supply power amount of the power supplied by the power supply device, and a selection unit which determines the number of battery units capable of distributing the supply power amount at a power amount greater than or equal to the reference power value and selects the battery units to which the power is supplied from the power supply device among the plurality of battery units, wherein the selected battery units are equal in number to the determined number. |
| US09653923B2 |
Resonant power management architectures
Disclosed are various embodiments of resonant power management of a mobile device. In one embodiment, a mobile device including a power management unit (PMU) including a resonant inverter, a plurality of AC/DC converters, and an AC bus configured to route the AC power from the resonant inverter to the plurality of AC/DC converters. The resonant inverter converts DC power from a power source to AC power that is converted to DC power by the AC/DC converters and supplied to loads of the mobile device. In another embodiment, a method for power management of a mobile device includes monitoring, by a PMU of the mobile device, an operating mode of the mobile device and adjusting an output frequency of a resonant inverter of an AC power distribution network of the PMU in response to a change in the operating mode of the mobile device. |
| US09653922B2 |
Power supply apparatus, control method of power supply apparatus, and power supply system
Provided is a plurality of power supply apparatuses connected in parallel with a grid that are capable of obtaining the same measured values of the same voltage.The power supply apparatus according to the present invention is connected in parallel with the grid and includes a voltage sensor 108 configured to obtain a first measured voltage value by measuring a voltage of the grid, a communication interface 114 configured to communicate with another power supply apparatus connected in parallel with the grid, and a controller 118 configured to obtain, via the communication interface 114, a second measured voltage value obtained by the another power supply apparatus by measuring the voltage of the grid and carrying out an adjustment such that the first measured voltage value and the second measured voltage value of the same voltage of the grid approximate to the same value. |
| US09653918B2 |
Autonomous thermal event control and monitoring system for a network vault
An autonomous thermal event control and monitoring system includes a processor component having an enclosure, a processor within the enclosure, a routine, a number of inputs from the processor, and a plurality of inputs to and a plurality of outputs from the processor for each of a plurality of feeders. The system also includes a human machine interface communicating with the processor. The inputs include for each of the feeders, a first input for a thermal sensor and a second input for a status of a network protector, a plurality of third inputs for statuses of a medium voltage interrupter, and a fourth input for a sudden pressure sensor of a network transformer. The outputs include for each of the feeders, a first output for a command to the network protector, and a plurality of second outputs for commands to the medium voltage interrupter. |
| US09653917B2 |
Energy management system
The present invention relates to an energy management system comprising an energy storage, a control system and a power converter supplying power to a load. The energy storage is arranged in individual energy units and the power converter is provided with a switching system for controlling the voltage over the load. The switching system comprises multiple parallel-connected power switches and at least one of the power switches is connected to each energy unit. The control system comprises individual control units, each being configured to monitor the status of a dedicated energy unit and produce an individual enable signal indicative of the status. Each power switch is configured to be controlled by the individual enable signal and a first control signal, wherein the control system is configured to connect multiple energy units in parallel to the load. |
| US09653915B2 |
Method and apparatus for detecting electro static discharge in electronic device
A system detects Electro Static Discharge (ESD) of an electronic device by sensing a ground voltage of an electronic device, comparing the sensed ground voltage with a predetermined reference voltage and if the sensed ground voltage exceeds the reference voltage, performs at least one predetermined operation of the electronic device. |
| US09653910B2 |
Power structure diagnostic method and apparatus for improved motor drive diagnostic coverage
Motor drive diagnostic and control methods and apparatus are provided in which rectifier and inverter switching devices are individually monitored for malfunctions, and detected malfunctions initiate implementation of a safety function to signal a drive controller to shut down non-safety-related processing, to discontinue command pulse signaling to the switching devices, and to disable optical transmitters between the drive controller and the rectifier and inverter switches, and an input contactor or other switching circuit is opened to disconnect input power from the motor drive after implementation of the safety function. |
| US09653909B1 |
Fault handling for motor controllers
In one aspect, a method is described. The method may include operating a plurality of circuit elements, and operating a plurality of fault-mitigation circuits. Each circuit element may include an energy storage element, each individual fault-mitigation circuit may be electrically coupled in parallel to a respective circuit element, and each individual fault-mitigation circuit may include a switch. The method may include detecting an electrical fault in one of the circuit elements and cycling the switch of the fault-mitigation circuit coupled in parallel to the faulty circuit element between an open position and a closed position until the storage element of the faulty circuit element is discharged of energy, at which point the switch remains closed. |
| US09653906B2 |
Overcurrent detection circuit, inverter, compressor, and air-conditioning machine, and adjusting method for adjusting overcurrent detection circuit
A current detection device for detecting an electric current flowing through an inverter, an overcurrent level generation device for generating an abnormality judgment reference value, an overcurrent detection device for generating an interruption signal to the inverter on the basis of an output of the current detection device and the abnormality judgment reference value, and an adjusting apparatus for correcting the abnormality judgment reference value of the overcurrent level generation device on the basis of the output at a time when a constant electric current is applied to the current detection device are provided. The overcurrent level generating device is provided with one or a plurality of resistance value adjusting sections, and generates the abnormality judgment reference value in correspondence to a resistance value of the resistance value adjusting section. The adjusting apparatus performs a zapping operation by means of applying a reverse-bias to a zener diode, and corrects the abnormality judgment reference value. |
| US09653905B2 |
Power supply and measuring device for an intelligent electronic device
The present invention relates to a power supply and measuring device for an electronic device (e.g. an IED), which is configured to provide supervision, control, protection, communication and/or monitoring functionalities for LV or MV circuits or apparatuses. The power supply device comprises a current transformer, which is operatively associated to a main power line. An input section of the power supply device comprises a burden regulating stage that is configured to regulate the equivalent electric load at the secondary winding of said current transformer. An output section of the power supply device provides a supply voltage suitable to feed said electronic device. |
| US09653904B2 |
Arc flash protection system with self-test
An method for automatically testing an arc flash detection system by periodically or continually transmitting electro-optical (EO) radiation through one or more transmission cables electro-optically coupled to respective EO radiation collectors. A test EO signal may pass through the EO radiation collector to be received by an EO sensor. An attenuation of the EO signal may be determined by comparing the intensity of the transmitted EO signal to an intensity of the received EO signal. A self-test failure may be detected if the attenuation exceeds a threshold. EO signals may be transmitted according to a particular pattern (e.g., a coded signal) to allow an arc flash detection system to distinguish the test EO radiation from EO radiation indicative of an arc flash event. |
| US09653901B2 |
Holding component for vehicle
In a holding component 1, for a vehicle, having: a fixing portion 10 which houses and fixedly engages with a mounting tool 101 having been moved upward through a lower opening 11H; and a holding portion 20 for holding a predetermined member 5 by an upper holding portion 21 and a lower holding portion 22 being engaged with each other, in a state where an engagement portion 23 provided in the upper holding portion 21 is housed in and engaged with an engagement housing portion 24 provided in the lower holding portion 22, a pressing portion 200 provided in the engagement portion 23 presses downward the mounting tool 101 which is engaged with and fixed to the fixing portion 10. |
| US09653899B2 |
Floor stand system for mounting an electrical box
A floor stand system for mounting an electrical box above a floor includes an electrical box mount having a mechanical interface thereon. A set of substantially interchangeable floor supports have mating mechanical interfaces at their upper ends for connecting to the mechanical interface on the electrical box mount. The set of floor supports includes a plurality of floor supports having different fixed lengths. The floor supports are substantially interchangeable so that one of the floor supports having a fixed length suitable for supporting the electrical box mount at a desired elevation above the floor can be selected and connected to the electrical box mount using the mechanical interfaces to create a floor stand suitable for supporting the electrical box mount at the desired elevation above the floor. |
| US09653898B1 |
Electrical outlet faceplate with electrical cord cleat
The electrical outlet faceplate with electrical cord cleat is a cleat plate that is for use with an electrical outlet faceplate. The cleat plate is a structure around which a cable can be secured such that the cable will not be disconnected or damaged inadvertently. The electrical outlet faceplate with electrical cord cleat is attached by a hinge to the electrical outlet faceplate allowing the cleat plate to be rotated to a position perpendicular to the electrical face plate while the cleat plate is in use and allowing the cleat plate to be rotated to a closed position flush to the electrical outlet faceplate when the cleat plate is not in use. The electrical outlet faceplate with electrical cord cleat includes an outlet faceplate, a cleat plate, and a hinge. |
| US09653893B2 |
Ceramic feedthrough brazed to an implantable medical device housing
One aspect is an implantable medical device with a feedthrough assembly having an insulator and a plurality of conducting elements extending therethrough. The feedthrough assembly is placed in a case with an opening defining a narrow space therebetween. A braze material fills the narrow space, thereby hermetically sealing the feedthrough assembly to the case. One of the feedthrough assembly and the case include a feature configured to securely hold the braze and in that the implantable medical device does not include a ferrule. |
| US09653892B2 |
Assembly of compactly integrated contactors in an electrical core
An electrical core comprising an assembly of power management and distribution contactors is provided. The power management contactors are attached to a first support element and the distribution contactors are carried by a second support element superimposed on the first so as to form a multilayer assembly. The distribution contactors are arranged in double symmetry about two axes perpendicular to one another. They are mechanically linked through a mechanical linkage element extending between two rows of contactors and which carries electrical connection elements connecting the contactors to an element for connecting to a power source. The contactors are assembled in modules according to their type. In particular, the management module comprises at least one modular element common to the power management contactors which is suitable for performing a given secondary function other than the function of establishing a contact. |
| US09653884B2 |
High reliability etched-facet photonic devices
Semiconductor photonic device surfaces are covered with a dielectric or a metal protective layer. The protective layer covers the entire device, including regions near facets at active regions, to prevent bare or unprotected semiconductor regions, thereby to form a very high reliability etched facet photonic device. |
| US09653870B1 |
Rare-earth doped gain fibers
Rare earth oxides doped multicomponent glass fibers for laser generation and amplification, including a core and a cladding, the core comprising at least 2 weight percent glass network modifier selected from BaO, CaO, MgO, ZnO, PbO, K2O, Na2O, Li2O, Y2O3, or combinations; wherein the mode of the core is guided with step index difference between the core and the cladding, a numerical aperture of the fiber is between 0.01 and 0.04; core diameter is from 25 to 120 micron, and a length of the gain fiber is shorter than 60 cm. |
| US09653867B2 |
Multi-wavelength source of femtosecond infrared pulses
A source of femtosecond pulses at center wavelengths of about 940 nm and about 1140 nanometers (nm) includes a mode-locked fiber MOPA delivering pulses having a center wavelength of about 1040 nm. The 1040-nanometer pulses are spectrally spread into a continuum spectrum extending in range between about 900 nm and about 1200 nm and having well defined side-lobes around the 940-nm and 1140-wavelengths. Radiation is spatially selected from these side-lobes and delivered as the 940-nm and 1140-nm pulses. |
| US09653866B2 |
Real-time wavelength correction system for visible light
A real-time wavelength correction system for visible light is co-operated with an optical system to make a parallel light beam split into a zero-order diffractive parallel light beam and a first-order diffractive parallel light beam. The zero-order diffractive parallel light beam focuses on a first back focal plane to form a first light spot. A drift of the first light spot is applied to determine an angular drift of the parallel light beam. The first-order diffractive parallel light beam is focused on a second back focal plane to form a second light spot. A drift of the second light spot is applied to determine an angular drift of the first-order diffractive parallel light beam. The angular drifts of the parallel light beam and the first-order diffractive parallel light beam, which are changed with real time temperature variation, are applied to correct the wavelength of the parallel light beam. |
| US09653865B2 |
Method for fitting cables with cable sleeves
A method for fitting cables (13) with seals (1), in which the seals (1) are accommodated via a transfer unit and mounted on the mentioned cable (13). While the seal (1) is being accommodated via the transfer unit, its orientation on the holding arbor (2) is mechanically-electrically and fully automatically checked. If a seal (2) is incompletely or partially punched through, it is removed from the holding arbor (2). Equally, a seal (2) which is not accommodated by the holding arbor (2), is removed from the accommodation area. Also a transfer unit for seals (1) or comparable cable fitting components for a cable processing plant, the transfer unit encompassing a holding arbor (2) for accommodating seals (1), wherein at least one force and/or pressure transducer (3) is situated on or in the holding arbor (2). |
| US09653864B2 |
Wire straightening apparatus
A wire straightening apparatus that straightens kinks of a wire that is fed along a wire feeding path includes one or a plurality of straightening mechanisms. Each straightening mechanism includes a plurality of first straightening rollers and one or a plurality of second straightening rollers. Each roller has a groove along its outer periphery, the groove gradually deepening toward a bottom portion. The bottom portion of the groove of each first straightening roller is spaced from the wire feeding path in a first direction, and the bottom portion of the groove of each second straightening roller is spaced from the wire feeding path in a second direction opposite to the first direction. With this structure, the wire can be made to follow a path that meanders as viewed from a direction perpendicular to axes of the straightening rollers. |
| US09653861B2 |
Interconnection of hardware components
A method and related apparatuses for disconnecting components of a hardware assembly. The components each include two connectors configured to disengage in a staged manner so that one set of connectors disconnects before the other set. If power connectivity is provided across one set of connectors, that connection can be configured to end before the connectivity between the other connectors. |
| US09653856B2 |
Portable universal serial bus (USB) cable keychain assembly with carabiner clip
A cable assembly for connecting a portable electronic device to a host device includes an upstream connector section comprising a upstream connector housing, an upstream connector secured to the upstream connector housing, and a downstream connector section comprising a downstream connector housing, a first downstream connector secured to the downstream connector housing, and a second downstream connector secured to the downstream connector housing. The cable assembly further includes a main body section having an attachment mechanism comprising a through hole formed in the main body, the through hole including on one side a carabiner clip comprising a spring-loaded hinged inwardly movable outer portion completing the through hole. |
| US09653852B2 |
RF-isolating sealing enclosure and interconnection junctions protected thereby
An interconnection junction for communications cables includes: a first connector; a second connector; and a sealing enclosure having a cavity and formed of a polymeric material, the sealing enclosure comprising an RF-isolating material. The first connector and second connector are joined and reside within the cavity of the sealing enclosure. |
| US09653844B1 |
Electronic device connectors with rotatable anchors
An electronic device has an anchor assembly is movably mounted inside the device housing. The anchor assembly has a magnet portion and a ferromagnetic portion, and has a magnetic field that is stronger proximate the magnet portion than the ferromagnetic portion. The anchor assembly rotates between first and second positions, with the magnet portion facing an edge of the device housing for forming a connection with another device, and with the magnet portion facing away from the edge of the housing, respectively. A biasing member biases the connector to the second position by magnetic attraction. |
| US09653843B2 |
Connector
A connector includes: a plate-like terminal which is connected to an end of an electric wire; a rear connector in which the plate-like connector is accommodated; and a front connector in which a box-shaped female terminal that is connected to the plate-like terminal by being assembled to the rear connector and that is to be connected to a counterpart terminal of the electric device side is received. The plate-like terminal and the female terminal are connected by a connection terminal composed of a soft material capable of absorbing both positional displacement between the plate-like terminal and the female terminal and vibration of the plate-like terminal. |
| US09653838B2 |
Dust and debris tolerant retractable cover connector
A debris exclusion and removal apparatus for connectors which have retractable cover configurations which include internal wafers that clean the connectors prior to mating. |
| US09653832B2 |
Conductive elastic member and connector
A conductive elastic member is formed by having a columnar member having elasticity, and plural wire rods which extend from one end face to the other end face of the columnar member in an axial direction and are formed in a state inclined with respect to the axial direction and have conductivity. At least a part of the plural wire rods are cabled in a direction of intersection mutually. |
| US09653831B2 |
Float adapter for electrical connector
A float adapter for an electrical connector that includes a conductive shell and an insulator received in the conductive shell. The insulator includes an engagement end, an interface end that is opposite the engagement end, and a reduced diameter middle portion therebetween. The insulator includes an inner bore that extends through the engagement end, the interface end, and the reduced diameter middle portion. The interface end has a lead-in tip portion that extends outside of the first end of the conductive shell. The lead-in tip portion has a tapered outer surface that terminates in an end face surface and a shoulder remote from the end face surface that defines an outer diameter that is larger than the inner diameter of the conductive shell. An inner contact is received in the inner bore of the insulator. The inner contact has socket openings at either end. |
| US09653830B1 |
Extending device for signal transmission and mainboard assembly
An extending device includes a first riser card, a signal coupling card and a second riser card. A first electric socket of the first riser card is disposed on a side surface of a first circuit board of the first riser card, and a first electric connector is disposed at an edge of the first circuit board. A second electric connector and a third electric connector of the signal coupling card are respectively disposed on both side surfaces of a third circuit board of the signal coupling card. The second electric connector inserts into the first electric socket. A second electric socket and an extending socket of the second riser are respectively disposed on both side surfaces of a second circuit board of the second riser. The third electric connector inserts into the second electric socket and the extending socket is electrically connected to the second electric socket. |
| US09653820B1 |
Active manifold system and method for an array antenna
A system and method uses an active manifold for an antenna array. The manifold can be assembled by a method including providing a first set of cards including a first set of antenna elements and a corresponding number of integrated circuit based time delay units or phase shifters for the first set of antenna elements. The first set of antenna elements is associated with a row of the antenna array. The method also includes providing a second set of cards including a second set of antenna elements and a corresponding number of integrated circuit based time delay units or phase shifters for the second set of antenna elements. The second set of antenna elements is associated with a column of the antenna array. |
| US09653818B2 |
Antenna structures and configurations for millimeter wavelength wireless communications
Methods, systems, and apparatuses are described for wireless communication using the mmW spectrum. In particular, antenna structures may include arrays of antenna elements to deal with line-of-sight issues. Further, antenna structures may be configured to produce a beam (e.g., signal) that is relatively narrow and has a relatively high gain to deal with losses, such as mentioned above. Still further, antenna structures may be configured to provide beam steering (e.g., beamforming) capability. Such antenna structures may be designed to be relatively compact to deal with the limited real estate available on modern wireless communication devices (e.g., cellular telephones). |
| US09653814B2 |
Mode generator device for a satellite antenna system and method for producing the same
The present invention is related to a device for generating waveguide modes for use in a feed horn of a satellite antenna system, said waveguide modes comprising at least one excitation mode of higher order than the fundamental mode, said device comprising a waveguide containing a first waveguide section with at least three longitudinal slots extending in the inner side of said waveguide, characterized in that said waveguide contains a second waveguide section with at least three longitudinal slots extending in said inner side of said waveguide. |
| US09653813B2 |
Diagonally-driven antenna system and method
An electronic device (100) includes an antenna system (150) having two antennas (110, 120). A first antenna (110) has a first antenna element (111) positioned near a first corner (191) of a planar, rectangular ground plane (165) and a second antenna element (115) positioned near a second corner of the ground plane that is diagonally across from the first corner. A second antenna (120) has a third antenna element (121) positioned near a third corner (193) of the ground plane that is adjacent to the first corner and a fourth antenna element (125) positioned near a fourth corner (195) of the ground plane that is diagonally across from the third corner. At low-band frequencies, the antenna elements (111, 115) of the first antenna (110) are driven out-of-phase relative to each other. Similarly, at low-band frequencies, the antenna elements (121, 125) of the second antenna (120) are driven out-of-phase relative to each other. |
| US09653808B2 |
Multilayer patch antenna
Disclosed is a multilayer-type patch antenna including: an upper patch antenna portion having a first through hole and a second through hole which are at a predetermined angle; a lower patch antenna portion having a third through hole and a fourth through hole which are at a predetermined angle, and a fifth through hole which is spaced from the third through hole and the fourth through hole; a first feeding pin which passes through the first through hole and the third through hole and protrudes from a lower end of the lower patch antenna portion; a second feeding pin which passes through the second through hole and the fourth through hole and protrudes from the lower end of the lower patch antenna portion; and a third feeding pin which passes through the fifth through hole and protrudes from the lower end of the lower patch antenna portion. |
| US09653802B2 |
Radar-based fill level measurement device having a security device
A radar-based fill level measurement device having a signal generator for the purpose of generating electromagnetic waves, and an antenna for the purpose of emitting the electromagnetic waves into a container, as well as for the purpose of receiving electromagnetic waves reflected out of the container, having a security device for the purpose of verifying the functional capability or improving the measurement quality of the radar-based fill level measurement device, wherein the security device has a reflector and an adjusting device, and is suitably designed to move the reflector between at least a first position, in which it reflects the electromagnetic waves, and a second position, in which it reflects the electromagnetic waves to a reduced degree, and wherein the security device has a drive which acts on the adjusting device. |
| US09653799B2 |
Method and apparatus for controlling sidelobes of an active antenna array
A method of controlling sidelobe distribution in an active electronically steered array, including electronically reshaping the array aperture so as to reduce sidelobes over a selected region of a coverage volume of the array. In one example, reshaping of the aperture is achieved by electronically turning on and/or off selected radiators in the array to vary the angle of edge discontinuities of the aperture, and thereby move the main sidelobes off the principal plane(s) of operation of the array. |
| US09653797B2 |
Antenna module for near field communication
Embodiments of the invention provide an antenna module for NFC. According to at least one embodiment, the antenna module includes an antenna sheet patterned with a loop coil of a conductive metal material, a magnetic shielding sheet comprising a metal sheet, which is embedded in a magnetic sheet, and an adhesive film interposed between the antenna sheet and the magnetic shielding sheet. |
| US09653795B2 |
Node in a wireless communication network with at least two antenna columns
A node in a wireless communication network, the node comprising at least two antenna columns which are physically separated from each other, each antenna column comprising at least one dual polarized antenna element. Each antenna element has a first polarization and a second polarization. The node further comprises at least two four-port power dividers/combiners, each power divider/combiner having a first port pair and a second port pair, where, for each power divider/combiner, power input into any port in a port pair is isolated from the other port in said port pair, but divided between the ports in the other port pair. Antenna ports of antenna columns that are pair-wise physically separated, from those pairs of antenna columns that are most physically separated to those that are least physically separated, are cross-wise connected to the first port pair in corresponding power dividers/combiners. |
| US09653794B2 |
Broadband antenna and wireless communication device employing same
A broadband antenna is mounted aside a metal electronic element and includes a feeding portion, a first connecting portion, a second connecting portion, a coupling portion, and a ground portion. The first radiating portion and the second radiating portion are both connected perpendicular to the feeding portion. The coupling portion is spaced from the first radiating portion and the second connecting portion. The ground portion is connected perpendicular to a middle portion of the coupling portion and adjacent to the metal electronic element. These portions cooperatively use a low frequency mode and a high frequency mode. The ground portion increases an inductance performance of the broadband antenna, thereby decreasing interference caused by the metal electronic elements. A wireless communication device employing the broadband antenna is also disclosed. |
| US09653793B2 |
Systems and methods for reconfigurable filtenna
Embodiments relate to systems and methods for a frequency reconfigurable filtenna system. Implementations incorporate a reconfigurable band-pass filter within the feeding line of an antenna structure. The combination of the filter and the antenna may be referred to as a “filtenna”. Implementations integrate both the band-pass filter and the antenna within the same substrate, permitting easier, more efficient and more compact integration in the transceiver hardware. Moreover, by using this configuration, the biasing of the switching elements are not present in the radiating plane of the antenna. This reduces the negative effect of the biasing lines on the antenna radiation performance, as we!! as provides a tunable filtered antenna radiation characteristic. |
| US09653789B2 |
Antenna having planar conducting elements, one of which has a slot
An antenna includes a dielectric material having a first side opposite a second side, and a conductive via therein. A first planar conducting element is on the first side of the dielectric material and has at least one closed slot therein, and an electrical connection to the conductive via. A second planar conducting element is on the first side of the dielectric material. Each of the first and second planar conducting elements is positioned adjacent a gap that electrically isolates the first planar conducting element from the second planar conducting element. An electrical microstrip feed line is on the second side of the dielectric material, is electrically connected to the conductive via, and has a route extending from the conductive via, to across the gap, to under the second planar conducting element. The second planar conducting element provides a reference plane for the electrical microstrip feed line. |
| US09653787B2 |
Antenna system for a vehicle
Antenna system for a vehicle including a first directive antenna device and a second antenna device for a frequency band of operation, and a reflector plane, where the first directive antenna device includes a first ground plane, a first dielectric substrate, a first antenna group shorted to the first ground plane and having a first radiating conductor and a second radiating conductor, forming a first configuration and connected to the reflector plane by transmission lines electromagnetically coupled to the frequency band of operation, the reflector plane, disposed forming an angle with respect to the first dielectric substrate, the first directive antenna device radiating in a direction of radiation, and the second antenna device, connected to the first directive antenna device, radiating in an opposing direction to the first directive antenna device. |
| US09653786B2 |
Wearable antenna system
Smaller footprint electronic devices may be contained in a wearable housing, for example in a housing forming a portion of a watch that is worn on a user's wrist. Incorporating antennas into such small footprint devices often precludes the use of anything other than short range communications with another device. Incorporating an antenna into a watch band or bracelet provides a possible avenue to improving the long range communication capabilities and consequent utility of such smaller footprint electrical devices. |
| US09653784B2 |
Conformal, wearable, thin microwave antenna for sub-skin and skin surface monitoring
A wearable antenna is operably positioned on a wearer's skin and is operably connected the wearer's tissue. A first antenna matched to the wearer's tissue is operably positioned on the wearer's skin. A second antenna matched to the air is operably positioned on the wearer's skin. Transmission lines connect the first antenna and the second antenna. |
| US09653778B2 |
Electronic device with display frame antenna
An electronic device has a display mounted in a housing using a plastic display frame. The display has an active area and an inactive area. A display cover layer may have polymer coating layers in the inactive area. The display frame may lie under the inactive area. A patterned metal coating layer may be formed on the display frame. The patterned metal coating layer may have portions that form adhesion promotion structures for promoting adhesion between the frame and the adhesive. The patterned metal coating layer may also have portions that form antenna structures. The antenna structures may be used to transmit and receive radio-frequency signals and may be used as adhesion promotion structures. Adhesive may be interposed between the polymer coating layers and the metal coating layer on the display frame to attach the display cover layer and the display to the display frame. |
| US09653777B2 |
Electronic device with isolated cavity antennas
An electronic device may have a metal housing. The metal housing may have an upper housing in which a component such as a display is mounted and a lower housing in which a component such as a keyboard is mounted. Hinges may be used to mount the upper housing to the lower housing for rotation about a rotational axis. A slot-shaped opening may separate the upper and lower housing. A flexible printed circuit with ground traces may bisect the slot-shaped opening to form first and second slots. Cavity antennas may be aligned with the slots. Each cavity antenna may include a hollow carrier with a pair of speakers. The speakers may have ports that emit sound through aligned openings in the lower housing. Conductive gaskets surrounding the ports may acoustically seal the speaker ports while shorting the cavity antenna to the lower housing. |
| US09653776B2 |
Outdoor wireless access point and antenna adjusting method thereof
An adjusting method of an antenna of the outdoor wireless access point includes steps of A. moving the antenna in a predetermined pointing range, and obtaining received signal strength indications in multiple pointing directions at different time points; B. separating the pointing range into at least two sub-ranges, and averaging the received signal strength indications in all pointing directions in each sub-range; and C. moving the antenna pointing at the sub-range in which the average received signal strength indication is the highest and setting the sub-range as the next predetermined pointing range, and repeating the steps A to C until the step C is executed a predetermined times. Besides, the composition elements of the outer wireless access point are also disclosed. |
| US09653775B2 |
Microwave antenna adjustment apparatus
Embodiments of the present invention disclose a microwave antenna adjustment apparatus, which relates to the field of communications technologies and is invented for resolving a problem that an existing adjustment apparatus has a low horizontal adjustment precision and is costly. The present invention is applicable to adjustment of a microwave antenna. |
| US09653774B2 |
System and method for accurately directing antennas
A system for accurately directing a directional antenna, that includes a calibration system for finding the current azimuth of the antenna and a rotation sensor attached to the antenna, for measuring deviations from the current azimuth of the antenna. The calibration system includes a first GPS receiver located at the antenna's position; a second GPS receiver located adjacent to a visible object at a minimal distance from the antenna and in an arbitrary direction with respect to the first GPS receiver; rotatable optical means positioned adjacent to the antenna in an initial direction being parallel to the current direction of the antenna, the optical means being coupled to a meter for measuring the angle between the current direction and the direction to the visible object by rotating the optical means until seeing the visible object and means for calculating a first azimuth from the position of the first GPS receiver to the position of the second GPS receiver and the current azimuth of the antenna by subtracting the angle from the first azimuth. |
| US09653771B2 |
Directional coupler
A directional coupler includes: a main line connecting an input port and an output port; first to third subline sections each of which is formed of a line configured to be electromagnetically coupled to the main line; a first matching section provided between the first subline section and the second subline section; and a second matching section provided between the second subline section and the third subline section. The first and second matching sections are configured to cause changes in phase of high frequency signals passing therethrough, and have mutually different characteristics so as to create two attenuation poles in the frequency response of the coupling of the directional coupler. |
| US09653767B2 |
Antenna and printed-circuit board using waveguide structure
A waveguide structure including a plurality of unit structures, each of which at least includes a first conductive plane and a second conductive plane, which are arranged to partially face with each other, a plurality of transmission lines with one ends being open ends, which are disposed in a plane, positioned opposite to the second conductive plane, in a layer different from the first conductive plane and the second conductive plane, and at least one conductive via, which electrically connect between the first conductive plane and other ends of the transmission lines. |
| US09653766B2 |
Polarizer and a method of operating the polarizer
A polarizer, such as a septum polarizer, which may alter between two states wherein, effectively, the septum is rotated 180 degrees around the longitudinal axis of the waveguide so that the polarization of the signals in the waveguide may easily be altered without having to alter receivers/transmitters connected to the waveguide. |
| US09653765B2 |
Gas diffusion electrodes for batteries such as metal-air batteries
The present invention generally relates to batteries and, in particular, to electrodes for use in batteries such as non-aqueous metal-air batteries, for example, lithium-air batteries, as well as in other electrochemical devices. Such devices may exhibit improved performance characteristics (e.g. power, cycle life, capacity, etc.). One aspect of the present invention is generally directed to electrodes for use in such devices containing one or more pores or channels for transport of gas and/or electrolyte therein, e.g., forming an open porous network. In certain embodiments, the electrolyte may be a gel or a polymer. In some embodiments, there may be network of such channels or pores within the electrode such that no active site within the electrode is greater than about 50 micrometers distant from a gas channel. In some embodiments, such systems may be created using electrodes containing gel or electrolyte polymers, and/or by forming electrodes having different wettabilities such that certain regions preferentially attract the electrolyte compared to other regions, thereby causing self-organization of the electrolyte within the electrode. Other aspects of the invention are generally directed to methods of making such batteries or electrochemical devices, methods of using such batteries or electrochemical devices, kits involving such batteries or electrochemical devices, or the like. |
| US09653764B2 |
Method and apparatus for recovering sodium from sodium-sulfur battery
A method for recovering sodium from a sodium-sulfur battery of the present invention includes a reaction step of injecting a treatment liquid toward the sodium housed in a sodium-housing component in the battery container and causing the sodium to react with the treatment liquid so as to generate a reaction liquid; and a circulation step of generating the treatment liquid by adjusting the concentration and liquid temperature of the reaction liquid, and, in the reaction step, while the entire amount of the sodium is reacted with the treatment liquid, the treatment liquid is continuously injected toward the sodium. |
| US09653763B2 |
Battery pack comprising a heat exchanger
A heat exchanger assembly includes a fluid transfer layer and a first external layer. The fluid transfer layer is made from an elastomeric material and the first external layer includes flexible graphite. The fluid transfer layer includes at least one channel and is configured to form a passage for receiving a thermal transfer fluid between the channel and a portion of the first external layer. |
| US09653762B2 |
Battery temperature regulation system and battery temperature regulation unit
Provided are a battery temperature regulation system capable of efficiently heating and/or cooling a battery, and a battery temperature regulation unit suitable for use in the battery temperature regulation system. The battery temperature regulation system 10 is provided with a thermally conductive member (e.g., a heat pipe 11) thermally connected to a battery 1, a heating device (e.g., a heater 12) that heats the battery 1 via the thermally conductive member and/or a cooling device (e.g., an air conditioning apparatus) that cools the battery 1 via the thermally conductive member. |
| US09653761B2 |
Secondary battery pack and authentication method
An authenticator (5, 11) is compatible with a plurality of authentication systems to authenticate an external device connected with a connection terminal (OUT, ID), and the authenticator executes authentication processes by the plurality of authentication systems in order, and permits transfer of electric power between the external device and a secondary battery part (1) when any one of authentication processes is successful. |
| US09653754B2 |
Nonaqueous electrolytes and nonaqueous-electrolyte secondary batteries employing the same
A nonaqueous electrolyte containing a monofluorophosphate and/or a difluorophosphate and a compound having a specific chemical structure or specific properties. The nonaqueous electrolyte can contain at least one of a saturated chain hydrocarbon, a saturated cyclic hydrocarbon, an aromatic compound having a halogen atom and an ether having a fluorine atom. |
| US09653753B2 |
Non-aqueous electrolyte solution and non-aqueous electrolyte secondary battery employing the same
The demand for improvements in lithium non-aqueous electrolyte secondary batteries has been constantly increasing in recent years, but the durability—most prominently the cycle characteristics—have resided in a trade off relationship with properties such as the capacity, resistance, and output characteristics. A problem has thus been a poor overall property balance. In order to solve this problem, the present invention uses a non-aqueous electrolyte solution including, in addition to an electrolyte and a non-aqueous solvent, (A) at least one compound selected from the group consisting of carbonates having a carbon-carbon unsaturated bond, compounds represented by the following general formula (1), sulfoxides, sulfites, sulfones, sulfonates, sultones, and sulfates; (B) a fluorine atom-containing cyclic carbonate; and (C) a compound that has at least two isocyanate groups in the molecule. |
| US09653749B2 |
Secondary battery and secondary battery pack having the same
Provided are a secondary battery and a secondary battery pack having the same capable of preventing performance degradation by preventing an increase in an interface resistance of an electrode body accommodated in a pouch and capable of improving stability by preventing deformation of the electrode body to thereby prevent a fine short circuit even though the pouch is swelled due to a gas generate at a high temperature, by providing first members for reinforcing rigidity and second members deformed at the high temperature and capable of adhering the electrode body to one side or both sides of the electrode body accommodated and sealed in the pouch. |
| US09653746B2 |
Manifold for redox flow battery for reducing shunt current and redox flow battery comprising same
A manifold for a redox flow battery capable of effectively suppressing a shunt current has a supply flow pathway and an exhaust flow pathway respectively formed at a left side and a right side of an anode or cathode electrode electrolyte reaction unit so as to include a U-shaped curved portion, and the U-shaped curved portion is formed to be positioned on the upper part of the top or the lower part of the bottom of the first electrode electrolyte reaction unit. When the manifold is applied to a redox flow battery, the supply flow pathway and the exhaust flow pathway having the U-shaped curved portion are formed on the upper part of the top or the lower part of the bottom of the electrode electrolyte reaction unit to prevent an electrolyte existing in the inside of a stack and a pipe from passing through the U-shaped curved portion. |
| US09653745B2 |
Block copolymer, manufacturing method therefor, and polymer electrolyte material, molded polymer electrolyte, and solid-polymer fuel cell using said block copolymer
To provide: a block copolymer that exhibits excellent proton conductivity even under low-humidification conditions, exhibits excellent mechanical strength and chemical stability, and when used in a polymer electrolyte fuel cell, allows high output and excellent physical durability; a polymer electrolyte material; and a polymer electrolyte form article and a polymer electrolyte fuel cell, using the same.The block copolymer of the present invention includes each one or more of: a segment (A1) containing an ionic group; a segment (A2) not containing an ionic group; and a linker moiety connecting the segments. The segment (A1) containing an ionic group comprises a constituent unit represented by a specific structure. The polymer electrolyte material, the polymer electrolyte form article, and the polymer electrolyte fuel cell according to the present invention are manufactured by using the above block copolymer. |
| US09653742B2 |
Fuel cell system
A fuel cell system control device includes a carbon amount determination unit for determining the carbon amount in fuel gas supplied to a fuel cell stack depending on required output of the stack, a temperature detector unit for detecting temperature of a steam reformer and temperature of an evaporator, an S/C determination unit for determining a range of steam/carbon ratio based on the temperature of the steam reformer, a water supply amount determination unit for determining a range of the water supply amount to the evaporator based on the carbon amount and the steam/carbon ratio, an evaporator operating state determination unit for determining whether the temperature of the evaporator is a temperature determined based on the range of the water supply amount, and a reformer control unit for controlling the steam reformer and a partial oxidation reformer based on the result of the evaporator operating state determination unit. |
| US09653741B2 |
Fuel cell stack
A fuel cell stack includes at least one membrane electrolyte assembly having an electrolyte membrane, an anode on a first surface of the electrolyte membrane, and a cathode on a second surface opposite to the first surface of the electrolyte membrane; and at least one supply member coupled to the electrolyte membrane and configured to supply a conductive material to the electrolyte membrane. |
| US09653740B2 |
Fuel cell system
A fuel cell system includes: a fuel cell; a fuel supply source; a supply passage; a circulation passage; a gas-liquid separator; a discharge passage; a discharge valve; a differential pressure detecting portion; and a control unit, wherein the control unit estimates a flow rate of a fuel gas. |
| US09653739B2 |
Electrical connection material for solid oxide fuel cell, solid oxide fuel cell, solid oxide fuel cell module, and method for manufacturing solid oxide fuel cell
A method for manufacturing solid oxide fuel cells, which includes preparing an electrical connection material, preparing a stacked body by stacking a plurality of power generation cells with the electrical connection material interposed therebetween, and firing the stacked body while applying pressure on the stacked body in a direction of stacking the power generation cells. The electrical connection material includes a ceramic porous layer and a ceramic dense layer stacked on the ceramic porous layer, the ceramic dense layer having a porosity lower than a porosity of the ceramic porous layer. |
| US09653738B2 |
Method for producing stainless steel for fuel cell separator, stainless steel for fuel cell separator, fuel cell separator, and fuel cell
A stainless steel for use in a fuel cell separator is produced by subjecting stainless steel containing 16 mass % or more of Cr to electrolytic treatment and thereafter to immersion treatment in a solution containing fluorine. The electrolytic treatment is carried out by anodic electrolyzation or by a combination of anodic electrolyzation and cathodic electrolyzation, and an anodic electrolytic quantity Qa and a cathodic electrolytic quantity Qc preferably satisfy Qa≧Qc. The solution containing fluorine preferably has a temperature of 40° C. or higher, and hydrofluoric acid concentration [HF] (mass %) and nitric acid concentration [HNO3] (mass %) satisfying [HF]≧0.8×[HNO3]. |
| US09653736B2 |
Method of producing porous metal-carbon materials
A method for creating a metal-carbon composite. In one embodiment, the method includes the steps of providing a polymer Schiff base transition metal film precursor having a chemical structure of the formula [M(Schiff)]n and a recurring unit and a transition metal selected from the group consisting of nickel, palladium, platinum, cobalt, copper, iron; Schiff is a tetradentate Schiff base ligand selected from the group consisting of Salen (residue of bis(salicylaldehyde)-ethylenediamine), Saltmen (residue of bis(salicylaldehyde)-tetramethylethylenediamine, Salphen (residue of bis-(salicylaldehyde)-o-phenylenediamine), a substituent in a Schiff base is selected from the group consisting of H—, and carbon-containing substituents, preferably CH3—, C2H5—, CH3O—, C2H5O—, and Y is a bridge in a Schiff base depositing the polymer Schiff base transition metal precursor film onto a support substrate; and heating the polymer Schiff base transition metal precursor film and support substrate in a furnace in an inert atmosphere. |
| US09653734B2 |
Electronically conductive polymer binder for lithium-ion battery electrode
A family of carboxylic acid group containing fluorene/fluorenon copolymers is disclosed as binders of silicon particles in the fabrication of negative electrodes for use with lithium ion batteries. These binders enable the use of silicon as an electrode material as they significantly improve the cycle-ability of silicon by preventing electrode degradation over time. In particular, these polymers, which become conductive on first charge, bind to the silicon particles of the electrode, are flexible so as to better accommodate the expansion and contraction of the electrode during charge/discharge, and being conductive promote the flow battery current. |
| US09653728B2 |
Graphene, power storage device, and electric device
An object is to provide graphene which has high conductivity and is permeable to ions of lithium or the like. Another object is to provide, with use of the graphene, a power storage device with excellent charging and discharging characteristics. Graphene having a hole inside a ring-like structure formed by carbon and nitrogen has conductivity and is permeable to ions of lithium or the like. The nitrogen concentration in graphene is preferably higher than or equal to 0.4 at. % and lower than or equal to 40 at. %. With use of such graphene, ions of lithium or the like can be preferably made to pass; thus, a power storage device with excellent charging and discharging characteristics can be provided. |
| US09653727B2 |
Metal tin-carbon composites, method for producing said composites, anode active material for non-aqueous lithium secondary batteries which is produced using said composites, anode for non-aqueous lithium secondary batteries which comprises said anode active material, and non-aqueous lithium secondary battery
A metal tin-carbon composite having excellent properties required for various use applications, a method for producing the composite at low cost and in a simple manner, and use applications of a non-aqueous lithium secondary battery produced using the composite are provided. A metal tin-carbon composite comprising metal tin nanoparticles (B) contained in a sheet-like matrix (A) composed of carbon, wherein the metal tin-carbon composite contains the metal tin nanoparticle (B) having a particle size of a range of 0.2 nm to 5 nm and does not contain a coarse metal tin particle having a particle size of 1 μm or more, a preferable method for producing the composite using a specific precursor, an anode active material for a non-aqueous lithium secondary battery comprising the composite, a negative electrode for non-aqueous lithium secondary battery using the anode active material, and a non-aqueous lithium secondary battery. |
| US09653725B2 |
Lithium rechargeable battery
The lithium rechargeable battery of the present invention is provided with a current collector and an active material layer containing active material particles 10 supported on this current collector. The active material particles 10 are secondary particles 14 in which a plurality of primary particles 12 of a lithium transition metal oxide are aggregated, and have a hollow structure that contains a hollow section 16 formed inside the secondary particle 14 and a shell section 15 that surrounds the hollow section 16. A through hole 18 that penetrates from the outside to the hollow section 16 is formed in the secondary particle 14. The ratio (A/B) in a powder x-ray diffraction pattern of the active material particles 10, where A is the full width at half maximum of the diffraction peak obtained for the (003) plane and B is the full width at half maximum of the diffraction peak obtained for the (104) plane, satisfies the equation (A/B)≦0.7. |
| US09653721B2 |
Rechargeable battery
A rechargeable battery including an electrode assembly including a separator, and a negative electrode and a positive electrode provided on opposite surfaces of the separator; a case accommodating the electrode assembly therein; a cap plate coupled to the case; a negative electrode terminal and a positive electrode terminal respectively connected to the negative electrode and the positive electrode, the negative electrode terminal and positive electrode terminal extending through a terminal hole of the cap plate; a safety member between the electrode assembly and the case; and a first resistance member connecting the safety member with the negative electrode. |
| US09653718B2 |
Unification-typed electrode assembly and secondary battery using the same
Disclosed herein is an integrated electrode assembly including a cathode, an anode, and a separation layer integrated between the cathode and the anode. The separation layer includes 3 phases including a liquid-phase component containing an ionic salt, which partially flows from the separation layer into the cathode and the anode during preparation of the integrated electrode assembly to increase ionic conductivity of the cathode and the anode, a solid-phase component supporting the separation layer between the cathode and the anode, and a polymer matrix having affinity for the liquid-phase component and providing binding force with the cathode and the anode. |
| US09653715B2 |
Packaged battery, stacked battery assembly, and film-covered battery
A packaged battery, an assembled battery, and a film-covered battery, which can prevent a dangerous state involving a high-pressure gas filled in the film-covered battery while ensuring a sealing reliability, are provided. The Packaged battery includes film-covered battery 1 including a battery element and exterior films forming a sealed space housing the battery element, and holding member 10 holding film-covered battery 1. The sealed space includes a housing section housing the battery element, and a pocket communicating with the housing section to expand when the pressure in the sealed space increases. The pocket includes a safety valve which activates when the pocket expands. Holding member 10 includes an opening and a cavity fitting the housing section therein. When the housing section is fitted into the cavity, at least part of the pocket and the safety valve protrude to the outside of the holding member from the opening. |
| US09653713B2 |
Folding cell holder
A battery cell holder that may be used to form interconnection of cells in series and/or parallel arrangements. The cell holder includes slots for receiving battery cells, conductive apertures within the slots for attaching a conductor to the cells, and a hinge. The cell holder is foldable about the hinge and includes a keying system that allows multiple cell holders to be interconnected to form battery packs of multiple sizes and arrangements. |
| US09653710B2 |
Electrical energy stores, and method for operating an electrical energy store
An electrical energy store and a method for operating an electrical energy store are described. The electrical energy store includes: a housing; at least one energy storage element situated in the housing; and at least one gas-tight cavity, to which an internal pressure is applicable, situated in the housing, with the aid of which a pressure is exertable on at least one section of the energy storage element by applying the internal pressure to the cavity. |
| US09653703B2 |
Electroluminescent device including a protective film between an electroluminescent element and a desiccant layer
In an organic EL display device (electroluminescent device) equipped with an organic EL element (electroluminescent element), the organic EL element is encapsulated by a TFT substrate (substrate), a counter substrate, and a sealing resin. A desiccant layer and a highly-moisture-permeable layer are laminated in this order on the organic EL element. The highly-moisture-permeable layer is in direct contact with the sealing resin. |
| US09653699B2 |
Method of manufacturing a display apparatus
Provided is a display apparatus and a method of manufacture. The display apparatus includes a first substrate with a plurality of organic electroluminescence devices, a second substrate with a color filter, the second substrate facing the first substrate, and an adhesive layer disposed between the first substrate and the second substrate so as to cover the plurality of organic electroluminescence devices, the adhesive layer being made of a material selected from the group consisting of a phenol resin, a melanin resin, an unsaturated polyester resin, an epoxy resin, a silicon resin and a polyurethane resin. |
| US09653688B2 |
Organic devices, organic electroluminescent devices and organic solar cells
An organic device, including an organic compound having charge-transporting ability (i.e., transporting holes and/or electrons) and/or including organic light emissive molecules capable of emitting at least one of fluorescent light or phosphorescent light, has a charge transfer complex-contained layer including a charge transfer complex formed upon contact of an organic hole-transporting compound and molybdenum trioxide via a manner of lamination or mixing thereof, so that the organic hole-transporting compound is in a state of radical cation (i.e., positively charged species) in the charge transfer complex-contained layer. |
| US09653685B2 |
Ink for functional layer formation, method for manufacturing light emitting element, light emitting device, and electronic apparatus
The ink for functional layer formation includes a first component that is a solute; and a second component with a boiling point of 280° C. or higher and 350° C. or lower, is a good solvent, and is at least one type selected from a group consisting of an aromatic hydrocarbon including at least two aromatic rings, aromatic glycol ether, aliphatic glycol ether, aliphatic acetate, and aliphatic ester. |
| US09653681B2 |
Semiconductor memory device
According to one embodiment, a semiconductor memory device includes a plurality of first resistance-change memory elements of a two-terminal type, a second resistance-change memory element of a two-terminal type, a rectifier element of a two-terminal type, a local bit line connected to ends of the first resistance-change memory elements, an end of the second resistance-change memory element and an end of the rectifier element, and a global bit line connected to the other end of the second resistance-change memory element. |
| US09653680B2 |
Techniques for filament localization, edge effect reduction, and forming/switching voltage reduction in RRAM devices
The present disclosure provides a system and method for forming a resistive random access memory (RRAM) device. A RRAM device consistent with the present disclosure includes a substrate and a first electrode disposed thereon. The RRAM device includes a second electrode disposed over the first electrode and a RRAM dielectric layer disposed between the first electrode and the second electrode. The RRAM dielectric layer has a recess at a top center portion at the interface between the second electrode and the RRAM dielectric layer. |
| US09653677B2 |
Magnetoresistive effect element and magnetic memory
The present invention makes it possible to inhibit an MR ratio from decreasing by high-temperature heat treatment in a magnetoresistive effect element using a perpendicular magnetization film. The magnetoresistive effect element includes a data storage layer, a data reference layer, and an MgO film interposed between the data storage layer and the data reference layer. The data storage layer includes a CoFeB film coming into contact with the MgO film, a perpendicular magnetization film, and a Ta film interposed between the CoFeB film and the perpendicular magnetization film. The CoFeB film is magnetically coupled to the perpendicular magnetization film through the Ta film. |
| US09653670B2 |
Method for producing an optoelectronic semiconductor component, and optoelectronic semiconductor component
In at least one embodiment, the semiconductor component includes at least one optoelectronic semiconductor chip having a radiation exit side. The surface-mountable semiconductor component comprises a shaped body that covers side surfaces of the semiconductor chip directly and in a positively locking manner. The shaped body and the semiconductor chip do not overlap, as seen in a plan view of the radiation exit side. |
| US09653669B2 |
LED package structure
An LED package structure includes a base, an LED chip disposed on the base, at least one metal wire, a phosphor sheet, and an encapsulation resin disposed in the base and encapsulating the LED chip, the metal wire, and the phosphor sheet. The LED chip has at least one electrode thereon. The metal wire has an apex and a loop height being defined by the apex. The metal wire is electrically connected to the electrode and the base. The phosphor sheet includes a B-stage resin and a plurality of phosphor powders mixed therewith. The phosphor sheet is adhered to the LED chip by the B-stage resin capable of viscosity and covers the top surface, the side surface, and the electrode of the LED chip. A thickness of the phosphor sheet is smaller than the loop height, and the apex of the metal wire is exposed from the phosphor sheet. |
| US09653663B2 |
Ceramic LED package
A package for multiple LED's and for attachment to a substrate includes a body, which includes a top body layer, a cavity disposed through the top body layer and having a floor for bonding to the multiple LED's, and a thermal conduction layer bonded to the top body layer and having a top surface forming the floor of the cavity and a bottom surface. The thermal conduction layer includes a thermally conducting ceramic material disposed between the floor and the bottom surface. The package also includes a plurality of LED bonding pads in direct contact with the floor and configured to bond to the multiple LED's and a plurality of electrical bonding pads in direct contact with the floor, proximate to the LED bonding pads, and in electrical communication with a plurality of electrical contacts disposed on a surface of the body. |
| US09653660B1 |
Chip scale LED packaging method
A chip scale LED packaging method includes the following steps: clamping an upper mold with a plurality of through holes and a plate-shaped lower mold together; allowing bottoms of the plurality of through holes of the upper mold to be sealed by the plate-shaped lower mold to form a pattern of a plurality of grooves; placing chips one by one in corresponding through holes of the plurality of through holes; pouring encapsulation gel into each of the corresponding through holes; separating the upper mold from the plate-shaped lower mold after the encapsulation gel is cured and molded; and separating each cured and molded encapsulation gel from each of the corresponding through holes of the upper mold and taking each cured and molded encapsulation gel out of the upper mold to obtain an individual chip scale LED package. |
| US09653658B2 |
Red phosphor and light emitting device including the same
A red phosphor including the composition represented by the following general formula. (x−a)MgO.(a/2)Sc2O3.yMgF2.cCaF2.(1−b)GeO2.(b/2)M2O3:zMn4+ where x, y, z, a, b, and c satisfy 2.0≦x≦4.0, 0 |
| US09653657B2 |
Semiconductor light emitting apparatus
A semiconductor light emitting apparatus comprised of a semiconductor light emitting device (100) having a layered semiconductor layer (110) configured by layering at least two or more semiconductor layers (103), (105) and a light emitting layer (104) to emit first light, and a wavelength conversion member that covers at least apart of the semiconductor light emitting device (100), absorbs at least a part of the first light and that emits second light with a wavelength different from that of the first light, characterized in that the semiconductor light emitting device (100) is provided with a fine structure layer, as a component, including dots comprised of a plurality of convex portions or concave portions extending in the out-of-plane direction on one of main surfaces forming the semiconductor light emitting device (100), the fine structure layer forms a two-dimensional photonic crystal (102) controlled by at least one of a pitch among the dots, a dot diameter and a dot height, and that the two-dimensional photonic crystal (102) has at least two or more periods each of 1 μm or more. |
| US09653651B2 |
Light emitting device and method for manufacturing light emitting device
A light emitting device that is inexpensive, is easy to manufacture, and has high light extraction efficiency is provided. The light emitting device includes an oriented polycrystalline substrate, a plurality of columnar light emitting parts, and a light confinement layer. The oriented polycrystalline substrate includes a plurality of oriented crystal grains. The plurality of columnar light emitting parts are discretely located on or above one main surface of the oriented polycrystalline substrate in areas in which there are no crystal defects, and are each a columnar part having a longitudinal direction matching a normal direction of the oriented polycrystalline substrate. The light confinement layer is made of a material having a lower refractive index than a material for the plurality of columnar light emitting parts, and is located on or above the oriented polycrystalline substrate so as to surround the plurality of columnar light emitting parts. |
| US09653649B2 |
Gallium nitride substrates and functional devices
The maximum value of peak intensities of cathode luminescence of a wavelength corresponding to a band gap of gallium nitride and in a measured visual field of 0.1 mm×0.1 mm is 140 percent or higher of an average value of the peak intensities of the cathode luminescence, provided that the peak intensities of the cathode luminescence are measured on a surface of the gallium nitride substrate. |
| US09653647B2 |
Ultrathin solid state dies and methods of manufacturing the same
Various embodiments of SST dies and solid state lighting (“SSL”) devices with SST dies, assemblies, and methods of manufacturing are described herein. In one embodiment, a SST die includes a substrate material, a first semiconductor material and a second semiconductor material on the substrate material, an active region between the first semiconductor material and the second semiconductor material, and a support structure defined by the substrate material. In some embodiments, the support structure has an opening that is vertically aligned with the active region. |
| US09653637B2 |
Air cooled photovoltaic cells
An apparatus is provided that comprises photovoltaic cells provided on a first rotatable member, an electric motor having an axial shaft, and a second rotatable member provided with an impeller. The photovoltaic cells capture and convert the solar energy into electrical energy. The electric motor is connected to and is in electric communication with the photovoltaic cells for powering the electric motor. The electric motor converts the electrical energy into mechanical energy for rotating the photovoltaic cells in a first direction about a central axis and for rotating the axial shaft connected to an impeller in a second direction about the central axis. The rotating axial shaft rotates the impeller at high revolutions per minute which generates a flow of air that is directed to the rotating photovoltaic cells on the first rotatable member. The photovoltaic cells are cooled by the air-flow and operate at a lower temperature. |
| US09653629B2 |
Substrate material of iron-nickel alloy metal foil for CIGS solar cells
The present invention relates to an exclusive alloy substrate material for CIGS solar cells. Particularly, the present invention provides a substrate material having a thermal expansion coefficient similar to that of a CIGS layer. The substrate material according to the present invention may prevent damage such as interlayer separation due to differing thermal expansion coefficients from occurring because the substrate material has a thermal expansion coefficient similar to that of the CIGS layer. |
| US09653628B2 |
Absorber layer for photovoltaic device, and method of making the same
A photovoltaic device includes a substrate, a back contact layer disposed above the substrate, and an absorber layer disposed above the back contact layer. The absorber layer includes at least two regions at respectively different horizontally locations. Each respective region has a respectively different concentration profile of an ingredient at a respective depth of the absorber layer. |
| US09653627B2 |
Arrangements with pyramidal features having at least one nanostructured surface and methods of making and using
One embodiment is a nanostructured arrangement having a base and pyramidal features formed on the base. Each pyramidal feature includes sloping sides converging at a vertex. The nanostructured arrangement further includes a nanostructured surface formed on at least one of the sloping sides of at least one of the pyramidal features. The nanostructured surface has a quasi-periodic, anisotropic array of elongated ridge elements having a wave-ordered structure pattern. Each ridge element has a wavelike cross-section and oriented substantially in a first direction. |
| US09653625B2 |
Method for manufacturing anti-reflective coating for solar cell having moth-eye structure and solar cell incliding the same
A method of manufacturing antireflective coating for solar cell having a moth-eye structure and a solar cell including the same are provided to greatly reduce reflectivity by forming an antireflective coating layer having a moth-eye structure on an upper electrode layer of the solar cell using a bottom-up method. A bottom electrode layer is formed on a substrate. A photoreactive layer is formed on the bottom electrode layer. The photoreactive layer is made of CIS (Copper, Indium, Selenide) materials. A buffer layer is formed on the photoreactive layer. A ZnO layer is formed on the buffer layer. A top electrode layer is formed on the ZnO layer. |
| US09653620B2 |
Semiconductor device
A semiconductor device including a p or p+ doped portion and an n or n+ doped portion separated from the p or p+ doped portion by a semiconductor drift portion. The device further includes an insulating portion provided adjacent the drift portion and at least one of the doped portions in a region where the drift portion and the at least one doped portion meet. The device further includes at least one additional portion, wherein the at least one additional portion is located such that, when the doped portions and the at least one additional portion are biased, the electrical potential lines leave the semiconductor drift portion homogeneously. |
| US09653613B2 |
Semiconductor device and manufacturing method thereof
Provided is a transistor with stable electrical characteristics. Provided is a semiconductor device including an oxide semiconductor over a substrate, a first conductor in contact with a top surface of the oxide semiconductor, a second conductor in contact with the top surface of the oxide semiconductor, a first insulator over the first and second conductors and in contact with the top surface of the oxide semiconductor, a second insulator over the first insulator, a third conductor over the second insulator, and a third insulator over the third conductor. The third conductor overlaps with the first conductor with the first and second insulators positioned therebetween, and overlaps with the second conductor with the first and second insulators positioned therebetween. The first insulator contains oxygen. The second insulator transmits less oxygen than the first insulator. The third insulator transmits less oxygen than the first insulator. |
| US09653612B2 |
Semiconductor device
A semiconductor device includes a gate electrode having a first side wall at an end thereof, a gate insulating layer on a top surface and the first side wall of the gate electrode, an oxide semiconductor layer facing the first side wall, the gate insulating layer being between the first side wall and the oxide semiconductor layer, a first insulating layer on the oxide semiconductor layer, the oxide semiconductor layer being between the gate insulating layer and the first insulating layer, a first electrode connected with a first portion of the oxide semiconductor layer, and a second electrode connected with a second portion of the oxide semiconductor layer. |
| US09653602B1 |
Tensile and compressive fins for vertical field effect transistors
Various embodiments disclose a method for fabricating one or more vertical fin field-effect-transistors. In one embodiment, a spacer layer is formed in contact with at least one fin structure. The at least one fin structure contacts a source/drain layer formed on a substrate and includes a channel material. A high-k dielectric layer is formed in contact with the spacer layer and the at least one fin structure. A work function metal layer is formed in contact with and conforms to the high-k dielectric layer. A metal gate layer is formed in contact with the work function metal layer. The metal gate layer includes an intrinsic stress inducing a stress on the at least one fin structure. |
| US09653600B2 |
Semiconductor device and method of fabricating same
A semiconductor device and method of fabricating the semiconductor device are disclosed. The method includes forming a plurality of gate electrodes at a predetermined interval on a surface of a semiconductor substrate, forming spacers on sidewalls of the gate electrodes, depositing an interconnection layer conformally on the surface of the semiconductor substrate over the gate electrodes and the spacers, selectively etching the interconnection layer, wherein at least a portion of the interconnection layer that is formed on the surface of the semiconductor substrate and sidewalls of the spacers and located between adjacent gate electrodes remains after the selective etch, and forming an electrical contact on the etched interconnection layer located between the adjacent gate electrodes. |
| US09653596B2 |
Superjunction device and semiconductor structure comprising the same
The present disclosure relates to a superjunction device and a semiconductor structure having the same. The superjunction device includes a body region of a second conduction type, a drain region of a first conduction type, a drift region located between said body region and said drain region. The drift region includes first regions of a first conduction type and second regions of a second conduction type arranged alternately along a direction being perpendicular to the direction from the body region to the drain region, and a plurality of trench gate structures, each of them comprising a trench extending into said drift region from an upper surface of said body region and a gate electrode in said trench surrounded by a first dielectric layer filling said trench, and a source region of a first conduction type embedded into said body region. There is no source region along at least 10% of the total interface length between the first dielectric layer and the body region. |
| US09653591B2 |
Compound semiconductor device having at least one buried semiconductor material region
A semiconductor device includes a first compound semiconductor material, a second compound semiconductor material on the first compound semiconductor material, the second compound semiconductor material having a first doping concentration and including a different material than the first compound semiconductor material, a control electrode, and at least one buried semiconductor material region having a second doping concentration different from the first doping concentration. The at least one buried semiconductor material region is disposed in the second compound semiconductor material in a region other than a region of the second compound semiconductor material being covered by the control electrode. |
| US09653588B2 |
GaN substrate, semiconductor device and method for fabricating GaN substrate and semiconductor device
A gallium nitride (GaN) substrate, a semiconductor device, and methods for fabricating a GaN substrate and a semiconductor device are provided. The GaN substrate includes: a GaN base; an aluminum gallium nitride (AlGaN) layer, disposed on the GaN base; and a p-type conducting layer disposed on an active area of the AlGaN layer, and used to exhaust surface state negative electrons on the AlGaN layer and neutralize a dangling bond on the AlGaN layer. The p-type conducting layer is formed on the AlGaN layer, and a hole charge carrier in the p-type conducting layer can be used to exhaust the surface state negative electrons on an n-type AlGaN layer, neutralize the dangling bond on a section of the AlGaN layer, and prevent the forming of a virtual gate, so as to suppress a current collapse effect of the semiconductor device fabricated using the GaN substrate. |
| US09653586B2 |
Amplifier device comprising enhanced thermal transfer and structural features
A heterojunction bipolar transistor (HBT) amplifier device includes transistor fingers arranged in parallel on a substrate. Each transistor finger includes a base/collector mesa stripe shaving a trapezoidal shaped cross-section with sloping sides, and having a base stacked on a collector; a set of emitter mesa stripes arranged on the base/collector mesa stripe; and emitter metallization formed over the set of emitter mesa stripes and the base/collector mesa. The emitter metallization includes a center portion for providing electrical and thermal connectivity to the emitter mesa stripes and extended portions extending beyond the base and overlapping onto the sloping sides of the base/collector mesa stripe for increasing thermal coupling to the collector. A common conductive pillar is formed over the transistor fingers for providing electrical and thermal conductivity. Also, thermal shunts are disposed on the substrate between adjacent transistor fingers, where the thermal shunts are electrically isolated from the transistor fingers. |
| US09653585B2 |
Vertical gate-all-around TFET
A vertical tunneling FET (TFET) provides low-power, high-speed switching performance for transistors having critical dimensions below 7 nm. The vertical TFET uses a gate-all-around (GAA) device architecture having a cylindrical structure that extends above the surface of a doped well formed in a silicon substrate. The cylindrical structure includes a lower drain region, a channel, and an upper source region, which are grown epitaxially from the doped well. The channel is made of intrinsic silicon, while the source and drain regions are doped in-situ. An annular gate surrounds the channel, capacitively controlling current flow through the channel from all sides. The source is electrically accessible via a front side contact, while the drain is accessed via a backside contact that provides low contact resistance and also serves as a heat sink. Reliability of vertical TFET integrated circuits is enhanced by coupling the vertical TFETs to electrostatic discharge (ESD) diodes. |
| US09653582B2 |
Forming a Fin using double trench epitaxy
The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming a fin using double trench epitaxy. The fin may be composed of a III-V semiconductor material and may be grown on a silicon, silicon germanium, or germanium substrate. A double trench aspect ratio trapping (ART) epitaxy method may trap crystalline defects within a lower trench (i.e. a defective region) and may permit formation of a fin free of patterning defects in an upper trench (i.e. a fin mold). Crystalline defects within the defective region may be trapped via conventional aspect ratio trapping or three-sided aspect ratio trapping. Fin patterning defects may be avoided by utilizing a fin mold to grow an epitaxial fin and selectively removing dielectric material adjacent to a fin region. |
| US09653580B2 |
Semiconductor device including strained finFET
A semiconductor device includes at least one semiconductor fin on an upper surface of a base substrate. The at least one semiconductor fin includes a strained active semiconductor portion interposed between a protective cap layer and the base substrate. A gate stack wraps around the at least one semiconductor fin. The gate stack includes a metal gate element interposed between a pair of first cap segments of the protective cap layer. The strained active semiconductor portion is preserved following formation of the fin via the protective cap layer. |
| US09653577B2 |
Diluted drift layer with variable stripe widths for power transistors
A multi-finger lateral high voltage transistors (MFLHVT) includes a substrate doped a first dopant type, a well doped a second dopant type, and a buried drift layer (BDL) doped first type having a diluted BDL portion (DBDL) including dilution stripes. A semiconductor surface doped the second type is on the BDL. Dielectric isolation regions have gaps defining a first active area in a first gap region (first MOAT) and a second active area in a second gap region (second MOAT). A drain includes drain fingers in the second MOAT interdigitated with source fingers in the first MOAT each doped second type. The DBDL is within a fingertip drift region associated drain fingertips and/or source fingertips between the first and second MOAT. A gate stack is on the semiconductor surface between source and drain. The dilution stripes have stripe widths that increase monotonically with a drift length at their respective positions. |
| US09653575B1 |
Vertical transistor with a body contact for back-biasing
A method of forming a substrate contact in a vertical transistor device includes patterning a sacrificial layer to form an opening in the sacrificial layer, the sacrificial layer disposed on hardmask arranged on a substrate, and the substrate including a bulk semiconductor layer, a buried oxide layer arranged on the bulk semiconductor layer, and a semiconductor layer arranged on the buried oxide layer; forming oxide spacers on sidewalls of the opening in the sacrificial layer; using the oxide spacers as a pattern to etch a trench through the substrate, the trench stopping at a region within the bulk semiconductor layer; and depositing a conductive material in the trench to form the substrate contact. |
| US09653572B2 |
Method for fabricating semiconductor device
A method of fabricating a semiconductor device includes forming a dummy gate on a substrate, forming a dummy gate mask on the dummy gate, forming a gate spacer on the substrate, the gate spacer covering at least one sidewall surface of the dummy gate and the dummy gate mask, forming a recess on at least one side of the dummy gate by etching the substrate, and forming an epitaxial layer in the recess using an epitaxial growth process. The forming of the dummy gate mask includes forming an oxide layer and a dummy gate mask layer on the dummy gate. |
| US09653570B2 |
Junction interlayer dielectric for reducing leakage current in semiconductor devices
A semiconductor device includes a substrate and a p-doped layer including a doped III-V material on the substrate. A dielectric interlayer is formed on the p-doped layer. An n-type layer is formed on the dielectric interlayer, the n-type layer including a high band gap II-VI material to form an electronic device. |
| US09653569B1 |
Compound semiconductor device and manufacturing method thereof
A compound semiconductor stacked structure is constituted by including: a buffer layer; an n-type conductive region that is formed at one portion of the buffer layer; an channel layer that is formed on a top surface of the buffer layer and on a top surface of the n-type conductive region; and an barrier layer that is formed above the channel layer and contains Inx1Aly1Gaz1N (0≦x1<1, and 0 |
| US09653564B2 |
Semiconductor device and method of manufacturing the same
There is provided a method of manufacturing a semiconductor device. The method of manufacturing comprises a film formation process of forming a molybdenum layer that is mainly made of molybdenum (Mo), on at least one of a semiconductor layer, an insulating film and an electrode in the semiconductor device; a heat treatment process of heating the molybdenum layer at temperature of not lower than 200° C.; and a dry etching process of processing the semiconductor device that includes the formed molybdenum layer by dry etching, subsequent to the heat treatment process. |
| US09653561B2 |
Low on resistance semiconductor device
A semiconductor device is provided having a dual dielectric layer structure defined by a thin dielectric layer adjacent to a thick dielectric layer. More particularly, a high voltage metal oxide semiconductor transistor having a dual gate oxide layer structure comprising a thin gate oxide layer adjacent to a thick oxide/thin oxide layer may be provided. Such structures may be used in extended drain metal oxide semiconductor field effect transmitters, laterally diffused metal oxide field effect transistors, or any high voltage metal oxide semiconductor transistor. Methods of fabricating an extended drain metal oxide semiconductor transistor device are also provided. |
| US09653560B1 |
Method of fabricating power MOSFET
A method of fabricating a power metal oxide semiconductor field effect transistor (MOSFET) is provided, and the method includes forming a semiconductor layer on a substrate, forming at least one first trench in the semiconductor layer, forming a thermal oxide layer on a surface of the trench, forming a first gate in the first trench, forming a chemical vapor deposition (CVD) oxide layer on the first gate in the first trench, forming a mask layer on the CVD oxide layer in the first trench so as to form a second trench between the mask layer and the thermal oxide layer, and forming a second gate in the second trench. |
| US09653557B2 |
Semiconductor device
A semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region having a second conductivity type, a first insulating layer on the first and second semiconductor regions, and field plate electrodes are provided in the first insulating layer at different distances from the first semiconductor layer. A first field plate electrode is at a first distance, a second field plate electrode is at a second distance greater than the first distance, and a third field plate electrode is at a distance greater than the second distance. The first through third field plate electrodes are electrically connected to each other and the third electrode is electrically connected to the second semiconductor region. |
| US09653553B2 |
Semiconductor substrate, semiconductor device and method of manufacturing semiconductor device
A semiconductor substrate of an embodiment includes a SiC layer having a surface inclined in a <11-20> direction plus or minus 5° from a {0001} face at an off angle of 0° to 10°. Area density of threading edge dislocation clusters in the SiC layer is 18.8 cm−2 or less, each of the threading edge dislocation clusters includes a plurality of threading edge dislocations on the surface, the threading edge dislocations included in each of the threading edge dislocation clusters exist in a region that extends in a [1-100] direction plus or minus 5° and has a width of 30 μm or less, each of the threading edge dislocation clusters includes at least three threading edge dislocations adjacent at an interval of 30 μm or less, and an interval of adjacent threading edge dislocations in each of the threading edge dislocation clusters is 70 μm or less. |
| US09653549B2 |
Semiconductor device formed with nanowire
A semiconductor device is provided. The semiconductor device includes a substrate; a first nanowire disposed over the substrate; a second nanowire disposed over the substrate; a first pad formed at first ends of the first and second nanowires, a second pad formed at second ends of the first and second nanowires, wherein the pads comprise different materials than the nanowires; and a gate surrounding at least a portion of each of the first and second nanowires. |
| US09653547B1 |
Integrated etch stop for capped gate and method for manufacturing the same
A semiconductor device includes a plurality of gate stacks spaced apart from each other on a substrate, an etch stop layer formed on an upper surface of each gate stack, a dielectric cap layer formed on each etch stop layer, a plurality of source/drain regions formed on the substrate between respective pairs of adjacent gate stacks, and a plurality of contacts respectively corresponding to each source/drain region, wherein the contacts are separated from the gate structures and contact their corresponding source/drain regions. |
| US09653546B2 |
Nanowire structure and manufacturing method thereof
A manufacturing method of a nanowire structure includes the following steps. A fin and a shallow trench isolation (STI) are formed on a substrate. A first patterned insulation layer is formed on an exposed upper part of the fin. The STI is then recessed for exposing a lower part of the fin. A second patterned insulation layer is formed in second regions for covering the first patterned insulation layer and the exposed part of the fin. The lower part of the fin is then removed for forming an upper fin and a lower fin in a first region. The STI is further recessed for exposing a portion of the lower fin and a portion of the fin in the second regions. The first patterned insulation layer on the first region is removed, and the upper fin is converted into a first nanowire. |
| US09653531B2 |
Methods of manufacturing a package
A method of manufacturing a package may include: providing a first device having a first redistribution layer (RDL) and an insulator layer disposed over the first RDL; and forming a first micro-bump line over the insulator layer of the first device. The first micro-bump line may extend laterally over a surface of the insulator layer facing away from the first RDL, and a first inductor of the package comprises the first RDL and the first micro-bump line. |
| US09653530B2 |
Organic light-emitting diode module equipped with vertical electric connection structure
An OLED module equipped with vertical electric connection structure includes a substrate, a plurality of OLED clusters, an anode wire structure and a cathode wire structure. The substrate is extended toward a first direction. The OLED clusters are located on the substrate in the first direction. The anode wire structure includes a bottom layer wire set, an insulation layer, a middle wire layer set and a top layer wire set. The bottom layer wire set is located on the substrate. The insulation layer is located on the bottom layer wire set. The top layer wire set is located on the insulation layer. The cathode wire structure is located on the substrate and extended axially thereof. The middle layer wire set runs through the insulation layer and forms vertical connection between the bottom layer wire set and the top layer wire set. |
| US09653524B2 |
Organic light emitting display apparatus
An organic light emitting display apparatus includes: a first pixel electrode and a second pixel electrode on a substrate and spaced apart from each other, each of the first pixel electrode and the second pixel electrode including a reflective layer; a pixel definition layer extending between and overlapping adjacent edges of the first pixel electrode and the second pixel electrode; a first intermediate layer and a second intermediate layer respectively on the first pixel electrode and the second pixel electrode; and an opposite electrode on the first intermediate layer, the second intermediate layer and the pixel definition layer and including a reflective layer. |
| US09653511B2 |
CMOS image sensor with peninsular ground contracts and method of manufacturing the same
A complementary metal oxide semiconductor (CMOS) image sensor with peninsular ground contacts includes (a) a substrate having a plurality of pixel units arranged in rows of pixel units and (b) a plurality of ground contacts for grounding the pixel units, wherein the ground contacts are formed in respective peninsular regions of the substrate within respective ones of the pixel units, and wherein each of the peninsular regions is only partly enclosed by a shallow trench isolation and the peninsular regions have alternating orientation along each of the rows of pixel units. |
| US09653508B2 |
Pad structure exposed in an opening through multiple dielectric layers in BSI image sensor chips
An integrated circuit structure includes a semiconductor substrate, and a dielectric pad extending from a bottom surface of the semiconductor substrate up into the semiconductor substrate. A low-k dielectric layer is disposed underlying the semiconductor substrate. A first non-low-k dielectric layer is underlying the low-k dielectric layer. A metal pad is underlying the first non-low-k dielectric layer. A second non-low-k dielectric layer is underlying the metal pad. An opening extends from a top surface of the semiconductor substrate down to penetrate through the semiconductor substrate, the dielectric pad, and the low-k dielectric layer, wherein the opening lands on a top surface of the metal pad. A passivation layer includes a portion on a sidewall of the opening, wherein a portion of the passivation layer at a bottom of the opening is removed. |
| US09653505B2 |
Method for fabricating photo detector having sensor element array and photo conversion element
A photo detector and a method for fabricating the same are provided. The photo detector includes a first substrate and a photo conversion element. The first substrate has a sensor element array for receiving a light with a spectrum in a specific wavelength range. The photo conversion element is disposed on the sensor element array, where the photo conversion element includes a photo conversion material layer and a doped photo conversion material column structure layer. A luminescent spectrum of the doped photo conversion material layer column structure layer is overlapped with the spectrum in a specific wavelength range, and a luminescent spectrum of the photo conversion material layer is non-overlapped with the spectrum in a specific wavelength range. |
| US09653501B2 |
Image sensor including color filter and method of manufacturing the image sensor
An image sensor including a color filter and a method of manufacturing the image sensor are provided. The image sensor includes a light-sensing layer configured to detect incident light, and convert the incident light to an electrical signal. The image sensor further includes a color filter layer disposed on the light-sensing layer, the color filter layer including color filters, each of the color filters being configured to transmit, among the incident light, light in a wavelength band to the light-sensing layer. The image sensor further includes an isolation layer disposed between the color filters, the isolation layer being configured to optically isolate the color filters from each other. An upper portion of each of the color filters has a cylindrical shape, and a lower portion of each of the color filters has a hemispherical shape. |
| US09653500B2 |
Optical cover plate with improved solder mask dam on glass for image sensor package and fabrication method thereof
An optical cover plate for image sensor package includes a transparent substrate, at least an annular dam structure, and a barrier layer. The annular dam structure is disposed on the transparent substrate and encompasses a light-receiving area. The barrier layer conformally covers at least a sidewall of the annular dam structure. A method of manufacturing the optical cover plate, an image sensor package and fabrication method thereof are also disclosed. |
| US09653498B2 |
Imaging device having electrode overlying photoelectric conversion layer and having electrical contact to electrode
An imaging device includes a plurality of pixels arranged in a pixel region, each of the plurality of pixels including a photoelectric conversion element including a first electrode provided above a substrate, a second electrode provided above the first electrode and a photoelectric conversion layer provided between the first electrode and the second electrode, an interconnection layer provided between the substrate and the first electrode, the interconnection layer including a first conductive member extending in a first direction, and a second conductive member arranged at a level lower than the first conductive member and extending in a second direction intersecting the first direction, a first contact portion provided in the pixel region, the first contact portion electrically connecting the second electrode and the first conductive member, and a second contact portion electrically connecting the first conductive member and the second conductive member. |
| US09653496B2 |
Preparation method of poly-silicon TFT array substrate and array substrate thereof
A preparation method of a poly-silicon thin film transistor (TFT) array substrate and an array substrate thereof are provided. The preparation method includes: forming a photoresist layer on a poly-silicon layer, and exposing and developing the photoresist layer with a gray tone mask to form patterns of a photoresist completely-reserved region, a photoresist partially-reserved regions and a photoresist completely-removed region; removing part of the poly-silicon layer located in the photoresist completely-removed region, to form patterns of active layers; ashing the photoresist so as to expose part of the active layer located in the photoresist partially-reserved regions and inject P+ ions of high concentration into the part of the active layer, to form doping regions of patterns of source-drain electrodes of a P-type TFT; and stripping off remaining photoresist. |
| US09653495B2 |
Method of manufacturing display device
A method of manufacturing a display device includes: forming a gate electrode on a substrate; forming a gate insulating film on the substrate; forming an oxide semiconductor on the substrate; forming a source electrode and a drain electrode on the substrate; forming a passivation film on the substrate; forming a common electrode on the substrate; forming an interlayer insulating film on the substrate; forming a pixel electrode on the substrate; forming an alignment film on the substrate; radiating UV-rays onto the oxide semiconductor; and heat-treating the oxide semiconductor irradiated with the UV-rays. The radiating UV-rays is performed after the forming an oxide semiconductor, and the heat-treating is performed after the forming a passivation film. |
| US09653494B2 |
Array substrate, display panel and display apparatus
A thin-film transistor (TFT) array substrate is provided. The thin-film transistor (TFT) array substrate comprises a substrate having at least a display region; and a plurality of top-gated thin-film transistors formed over the substrate. The thin-film transistor (TFT) array substrate also comprises a plurality of scan lines and a plurality of data lines formed over the substrate in the display region and defining a plurality of sub-pixels, wherein a plurality of pre-reserved blank regions are configured among the scan lines, the data lines, and the plurality of sub-pixels in the display region; and a gate driver circuit formed over the substrate in the display region and disposed in the pre-reserved blank regions in the display region. |
| US09653487B2 |
Semiconductor device, manufacturing method thereof, module, and electronic device
A semiconductor device includes a transistor and a capacitor. The transistor includes a first conductive film; a first insulating film including a film containing hydrogen; a second insulating film including an oxide insulating film; an oxide semiconductor film including a first region and a pair of second regions; a pair of electrodes; a gate insulating film; and a second conductive film. The capacitor includes a lower electrode, an inter-electrode insulating film, and an upper electrode. The lower electrode contains the same material as the first conductive film. The inter-electrode insulating film includes a third insulating film containing the same material as the first insulating film and a fourth insulating film containing the same material as the gate insulating film. The upper electrode contains the same material as the second conductive film. A fifth insulating film containing hydrogen is provided over the transistor. |
| US09653483B2 |
Display motherboard, display panel and display device
The invention provides a display motherboard, a display panel and a display device for solving the problem of unsmooth cutting of the display motherboard in the prior art during cutting. In the display motherboard, the display panel and the display device provided by the present invention, a cutting area of the display motherboard is provided with a raised portion on one side close to sealant, and the raised portion can make the cutting stress more concentrated when the display motherboard is cut, so that adhesion of the sealant to substrates is reduced and thus the display motherboard is cut more smoothly. |
| US09653482B2 |
Display panel and display device
A display panel comprises a TFT substrate and a display medium layer. The display medium layer is disposed on the TFT substrate. The TFT substrate comprises a TFT and a substrate. The TFT is disposed on the substrate and comprises a gate, a metal oxide layer, a source, a drain and a protection layer. The gate is disposed corresponding to the metal oxide layer. The protection layer is disposed on the metal oxide layer. Each of the source and the drain contacts the metal oxide layer through an opening of the protection layer. One side of the gate or one side of the metal oxide layer partially overlaps at least one of the openings. In addition, a display device is also disclosed. |
| US09653479B2 |
Semiconductor device and electronic device
To provide a semiconductor device with excellent electrical characteristics or a semiconductor device with stable electrical characteristics. A semiconductor device includes a first transistor, a second transistor, a first insulator, a second insulator, a first wiring, and a first plug. The first transistor includes silicon. The second transistor includes an oxide semiconductor. The first insulator is located over the first transistor. The second insulator is located over the first insulator. The second transistor is located over the second insulator. The first wiring is located over the second insulator and the first plug. The first transistor and the second transistor are electrically connected to each other through the first wiring and the first plug. The first wiring has low hydrogen permeability. The hydrogen permeability of the second insulator is lower than the hydrogen permeability of the first insulator. |
| US09653472B2 |
Semiconductor device, method of fabricating the semiconductor device, and method of forming epitaxial layer
According to example embodiments, a method of fabricating a semiconductor device includes alternately stacking interlayer insulating layers and intermediate layers on a substrate, forming openings passing through the interlayer insulating layers and the intermediate layers to form recessed regions in the substrate, forming first epitaxial layers on recessed surfaces in the recessed regions, and forming second epitaxial layers using the first epitaxial layers as seed layers. The second epitaxial layers fill the recessed regions and extend above the substrate. |
| US09653459B2 |
MOSFET having source region formed in a double wells region
A MOS transistor comprises a substrate of a first conductivity, a first region of the first conductivity formed over the substrate, a second region of the first conductivity formed in the first region, a first drain/source region of a second conductivity formed in the second region, a second drain/source region of the second conductivity and a body contact region of the first conductivity, wherein the body contact region and the first drain/source region are formed in an alternating manner from a top view. |
| US09653448B2 |
Electrostatic discharge (ESD) diode in FinFET technology
In an embodiment, an ESD protection circuit is provided in which diodes may be formed between N+ and P+ diffusions within an insulated semiconductor region and in which additional diodes may be formed between adjacent insulated regions of opposite conduction type as well. The diodes may be used in parallel to form an ESD protection circuit, which may have low on resistance and may sink high ESD current per unit area. To support the formation of the ESD protection circuit, each silicon region may have alternating N+ and P+ diffusions, and adjacent silicon regions may have N+ and P+ diffusions alternating in opposite locations. That is a perpendicular drawn between the N+ diffusions of one adjacent region may intersect P+ diffusions in the other adjacent region, and vice versa. |
| US09653446B1 |
Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, AACNT-short-configured, TS-short-configured, and AA-short-configured, NCEM-enabled fill cells
An IC includes logic cells, selected from a standard cell library, and fill cells, configured for compatibility with the standard logic cells. The fill cells contain structures configured to obtain in-line data via non-contact electrical measurements (“NCEM”). The IC includes such NCEM-enabled fill cells configured to enable detection and/or measurement of a variety of open-circuit and short-circuit failure modes, including at least one via-open-related failure mode, one AACNT-short-related failure mode, one TS-short-related failure mode, and one AA-short-related failure mode. |
| US09653438B2 |
Electrical interconnect structure for an embedded semiconductor device package and method of manufacturing thereof
An electronics package includes a first dielectric substrate having a first plurality of vias formed through a thickness thereof, a metalized contact layer coupled to a top surface of the first dielectric substrate, and a first die positioned within a first die opening formed through the thickness of the first dielectric substrate. Metalized interconnects are formed on a bottom surface of the first dielectric substrate and extend through the first plurality of vias to contact the metalized contact layer. A second dielectric substrate is coupled to the first dielectric substrate and has a second plurality of vias formed through a thickness thereof. Metalized interconnects extend through the second plurality of vias to contact the first plurality of metalized interconnects and contact pads of the first die. A first conductive element electrically couples the first die to the metalized contact layer. |
| US09653433B2 |
Multi-chip structure and method of forming same
A device comprises a first chip and a second chip stacked together to form a multi-chip structure, wherein the multi-chip structure is embedded in an encapsulation layer, and wherein at least one edge of the first chip and the second chip is exposed outside the encapsulation layer, a redistribution layer on a surface of a first side of the encapsulation layer and a plurality of conductive bumps over the redistribution layer and connected to the redistribution layer. |
| US09653429B2 |
Multi-chip package structure having blocking structure, wafer level chip package structure having blocking structure and manufacturing process thereof
A multi-chip package structure includes a first chip, at least one blocking structure, a plurality of first conductive bumps, a second chip, a plurality of second conductive bumps and an underfill. The first chip has a chip connecting zone, a plurality of first inner pads in the chip connecting zone and a plurality of first outer pads outside of the chip connecting zone. The blocking structure is disposed between the first inner pads and the first outer pads and surrounds the first inner pads. The first conductive bumps are disposed on the first outer pads. The second chip is flipped on the chip connecting zone and has a plurality of second pads. The second conductive bumps are disposed between the first inner pads and the second pads. The underfill is disposed between the first chip and the second chip so as to cover the second conductive bumps. |
| US09653426B2 |
Method of manufacturing a semiconductor package having an integrated microwave component
A method of manufacturing an array of semiconductor device packages includes placing a plurality of semiconductor chips on a temporary carrier, covering the plurality of semiconductor chips with an encapsulation material to form an encapsulation body, providing a plurality of microwave components each including at least one electrically conducting wall structure integrated in the encapsulation body, forming a plurality of electrical interconnects each configured to electrically couple a semiconductor chip and a microwave component, and separating the encapsulation body into single semiconductor device packages each including a semiconductor chip, a microwave component and an electrical interconnect. |
| US09653425B2 |
Anisotropic conductive film structures
Anisotropic conductive film (ACF) structures and manufacturing methods for forming the same are described. The manufacturing methods include preventing clusters of conductive particles from forming between adjacent bonding pads and that are associated with electrical shorting of ACF structures. In some embodiments, the methods involve use of multiple layered ACF materials that include a non-electrically conductive layer that reduces the likelihood of formation of conductive particle clusters between bonding pads. In some embodiment, the methods include the use of ultraviolet sensitive ACF material combined with lithography techniques that eliminate conductive particles from between neighboring bonding pads. In some embodiments, the methods involve the use of insulation spacers that block conductive particles from entering between bonding pads. Any suitable combination of the described methods can be used. |
| US09653424B2 |
Semiconductor package with adhesive material pre-printed on the lead frame and chip, and its manufacturing method
This invention discloses a semiconductor package with adhesive material pre-printed on the lead frame and chip, and the manufacturing method. The adhesive material is applied onto the chip carrier and the pin of the lead frame and also on the front electrode of the semiconductor chip via pre-printing. The back of the semiconductor chip is adhered on the chip carrier, and the front electrode of the semiconductor chip and the pin are connected respectively with a metal connector. The size, shape and thickness of the adhesive material are applied according to different application requirements according to size and shapes of the contact zone of the semiconductor chip and the metal connector. Particularly, the adhesive zones are formed by pre-printing the adhesive material thus significantly enhance the quality and performance of semiconductor products, and improves the productivity. |
| US09653423B2 |
Integrated circuit structure having dies with connectors
An embodiment is an integrated circuit structure including a first die having a bump structure, and a second die having a pad structure. The first die is attached to the second die by bonding the bump structure and the pad structure. The bump structure includes a metal pillar, a metal cap layer on the metal pillar, a metal insertion layer on the metal cap layer, and a solder layer on the metal insertion layer. The pad structure includes at least one of a nickel (Ni) layer, a palladium (Pd) layer or a gold (Au) layer. |
| US09653422B2 |
Chip package and method for forming the same
A method for forming a chip package is provided. The method includes providing a first substrate and a second substrate. The first substrate is attached onto the second substrate by an adhesive layer. A first opening is formed to penetrate the first substrate and the adhesive layer and separate the first substrate and the adhesive layer into portions. A chip package formed by the method is also provided. |
| US09653418B2 |
Packaging devices and methods
A method of manufacturing a packaging device may include: forming a plurality of through-substrate vias (TSVs) in a substrate, wherein each of the plurality of TSVs has a protruding portion extending away from a major surface of the substrate. A seed layer may be forming over the protruding portions of the plurality of TSVs, and a conductive ball may be coupled to the seed layer and the protruding portion of each of the plurality of TSVs. The seed layer and the protruding portion of each of the plurality of TSVs may extend into an interior region of the conductive ball. |
| US09653413B2 |
Power grid conductor placement within an integrated circuit
An integrated circuit 2 is formed with standard-cell power conductors 14 which are overlaid by power grid conductors 20. The power grid conductors are offset in a direction transverse to the longitudinal axis of the power grid conductors relative to their underlying standard-cell power conductor. This has the effect of increasing the conductor spacing possible to one side of the power grid conductor. Accordingly, a wider than minimum width power grid conductor may be provided which blocks only one of its adjacent track positions from being used by a routing conductor 22. |
| US09653412B1 |
Method of manufacturing semiconductor device
On a first wafer surface of a semiconductor wafer, a projection-depression shape is formed. On the first wafer surface, a resin member is so formed to have a resin outer peripheral end positioned away from a wafer outer peripheral end and expose the wafer outer peripheral end. By partially removing the semiconductor wafer, on a second wafer surface of the semiconductor wafer, formed is a recessed shape having a recessed-portion outer peripheral end positioned 0.5 mm or more inside from the resin outer peripheral end. After performing a processing on the second wafer surface, the resin member is removed. |
| US09653410B1 |
Transistor with shield structure, packaged device, and method of manufacture
A transistor includes a semiconductor substrate having an intrinsic active device, a first terminal, and a second terminal. The transistor also includes an interconnect structure formed of multiple layers of dielectric material and electrically conductive material on an upper surface of the semiconductor substrate. The interconnect structure includes a pillar, a tap interconnect, and a shield structure formed from the electrically conductive material. The pillar electrically contacts the first terminal, extends through the dielectric material, and connects to a first runner. The tap interconnect electrically contacts the second terminal, extends through the dielectric material, and connects to a second runner. The shield structure extends from a shield runner through the dielectric material toward the semiconductor substrate. The shield structure is positioned between the pillar and the tap interconnect to limit feedback capacitance between the tap interconnect and the pillar. |
| US09653409B2 |
Semiconductor package having a metal paint layer
Disclosed are devices and methods related to a conductive paint layer configured to provide radio-frequency (RF) shielding for a packaged semiconductor module. Such a module can include a packaging substrate, one or more RF components mounted on the packaging substrate, a ground plane disposed within the packaging substrate, and a plurality of RF-shielding wirebonds disposed on the packaging substrate and electrically connected to the ground plane. The module can further include an overmold structure formed over the packaging substrate and dimensioned to substantially encapsulate the RF component(s) and the RF-shielding wirebonds. The overmold structure can define an upper surface that exposes upper portions of the RF-shielding wirebonds. The module can further include a conductive paint layer having silver flakes disposed on the upper surface of the overmold structure so that the conductive paint layer, the RF-shielding wirebonds, and the ground plane form an RF-shield for the RF component(s). |
| US09653406B2 |
Conductive traces in semiconductor devices and methods of forming same
An embodiment device package includes a semiconductor device die comprising a passivation layer at a top surface, a first conductive line over the passivation layer and electrically connected to the device die, and a second conductive line over the passivation layer and electrically connected to the device die. The first conductive line is thicker than the second conductive line, and the first conductive line and the second conductive line are formed in a same device package layer. |
| US09653402B2 |
Semiconductor device and method for fabricating the same
A semiconductor device and a method of fabricating the same, the semiconductor device including a fin structure, a first liner, a first insulating layer and a dummy gate structure. The fin structure is disposed on a substrate, where the fin structure has a trench. The first liner disposed in the trench. The first insulating layer disposed on the first liner. The dummy gate structure is disposed on the first insulating layer and disposed above the trench, where a bottom surface of the dummy gate and a top surface of the fin structure are on a same level. |
| US09653400B2 |
Semiconductor device and method of manufacturing the same
A semiconductor device is provided. The semiconductor device includes a first porous interlayer insulating film having a low dielectric constant and including a first region and a second region, a second interlayer insulating film formed on the first interlayer insulating film in the first region, a plurality of first conductive patterns formed in the second interlayer insulating film such that the plurality of first conductive patterns are spaced apart from each other, at least one second conductive pattern formed in the first interlayer insulating film in the second region and air gaps disposed at lateral sides of the plurality of first conductive patterns. |
| US09653399B2 |
Middle-of-line integration methods and semiconductor devices
An electronic device includes a middle-of-line (MOL) stack. The electronic device includes a top local interconnect layer and a contact coupling the top local interconnect layer to a gate of a semiconductor device through a first dielectric layer. The electronic device also includes one or more isolation walls between the contact and the first dielectric layer, wherein the one or more isolation walls include aluminum nitride (AlN). |
| US09653397B2 |
Semiconductor package and method of manufacturing the same
Disclosed herein are a semiconductor package and a method of manufacturing the same, which allows a conductive path to be provided to connect upper and lower portions of the semiconductor package. A semiconductor package according to the present invention includes a semiconductor chip, a substrate including an accommodating portion to accommodate the semiconductor chip, a sealing material configured to mold the semiconductor chip and the substrate to be integrated, a through wiring configured to vertically pass through the substrate, a wiring portion configured to electrically connect the semiconductor chip and one side of the through wiring, and an external connection portion to electrically connected to the other side of the through wiring and configured to be able to be electrically connected to an outside, wherein a wiring layer of the wiring portion is provided to be connected to the through wiring. |
| US09653394B2 |
Logic cell, semiconductor device including logic cell, and method of manufacturing the logic cell and semiconductor device
A semiconductor device includes a substrate; a plurality of conductive areas formed on the substrate at a first vertical level; a first wiring layer formed on the substrate at a second vertical level which is higher than the first vertical level, the first wiring layer including first lines that extend in a first direction, one first line of the first lines connected to a first conductive area selected from the plurality of conductive areas through a via contact; a second wiring layer formed on the substrate at a third vertical level which is higher than the second vertical level, the second wiring layer including second lines that extend in a second direction that crosses the first direction, one second line of the second lines connected to a second conductive area selected from the plurality of conductive areas; and a deep via contact spaced apart from lines of the first wiring layer in a horizontal direction and extending from the second conductive area to the one second line. |
| US09653390B2 |
Semiconductor device and semiconductor device manufacturing method
A semiconductor device of the present invention includes a semiconductor element, a surface electrode formed on a surface of the semiconductor element, a metal film formed on the surface electrode so as to have a joining portion and a stress relieving portion formed so as to border on and surround the joining portion, solder joined to the joining portion while avoiding the stress relieving portion, and an external electrode joined to the joining portion through the solder. |
| US09653389B2 |
High efficiency module
A module (1) includes a first functional device (2) and a second functional device (3). The first functional device (2) includes a base electrode, an emitter electrode and a collector electrode. The second functional device (3) includes at least one electrode. The module (1) further includes a conductive frame (4). One of the base electrode, the emitter electrode, and the collector electrode of the first functional device (2) is directly connected to the frame (4). The electrode of the second functional device (3) is also directly connected to the frame (4). The frame (4) includes a portion serving as a terminal for external connection. |
| US09653388B2 |
Integrating multi-output power converters having vertically stacked semiconductor chips
A electronic multi-output device having a substrate including a pad and pins. A composite first chip has a first and a second transistor integrated so that the first terminals of the transistors are merged into a common terminal on one chip surface. Patterned second and third terminals are on the opposite chip surface. The common first terminal is attached to the substrate pad. The second terminals are connected by discrete first and second metal clips to respective substrate pins. A composite second chip has a third and a fourth transistor integrated so that the second terminals of the transistors are merged into a common terminal on one chip surface. Patterned first and third terminals are on the opposite chip surface. The second chip is flipped to be vertically attached with its first terminals to the first and second clips, respectively. The third terminals are connected by discrete clips to respective substrate pins. The common second terminal is connected by a common clip to a substrate pin. |
| US09653387B2 |
Semiconductor component and method of manufacture
In accordance with an embodiment, a semiconductor component includes a support having a first device receiving structure, a second device receiving structure, a first lead, a second lead, and a third lead. A first semiconductor chip is coupled to the first device receiving structure and a second semiconductor chip is coupled to the first semiconductor chip and the second device receiving structure. The first semiconductor chip is configured from a silicon semiconductor material and has a gate bond pad, a source bond pad, and a drain bond pad, and the second semiconductor chip is configured from a gallium nitride semiconductor chip and has a gate bond pad, a source bond pad, and a drain bond pad. In accordance with another embodiment, a method for manufacturing a semiconductor component includes coupling a first semiconductor chip to a support and coupling a second semiconductor chip to the support. |
| US09653380B2 |
Method for manufacturing component built-in substrate
A substrate is disclosed, which can remove heat from a stacked body of semiconductor elements through a phase change of a coolant. The substrate of the application includes: a stacked body of semiconductor elements; a first channel forming a path, receiving circulation of a first coolant, in a surface of the stacked body; and a second channel forming a path, receiving circulation of a second coolant having a boiling point higher than the boiling point of the first coolant, in an inter-layer portion of the stacked body. |
| US09653376B1 |
Heat dissipation package structure
A heat dissipation package structure includes a substrate, a chip disposed on the substrate and a heat dissipation sheet. The heat dissipation sheet comprises a covering portion disposed on a back surface of the chip, a first lateral covering portion disposed on a first lateral surface of the chip and a first conducting portion disposed on the substrate. The back surface comprises a first width, the covering portion comprises a second width, the chip comprises a thickness, and there is an interval between the chip and the substrate. The second width is not larger than summation of the first width, double the interval and double the thickness for making the chip disposed between the heat dissipation sheet and the substrate is not within a completely sealed space so as to prevent the heat dissipation sheet from deformation and separation from the chip or the substrate cause of air expansion. |
| US09653374B2 |
3DIC package comprising perforated foil sheet
A structure includes a thermal interface material, and a Perforated Foil Sheet (PFS) including through-openings therein, with a first portion of the PFS embedded in the thermal interface material. An upper layer of the thermal interface material is overlying the PFS, and a lower layer of thermal interface material is underlying the PFS. The thermal interface material fills through-openings in the PFS. |
| US09653373B2 |
Semiconductor package including heat spreader and method for manufacturing the same
A semiconductor package includes a semiconductor chip on a package substrate, a heat spreader on the semiconductor chip, a molding layer, an adhesive film between the semiconductor chip and the heat spreader, and a through-hole passing through the heat spreader. The heat spreader includes a first surface and a second surface. The molding layer covers sidewalls of the semiconductor chip and the heat spreader and exposes the first surface of the heat spreader. The adhesive film is on the second surface of the heat spreader. |
| US09653371B2 |
Underfill material and method for manufacturing semiconductor device using the same
An underfill material enabling voidless packaging and excellent solder bonding properties, and a method for manufacturing a semiconductor device using the same are provided. An underfill material is used which contains an epoxy resin and a curing agent, and a time for a reaction rate to reach 20% at 240° C. calculated by Ozawa method using a differential scanning calorimeter is 2.0 sec or less and a time for the reaction rate to reach 60% is 3.0 sec or more. This enables voidless packaging and excellent solder connection properties. |
| US09653369B2 |
Power semiconductor module comprising a case, base plate, and spacer
It is an object to provide a power semiconductor module having a case shared for base plates of different sizes and having a high-stability base plate. The power semiconductor module according to the present invention includes: a base plate; an insulating substrate disposed on a first main surface of the base plate; a semiconductor chip disposed on an insulating substrate; a case for enclosing the base plate except a second main surface of the base plate facing the first main surface, the insulating substrate, and the semiconductor chip; and a spacer provided between the outer periphery of the base plate and the inner periphery of the case and in contact with both. The spacer has a bonding surface with a side surface of the base plate and the first main surface in the contact with the outer periphery of the base plate. |
| US09653368B2 |
Display device and method of fabricating the same
A display device includes a display area, a test pad, a plurality of first test transistors, and at least one outline. The display area includes pixels coupled to data lines and scan lines. The test pad receives a test signal. The first test transistors are coupled between the data lines of the display area and the test pad. The at least one outline is coupled between one of the first test transistors and the test pad. The at least one outline is located in a non-display area outside the display area. |
| US09653367B2 |
Methods including a processing of wafers and spin coating tool
A method includes performing a spin coating process. In the spin coating process, a first fluid is dispensed to a surface of a wafer. The method further includes performing an inspection of an edge area of the wafer. On the basis of the inspection of the edge area of the wafer, a defect analysis is performed. In the defect analysis, it is determined if the edge area of the wafer has a defect that is indicative of an insufficient coating of the surface of the wafer by the first fluid. |
| US09653366B2 |
Method of dividing wafer
Disclosed herein is a method of dividing a wafer including an exposed area incising step of lowering a cutting blade to a preset lowered position for fully severing the wafer to cause the cutting blade to incise an exposed area of a wafer unit, an image capturing step of capturing an image of the exposed area which the cutting blade has incised in the exposed area incising step, with image capturing means, a determining step of determining whether or not it is possible to fully sever the wafer on the basis of the captured image in the image capturing step, and an adjusting step of increasing a distance by which to lower the cutting blade if it is determined that it is impossible to fully sever the wafer in the determining step. |
| US09653365B1 |
Methods for fabricating integrated circuits with low, medium, and/or high voltage transistors on an extremely thin silicon-on-insulator substrate
A method for fabricating an integrated circuit that include providing or obtaining an extremely thin silicon-on-insulator (ETSOI) substrate, dividing the ETSOI substrate into a low voltage field effect transistor (FET) region and one or both of a medium voltage FET region and a high voltage FET regions, and forming a low voltage FET within the low voltage FET regions and forming a medium and/or high voltage FET within the medium and/or high voltage FET region(s). Channel, source, and drain structures of the low voltage FET are formed in an upper silicon layer that is disposed above a buried oxide layer of the ETSOI substrate, whereas channel, source, and drain structures of the medium and/or high voltage FETs are formed at least partially below the upper silicon layer. |
| US09653364B1 |
FinFET device and method of forming the same
Provided is a FinFET device including a substrate having at least one fin, first and second gate stacks, first and second strained layers, first and second dielectric layers, and first and second connectors. The first and second gate stacks are across the fin. The first and second strained layers are respectively aside the first and second gate stacks. The first and second dielectric layer are respectively over the first and second strained layers, and the top surface of the first dielectric layer is lower than the top surface of the second dielectric layer. The first connector is through the first dielectric layer and is electrically connected to the first strained layer. The second connector is through the second dielectric layer and is electrically connected to the second strained layer. Besides, the width of the second connector is greater than the width of the first connector. |
| US09653363B2 |
Methods of fabricating FinFET semiconductor devices including dummy structures
Provided are a semiconductor device and a method of fabricating a semiconductor device. The semiconductor device includes a first active fin and a second active fin which protrude from a substrate and extend along a first direction, a first gate structure which is on the first active fin to extend along a second direction intersecting the first direction, a second gate structure which is located adjacent to the first gate structure in the second direction and is on the second active fin to extend along the second direction, and a dummy structure which is in a space between the first gate structure and the second gate structure. |
| US09653360B2 |
Vertical field effect transistors
Vertical field effect transistors (FETs) with minimum pitch and methods of manufacture are disclosed. The structure includes at least one vertical fin structure and gate material contacting with the at least one vertical fin structure. The structure further includes metal material in electrical contact with the ends of the at least one vertical fin. |
| US09653355B2 |
Flip chip package structure and fabrication process thereof
Disclosed herein are various chip packaging structures and methods of fabrication. In one embodiment, a flip chip package structure can include: (i) a pad on a chip; (ii) an isolation layer on the chip and the pad, where the isolation layer includes a through hole that exposes a portion of an upper surface of the pad; (iii) a metal layer on the pad, where the metal layer fully covers the exposed upper surface portion of the pad; and (iv) a bump on the metal layer, where side edges of the bump do not make contact with the isolation layer. |
| US09653354B2 |
Metal wiring layer forming method, metal wiring layer forming apparatus, and recording medium
A metal wiring layer can be formed within a recess of a substrate while suppressing the metal wiring layer from being formed at the outside of the recess. A metal wiring layer forming method includes forming a catalyst layer 5 formed of Pd on a tungsten layer W on a bottom surface 3a of the recess 3 of the substrate 2 without forming the catalyst layer 5 on a surface 3b of an insulating layer of the recess 3; and forming a Ni-based metal wiring layer 7 on the catalyst layer 5 of the recess 3. |
| US09653353B2 |
Tungsten feature fill
Described herein are methods of filling features with tungsten and related systems and apparatus. The methods include inside-out fill techniques as well as conformal deposition in features. Inside-out fill techniques can include selective deposition on etched tungsten layers in features. Conformal and non-conformal etch techniques can be used according to various implementations. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) word lines. Examples of applications include logic and memory contact fill, DRAM buried word line fill, vertically integrated memory gate/word line fill, and 3-D integration with through-silicon vias (TSVs). |
| US09653351B2 |
Method of manufacturing semiconductor device
A method of manufacturing a semiconductor device may include: (a) loading a substrate into a process chamber, the substrate having: a process surface provided with a first metal film containing at least a first metal element; (b) forming a second metal film on the substrate loaded in the process chamber by alternately supplying a metal compound and a first reactive gas reactive with the metal compound to the substrate a plurality of times; (c) alternately performing steps (c-1) and (c-2) a plurality of times wherein the step (c-1) includes: forming an amorphous third metal film on the second metal film, and the step (c-2) includes: forming a fourth metal film on the third metal film; and (d) forming an amorphous fifth metal film on the fourth metal film by supplying the metal compound mixed with the second reactive gas to the substrate. |
| US09653350B2 |
Pre-treatment method for plating and storage medium
Catalytic metal nanoparticles can be attached on a base. A pre-treatment method for plating includes a catalytic particle-containing film forming process of forming a catalytic particle-containing film on a surface of a substrate by supplying, onto the substrate, a catalytic particle solution which is prepared by dispersing the catalytic metal nanoparticles and a dispersing agent in a solvent containing water; a first heating process of removing moisture contained at least in the catalytic particle-containing film by heating the substrate to a first temperature; and a second heating process of polymerizing the dispersing agent to have a sheet shape by heating the substrate to a second temperature higher than the first temperature after the first heating process and fixing the catalytic metal nanoparticles on a base layer by covering the catalytic metal nanoparticles with the sheet-shaped dispersing agent. |
| US09653347B1 |
Vertical air gap subtractive etch back end metal
After forming source/drain contact structures within an interlevel dielectric (ILD) layer to contact source/drain regions of a field effect transistor (FET), the ILD layer is recessed to expose upper portions of the source/drain contact structures. A sacrificial layer is then formed on a remaining portion of the ILD layer to laterally surround the upper portions of the source/drain contact structures. An interconnect conductor portion is subsequently formed to contact the source/drain contact structures by subtractive patterning of a metal layer that is formed on the sacrificial layer. Next, the sacrificial layer is removed, leaving a void between the interconnect conductor portion and the remaining portion of the ILD layer. A interconnect liner layer is then formed on a top surface and sidewalls of the interconnect conductor portion and on the remaining portion of the ILD layer. The interconnect liner layer encloses an air gap surrounding the upper portions of the source/drain contact structures. |
| US09653342B2 |
Trench having thick dielectric selectively on bottom portion
A method of fabricating a semiconductor device includes etching a semiconductor substrate having a top surface to form a trench having sidewalls and a bottom surface that extends from the top surface into the semiconductor substrate. A dielectric liner of a first dielectric material is formed on the bottom surface and sidewalls of the trench to line the trench. A second dielectric layer of a second dielectric material is deposited to at least partially fill the trench. The second dielectric layer is partially etched to selectively remove the second dielectric layer from an upper portion of the trench while preserving the second dielectric layer on a lower portion of the trench. The trench is filled with a fill material which provides an electrical conductivity that is at least that of a semiconductor. |
| US09653338B2 |
System and method for non-contact wafer chucking
A non-contact wafer chucking apparatus includes a wafer chuck and a gripper assembly coupled to a portion of the wafer chuck. The wafer chuck includes pressurized gas elements configured to generate pressurized gas regions across a surface of the wafer chuck suitable for elevating the wafer above the surface of the wafer chuck. The wafer chuck further includes vacuum elements configured to generate reduced pressure regions across the surface of the wafer chuck having a pressure lower than the pressurized gas regions. The reduced pressure regions are suitable for securing the wafer above the wafer chuck without contact to the wafer chuck. The chucking apparatus includes a rotational drive unit configured to selectively rotate the wafer chuck. The gripper elements are reversibly couplable to an edge portion of the wafer so as to secure the wafer such that the wafer and gripper assembly rotate synchronously with the wafer chuck. |
| US09653334B2 |
Plasma processing apparatus and method
A plasma processing apparatus includes a processing chamber, a plasma source that generates plasma within the processing chamber, a transfer carrier that has a holding sheet and a frame, the holding sheet holding a substrate, and the frame being attached to the holding sheet so as to surround the substrate, a stage that is provided within the processing chamber and has a gas supply hole formed in a mounting area of the stage for mounting the transfer carrier thereon, an electrostatic chucking part that is provided within the stage and electrostatically attracts the transfer carrier, and a gas supply part that supplies gas through the gas supply hole of the stage to assist separation of the transfer carrier from the stage. |
| US09653333B2 |
Method of manufacturing lighting emitting device with aligned-bonding
A method of manufacturing a light-emitting device comprises the steps of: providing a semiconductor light-emitting stack having a first connecting surface and a first alignment pattern; providing a substrate having a second connecting surface and a second alignment pattern; detecting the position of the first alignment pattern and the position of the second alignment pattern; and moving at least one of the substrate and the semiconductor light-emitting stack to make the first alignment pattern be aligned with the second alignment pattern. |
| US09653332B1 |
Wafer probe holder for planarity and orientation adjustment
A compact device allows individual or combined correction of wafer probe planarity and orientation misalignment. The device is made as a metallic block or as a strong plastic block and contains three sections, which are held together by a steel blade or by a steel blade and a rotation pin; the sections are split apart for “Phi”—orientation alignment or rotated against each-other for “Theta” planarity alignment. The steel blade provides secure and anti-backlash flexibility both in lateral (“Phi”) and perpendicular (“Theta”) direction. Alternatively the “Theta” alignment can use a rotation shaft or a small part of the original block left over as a bridge joining both sections. The device is inserted between the fixed probe support and the probe itself. |
| US09653318B2 |
Directional SiO2 etch using plasma pre-treatment and high-temperature etchant deposition
Methods for processing a substrate are described herein. Methods can include positioning a substrate with an exposed surface comprising a silicon oxide layer in a processing chamber, biasing the substrate, treating the substrate to roughen a portion of the silicon oxide layer, heating the substrate to a first temperature, exposing the exposed surface of the substrate to ammonium fluoride to form one or more volatile products while maintaining the first temperature, and heating the substrate to a second temperature, which is higher than the first temperature, to sublimate the volatile products. |
| US09653316B2 |
Plasma processing method and plasma processing apparatus
Disclosed is a plasma processing method which includes a gas supplying process, a power supplying process, and an etching process. In the gas supplying process, a processing gas is supplied into a processing container in which an object to be processed is disposed. In the power supplying process, a plasma generating power of a frequency ranging from about 100 MHz to about 150 MHz as a power for generating plasma of the processing gas supplied into the processing container, and a biasing power which is a power having a frequency lower than that of the plasma generating power are supplied. In the etching process, the object to be processed is etched by the plasma of the processing gas while the biasing power is pulse-modulated so that the duty ratio ranges from about 10% to about 70% and the frequency ranges from about 5 kHz to about 20 kHz. |
| US09653313B2 |
Stress relieving semiconductor layer
A semiconductor structure, such as a group III nitride-based semiconductor structure is provided. The semiconductor structure includes a cavity containing semiconductor layer. The cavity containing semiconductor layer can have a thickness greater than two monolayers and a multiple cavities. The cavities can have a characteristic size of at least one nanometer and a characteristic separation of at least five nanometers. |
| US09653310B1 |
Methods for selective etching of a silicon material
The present disclosure provides methods for etching features in a silicon material includes performing a remote plasma process formed from an etching gas mixture including chlorine containing gas to remove a silicon material disposed on a substrate. |
| US09653305B2 |
Semiconductor component with field electrode between adjacent semiconductor fins and method for producing such a semiconductor component
A semiconductor component includes semiconductor fins formed between a base plane and a main surface of a semiconductor body. Each semiconductor fin includes a source region formed between the main surface and a channel/body region, and a drift zone formed between the channel/body region and the base plane. The semiconductor component further includes gate electrode structures on two mutually opposite sides of each channel/body region, and a field electrode structure between mutually adjacent ones of the semiconductor fins. Each field electrode structure is separated from the drift zone by a field dielectric and extends from the main surface as far as the base plane. The gate electrode structures assigned to the mutually adjacent semiconductor fins enclose an upper portion of the corresponding field electrode structure from two sides. |
| US09653299B2 |
Semiconductor device producing method
A first laser pulse emitted from a semiconductor laser oscillator and having a first pulse width is entered onto a second surface of a semiconductor substrate in which a semiconductor device is formed on a first surface and dopants are added to a surface layer portion on the second surface side. A second laser pulse having a second pulse width less than or equal to 1/10 of the first pulse width is entered on an incident area of the first laser pulse in an overlapping manner. The relative positional relationship on a time axis between falling time of the first laser pulse and rising time of the first laser pulse is set such that the temperature of the first surface, which rises due to the incidence of the first laser pulse and the second laser pulse, does not exceed an allowable upper limit value which is predetermined. |
| US09653293B2 |
Semiconductor device manufacturing method and semiconductor device manufacturing apparatus
A manufacturing a semiconductor device of the present disclosure includes coating a photosensitive material on a workpiece; exposing the photosensitive material using a first exposure mask; performing a positive-tone development on the photosensitive material using a first developer after the first exposing; exposing the photosensitive material using a second exposure mask after the first developing; and performing a negative-tone development on the photosensitive material using a second developer after the second exposing. |
| US09653292B2 |
Method of manufacturing thin film transistor substrate, method of manufacturing display apparatus, thin film transistor substrate, and display apparatus
A method of manufacturing a thin film transistor substrate includes forming an amorphous silicon layer on a substrate, the substrate having a rectangular shape, and irradiating the amorphous silicon layer with a laser beam at a random pitch, such that the amorphous silicon layer is crystallizes into a polycrystalline silicon layer, wherein the laser beam has a major axis and a minor axis, the major axis being non-parallel with respect to sides of the substrate. |
| US09653291B2 |
Method for removing native oxide and residue from a III-V group containing surface
Native oxides and residue are removed from surfaces of a substrate by performing a multiple-stage native oxide cleaning process. In one example, the method for removing native oxides from a substrate includes supplying a first gas mixture including an inert gas onto a surface of a material layer disposed on a substrate into a first processing chamber, wherein the material layer is a III-V group containing layer for a first period of time, supplying a second gas mixture including an inert gas and a hydrogen containing gas onto the surface of the material layer for a second period of time, and supplying a third gas mixture including a hydrogen containing gas to the surface of the material layer while maintaining the substrate at a temperature less than 550 degrees Celsius. |
| US09653289B1 |
Fabrication of nano-sheet transistors with different threshold voltages
A method of forming two or more nano-sheet devices with varying electrical gate lengths, including, forming at least two cut-stacks including a plurality of sacrificial release layers and at least one alternating nano-sheet channel layer on a substrate, removing a portion of the plurality of sacrificial release layers to form indentations having an indentation depth in the plurality of sacrificial release layers, and removing a portion of the at least one alternating nano-sheet channel layer to form a recess having a recess depth in the at least one alternating nano-sheet channel layers, where the recess depth is greater than the indentation depth. |
| US09653286B2 |
Gallium nitride nanowire based electronics
GaN based nanowires are used to grow high quality, discreet base elements with c-plane top surface for fabrication of various semiconductor devices, such as diodes and transistors for power electronics. |
| US09653284B2 |
Thin film transistor, manufacturing method thereof and array substrate
A thin film transistor, a manufacturing method thereof and an array substrate are provided. The thin film transistor comprises: a gate electrode (11), a source electrode (15) and a drain electrode (16), and the thin film transistor further comprises a buffer layer (11) which is directly provided at one side or both sides of at least one of the gate electrode (11), the source electrode (15) and the drain electrode (16), wherein, the buffer layer (11) and at least one of the gate electrode (11), the source electrode (15) and the drain electrode (16) directly contacting the buffer layer (11) are conformal. Therefore, the adhesion between an electrode of the thin film transistor and a film layer contacting it is improved and at the same time an atom in the electrode of the thin film transistor is effectively prevented from diffusing to the film layer connected with it, and the reliability of the thin film transistor is improved and the production cost is reduced. |
| US09653281B2 |
Structure and method for tunable memory cells including fin field effect transistors
In a particular aspect, an integrated circuit includes a first gate structure coupled to a first fin field effect transistor (FinFET) device. The integrated circuit includes a second gate structure coupled to a second FinFET device. The first gate structure and the second gate structure are separated by a dielectric region. The integrated circuit further includes a metal contact having a first surface that is in contact with the dielectric region, the first gate structure, and the second gate structure. |
| US09653276B2 |
Enhanced spray formation for liquid samples
Methods and systems for generating ions from a liquid sample for mass spectrometry are provided herein. In various aspects, the methods and systems can enhance the break-up of a jet of the liquid sample upon injection into an ionization chamber. In some aspects, methods and systems perturb the liquid sample prior to discharge to increase the internal energy of the sample so as to enhance the formation of liquid droplets when the liquid sample is injected into the ionization chamber. |
| US09653274B2 |
Assemblies for ion and electron sources and methods of use
Certain embodiments described herein are directed to devices that can be used to align the components of a source assembly in a source housing. In some examples, a terminal lens configured to couple to the housing through respective alignment features can be used to retain the source components in a source housing to provide a source assembly. |
| US09653273B2 |
Ion optical elements
Ion optics devices and related methods of making and using the same are disclosed herein that generally involve forming a plurality of electrode structures on a single substrate. An aspect ratio of the structures relative to a plurality of recesses which separate the structures can be selected so as to substantially prevent ions passing through the finished device from contacting exposed, electrically-insulating portions of the substrate. The substrate material can be a material that is relatively inexpensive and easy to machine into complex shapes with high precision (e.g., a printed circuit board material). In some embodiments, discrete ion optical elements are disclosed which can be formed from a core material to which an electrically-conductive coating is applied, the core material being relatively inexpensive and easy to machine with high precision. The coating can be configured to substantially prevent outgassing from the core under the vacuum conditions typically experienced in a mass spectrometer. |
| US09653272B2 |
Mass-spectral method for selection, and de-selection, of cancer patients for treatment with immune response generating therapies
A method and system for predicting in advance of treatment whether a cancer patient is likely, or not likely, to obtain benefit from administration of a yeast-based immune response generating therapy, which may be yeast-based immunotherapy for mutated Ras-based cancer, alone or in combination with another anti-cancer therapy. The method uses mass spectrometry of a blood-derived patient sample and a computer configured as a classifier using a training set of class-labeled spectra from other cancer patients that either benefitted or did not benefit from an immune response generating therapy alone or in combination with another anti-cancer therapy. Also disclosed are methods of treatment of a cancer patient, comprising administering a yeast-based immune response generating therapy, which may be yeast-based immunotherapy for mutated Ras-based cancer, to a patient selected by a test in accordance with predictive mass spectral methods disclosed herein, in which the class label for the spectra indicates the patient is likely to benefit from the yeast-based immunotherapy. |
| US09653271B2 |
Methods and apparatus for performing mass spectrometry
The present disclosure relates, in part, to MS apparatus, methods, and/or software, having improved selectivity, sensitivity, specificity, resolution, mass accuracy and dynamic range over conventional MS technologies. In particular, the technology relates to apparatus, methods, and/or software wherein a combination of in-source fragmentation, ion mobility separation, and/or time-aligned parallel (TAP) sample ion fragmentations are utilized in mass spectrometry for the analysis of samples. |
| US09653266B2 |
Microwave plasma applicator with improved power uniformity
An apparatus for generating plasma includes a plasma discharge tube and a conductive coil helically wound around an outer surface of the plasma discharge tube. A waveguide is coupled to a microwave cavity surrounding the plasma discharge tube to guide the microwave energy into the plasma discharge tube such that the plasma is generated in the plasma discharge tube. The waveguide is positioned such that an electric field of the microwave energy is oriented at a predetermined angle with respect to the longitudinal axis of the plasma discharge tube. A resulting induced electric current in the conductive coil affects power absorption in the plasma discharge tube, the predetermined angle being selectable such that power absorption in the plasma discharge tube is according to a predetermined profile with respect to the longitudinal axis of the plasma discharge tube. |
| US09653264B2 |
Inductively coupled plasma source for plasma processing
Plasma processing apparatus and methods are disclosed. Embodiments of the present disclosure include a processing chamber having an interior space operable to receive a process gas, a substrate holder in the interior of the processing chamber operable to hold a substrate, and at least one dielectric window. A metal shield is disposed adjacent the dielectric window. The metal shield can have a peripheral portion and a central portion. The processing apparatus includes a primary inductive element disposed external to the processing chamber adjacent the peripheral portion of the metal shield. The processing apparatus can further include a secondary inductive element disposed between the central portion of the metal shield and the dielectric window. The primary and secondary inductive elements can perform different functions, can have different structural configurations, and can be operated at different frequencies. |
| US09653250B2 |
X-ray source
An X-ray source with optical indication of radiation, which can be used in various measuring devices for parameters control and visualization of structure of industrial and biological objects, is proposed. The source comprises a vacuum housing, an anode irradiated by electrons and generating the divergent flux of radiation, an exit window for X-ray radiation, means for optical indication of X-ray radiation beam including a source of optical radiation and an optical mirror. The anode is made composite in the form of a thin film and a radiolucent substrate luminescent in the optical range. The anode structure is an exit window of the source, and behind it the coaxially arranged means of collimation and focusing of X-ray and optical radiation and means of optical visualization of X-ray focus are mounted. The proposed device significantly increases the accuracy and informativity of optical indication of X-ray radiation parameters. |
| US09653249B2 |
Transmission type target, radiation generating tube having the transmission type target, radiation generator having the radiation generating tube, and radiation imaging apparatus having the radiation generator
The present invention relates to a transmission type target having a diamond base material as the transmissive base material. The transmission type target includes a target layer containing a metal carbide constituted of at least one metal selected from the group consisting of molybdenum, tantalum, and tungsten and carbon; and a diamond base material supporting the target layer. The transmission type target inhibits the composition of the target layer from varying with the drive history of the transmission type target and inhibits the output of radiation from varying over a long time. |
| US09653247B2 |
X-ray apparatus and a CT device having the same
A two dimensional array distributed x-ray apparatus of this disclosure includes: a vacuum box which is sealed at its periphery, where the interior thereof is high vacuum; a plurality of electron transmitting units arranged in one plane in a two dimensional array on the wall of the vacuum box; an anode having targets corresponding to the plurality electron transmitting unit arranged in parallel with the plane of the plurality of electron transmitting units in the vacuum box; a power supply and control system having a high voltage power supply connected to the anode, a filament power supply connected to each of the plurality of the electron transmitting units, and a grid-controlled apparatus connected to each of the plurality of electron transmitting units; and a control system for controlling each power supply. |
| US09653237B1 |
Electrical switching apparatus and slot motor therefor
A slot motor is for an electrical switching apparatus. The slot motor includes: a support apparatus including a support element having a first leg and a second leg located opposite the first leg, the first leg having a first inner surface, the second leg having a second inner surface facing the first inner surface; a plurality of permanent magnets including a first permanent magnet and a second permanent magnet, the first permanent magnet being located on the first leg, the second permanent magnet being located on the second leg; and a number of U-shaped plates coupled to the support element. The first inner surface and the second inner surface are located between the first permanent magnet and the second permanent magnet. |
| US09653236B2 |
Electromagnetic relay
An electromagnetic relay which is improved in arc blocking performance without being increased in size is desired. An electromagnetic relay according to the present invention is provided with a fixed contact, a moving contact which is movable respect to the fixed contact, a pair of magnets which is arranged at the side of the fixed contact and the moving contact so that pole faces with mutually reversed polarity are separated from and face each other and a pair of arc cooling plates which is arranged in a spaces between the magnets and which has first surfaces which face each other across a gap and second surfaces which face a pole face of either of the magnets, respectively. |
| US09653231B2 |
Luminous keyboard
A luminous keyboard includes a lateral-emitting type illumination element, a light guide panel, a sensing circuit pattern, a light-transmissible substrate, a supporting plate, and plural keys. When one of the keys is moved toward the sensing circuit pattern, the sensing circuit pattern generates a corresponding non-contact key signal. The lateral-emitting type illumination element is used for providing a light beam to the light guide panel. Consequently, the light beam can be diffused to the whole light guide panel. The light guide panel has plural light-guiding dots for collecting and scattering the light beam. The light-transmissible substrate is arranged between the light guide panel and the plural keys, and has plural light diffusion structures corresponding to the plural keys. The light beam scattered upwardly by each light-guiding dot is sequentially transmitted through the corresponding light diffusion structure and the supporting plate and directed to the corresponding key. |
| US09653228B2 |
Cosmetic dome switch
The systems and methods described herein are directed to a switch for use in an electronic device. The switching assembly may include an elastically deformable actuator having a conductive inner surface and a cosmetic outer surface. The actuator may be disposed on an exterior surface of an enclosure that houses an electric circuit board of the electronic device. The enclosure may have one or more openings for providing an electrical connection between the actuator and the enclosed circuit of the electronic device. When the actuator is pressed, an electrical circuit may be closed and electric current may flow through the conductive inner surface of the actuator. The actuator may be combined with a perimeter element for snapping on and off the enclosure. |
| US09653223B2 |
Switch
A switch comprising a body case, a movable board that is movably disposed in the body case and a movable contact point disposed in the movable board is disclosed. A fixed contact point is provided in the body case with a lubricating agent applied thereto. The movable contact point makes pressure-contact with the fixed contact point, and is connected and disconnected from the fixed contact point corresponding to a position of the movable contact point changing by moving the movable board. Grooves are formed in a contact portion of the movable contact point with the fixed contact point to be arranged along the movement direction of the movable contact point. |
| US09653218B2 |
Electrolytic solution for electric double-layer capacitor, and electric double-layer capacitor
An electric double-layer capacitor is provided which is larger in electrostatic capacitance, and can be much higher in rated voltage, than that in the prior art using a liquid electrolyte solely composed of an ionic liquid. Having an electrolyte and electrodes, the capacitor incorporates an atom encapsulated fullerene or an atom encapsulated fullerene salt in the electrolyte. The electrolyte can either be a liquid solution or a solid. With the electrolyte being a solid, cations of the atom encapsulated fullerene or atom encapsulated fullerene salt may either be made movable or static in the electrolyte. |
| US09653217B2 |
Method of manufacturing surface-treated transparent conductive polymer thin film, and transparent electrode manufactured using the same
Disclosed is a method of manufacturing a surface-treated transparent conductive polymer thin film, including: 1) preparing a PEDOT:PSS ink composition; 2) forming a PEDOT:PSS thin film on a substrate using the ink composition; 3) applying a p-toluene sulfonic acid solution on the PEDOT:PSS thin film and then thermally treating the PEDOT:PSS thin film; 4) rinsing the thermally treated PEDOT:PSS thin film; and 5) drying the rinsed PEDOT:PSS thin film. |
| US09653208B2 |
Wireless power receiver and method of manufacturing the same
Disclosed are a wireless power receiver and a method of manufacturing the same. The wireless power receiver includes a first coil to wirelessly receive power, a second coil to make communication, and a first magnetic substrate having first and second recesses spaced apart from each other. The first coil is disposed on the first recess of the first magnetic substrate, and the second coil is disposed on the second recess of a second magnetic substrate. |
| US09653207B2 |
Inductive power transfer system
An inductive power transfer (IPT system) includes an AC-AC full-bridge converter (Tp1-Tp4) provided between the primary conductive path (Lpt) and an alternating current power supply (Vin). The system may include a controller for controlling the pick-up device to shape the input current drawn from the alternating current power supply (Vin). |
| US09653205B2 |
Electrode structure and the corresponding electrical component using the same and the fabrication method thereof
An electrical component is disclosed, wherein the electrical component comprises: a body; a conductive element, disposed in the body, wherein at least one portion of a first terminal part of the conductive element is exposed outside of the body; a conductive and adhesive layer, overlaying on the body and covering a first portion of the terminal part of the conductive element, wherein a second portion of the terminal part of the conductive element is not covered by the conductive and adhesive layer; and at least one metal layer, overlaying on the conductive and adhesive layer and covering the second portion of the terminal part of the conductive element, wherein the at least one metal layers is electrically connected to the second portion of the terminal part of the conductive element for electrically connecting with an external circuit. |
| US09653204B2 |
Symmetric multi-port inductor for differential multi-band RF circuits
Structures and methods for implementing high performance symmetric multi-port inductors are provided. The multiport inductor structure includes a plurality of conductors which are structured and arranged in turns to obtain symmetry between a plurality of selected input terminals connecting to respective ones of the plurality of conductors. |
| US09653202B2 |
Power converter and device integrating inductors in parallel of the same
A device is provided that integrates a plurality of inductors in parallel. The device includes a plurality of windings and a magnetic core structure. A number of the windings corresponds to a number of the inductors. The magnetic core structure includes a plurality of windows, wherein each window includes at least two windings coupled with each other. When a phase difference of the voltage phases is smaller than a predetermined value, voltage phases of two terminals of any two of the windings within the same window are substantially the same. |
| US09653200B2 |
Electromagnetic-valve controller
An electromagnetic-valve controller includes a control switch, a control portion regulating a supply current supplied to the electromagnetic valve by controlling a drive of the control switch and controlling to open or close the electromagnetic valve, and a current detection portion detecting the supply current. The control portion controls the drive of the control switch based on a detection result of the current detection portion. The control portion controls the drive of the control switch by using a first pulse signal having a duty ratio that is variable, in a closed period. The control portion controls the drive of the control switch by using a second pulse signal maintaining the supply current to be constant so as to maintain the electromagnetic valve to be in the fully closed state, in a closed-state maintaining period. |
| US09653199B2 |
Electromagnetic coil assemblies having braided lead wires and/or braided sleeves
Embodiments of an electromagnetic coil assembly are provided, as are methods for the manufacture of an electromagnetic coil assembly. In one embodiment, the method includes joining a first end portion of a braided lead wire to a coiled magnet wire. A dielectric-containing material is applied in a wet-state over the coiled magnet wire and over the first end portion of the braided lead wire. The dielectric-containing material is cured to produce an electrically-insulative body in which the coiled magnet wire and the first end portion of the braided lead wire are at least partially embedded. Prior to application of the dielectric-containing material, the braided lead wire is at least partially impregnated with a masking material deterring wicking of the dielectric-containing material into an intermediate portion of the braided lead wire. |
| US09653197B2 |
Wire harness, wire harness manufacturing method and wire harness manufacturing apparatus
A wire harness manufacturing method prevents inadvertent deformation of thermoplastic material and separation of thermoplastic material. A predetermined part of an electric wire 91 is accommodated in a through hole of a tubular body formed by connection between a first and second nest members (123, 124) of a nozzle (12), by integrally connecting first and second case body members (121, 122) of the nozzle (12), with the predetermined part of the electric wire 91 therebetween. An approximately tubular covering member (92) covering the predetermined part of the electric wire (91) is molded integrally with the thermoplastic material, by discharging thermoplastic material plasticized by a material plasticizing unit (11) from thermoplastic material discharge orifices (1213) and (1223) in the nozzle (12) to the outer periphery of the electric wire (91), while moving the electric wire (91) and the nozzle (12) relatively to each other. |
| US09653191B2 |
Copper alloy for electric and electronic device, copper alloy sheet for electric and electronic device, conductive component for electric and electronic device, and terminal
The present invention relates to a copper alloy for electric and electronic device, a copper alloy sheet for electric and electronic device, a conductive component for electric and electronic device, and a terminal. The copper alloy for electric and electronic device includes more than 2.0 mass % to 15.0 mass % of Zn; 0.10 mass % to 0.90 mass % of Sn; 0.05 mass % to less than 1.00 mass % of Ni; 0.001 mass % to less than 0.100 mass % of Fe; 0.005 mass % to 0.100 mass % of P; and a remainder comprising Cu and unavoidable impurities, in which 0.002≦Fe/Ni<1.500, 3.0<(Ni+Fe)/P<100.0, and 0.10 |
| US09653189B2 |
Canister transfer system with independent traveling shielded bell
A transfer system for spent fuel canisters includes a carrier, a shielded bell trolley movable along the carrier and carrying a shielded bell, and a canister trolley movable along the carrier and carrying a lifting mechanism for raising and lowering the spent fuel canister into and out of the shielded bell. The canister trolley can move along the carrier independent of the shielded bell trolley and the shielded bell trolley can move along the carrier independent of the canister trolley. The shielded bell trolley and the canister trolley can be selectively interlocked for selected transfer operations. |
| US09653181B1 |
Smart self-repair device and method of self-repairing a package
A smart self-repair device and method of self-repairing a package is disclosed. The smart self-repair device may include a fuse array configured to store information regarding respective bits of a fail address in fuses. The smart self-repair device may include a self-repair control circuit configured to control repairing of not only a target mat in which a fail occurs, but also adjacent upper and lower mats sharing a sense amplifier along with the target mat, and to output fail address information corresponding to a fail mode, and row fuse set information or a column fuse set information. The smart self-repair device may include a data control circuit configured to output repair information to the fuse array based on the fail address information and the row fuse set information or the column fuse set information, and may include a control circuit configured to control a rupture operation of the fuse array. |
| US09653180B1 |
System method and apparatus for screening a memory system
A system and method of writing data to a memory block includes receiving user data in a memory controller to be written to the memory block. The user data is first written to a buffer. A screening pattern is written to at least one screening column and a first memory integrity test is performed based on at least one operational aspect of the memory block. The first memory integrity test includes reading screening column data from the at least one screening column and comparing the screening column data read from the at least one screening column to the screening pattern. The user data is written to at least one user data column in the memory block when the screening column data read from the at least one screening column matches the screening pattern in the first memory integrity test. |
| US09653178B2 |
Magnetic track storage unit, memory, and method for controlling magnetic track storage unit
A storage device, a memory, and a method for controlling a storage device, where the storage device includes a comb-shaped magnetic track, a first drive circuit, a second drive circuit, a first drive port, and a second drive port, where the comb-shaped magnetic track includes a first storage area, a second storage area, and a comb handle, and the first storage area and the second storage area include more than two memory bars. |
| US09653175B2 |
Determination of word line to word line shorts between adjacent blocks
A number of techniques for determining defects in non-volatile memory arrays are presented, which are particularly applicable to 3D NAND memory, such as that of the BiCS type. Word line to word shorts within a memory block are determined by application of an AC stress mode, followed by a defect detection operation. An inter-block stress and detection operation can be used determine word line to word line leaks between different blocks. Select gate leak line leakage, both the word lines and other select lines, is consider, as are shorts from word lines and select lines to local source lines. In addition to word line and select line defects, techniques for determining shorts between bit lines and low voltage circuitry, as in the sense amplifiers, are presented. |
| US09653174B2 |
Semiconductor storage device
According to one embodiment, a semiconductor storage device includes memory cell array including a memory cell, a bit line coupled to the memory cell, a sense circuit coupled to the bit line and being capable of charging the bit line, and a charging circuit, the memory cell array being disposed between the sense circuit and the charging circuit and being capable of charging the bit line. |
| US09653170B2 |
Pillar-shaped semiconductor memory device and method for producing the same
A pillar-shaped semiconductor memory device includes Si pillars arranged in at least two rows; a tunnel insulating layer; a data charge storage insulating layer; first, second, and third interlayer insulating layers; and first and second conductor layers, all of which surround outer peripheries of the Si pillars, the first and second conductor layers being located at the same height in a perpendicular direction. A row of the semiconductor pillars is interposed between the first and second conductor layers of Si pillars arranged in an X direction. Shapes of the first and second conductor layers facing the semiconductor pillars are circular arcs. Adjacent circular arcs of the first conductor layer are in contact with each other, and adjacent circular arcs of the second conductor layer are in contact with each other. A pitch length of the Si pillars in the X direction is smaller than that in a Y direction. |
| US09653154B2 |
Write abort detection for multi-state memories
Techniques are presented to determine whether a multi-state memory device suffers has a write operation aborted prior to its completion. In an example where all the word lines of a memory block is first programmed to an intermediate level (such as 2 bits per cells) before then being fully written (such as 4 bits per cell), after determining that intermediate programming pass completed, the block is searched using the read level for the highest multi-state to find the last fully programmed word line, after which the next word line is checked with the lowest state's read level to determine whether the full programming had begun on this word line. In an example where each word line is fully written before beginning the next word line of the block, after determining the first erased word line, the preceding word line is checked as the highest state to see if programming completed and, if not, checked at the lowest read level to see if programming began. |
| US09653152B1 |
Low voltage high sigma multi-port memory control
In an aspect of the disclosure, an apparatus is provided. In one aspect, the apparatus is a memory controller that includes a logic circuit configured to generate a select signal for selecting between first and second ports of a memory as a function of first and second port signals. Additionally, the memory controller includes a switch configured to connect and disconnect the first and the second port signals. In another aspect of the disclosure, the apparatus is a storage apparatus that includes a memory and a memory controller. The memory controller includes a latch configured to latch a first port selection signal to produce a first port signal and latch a second port selection signal to produce a second port signal. The memory controller also includes a switch configured to connect and disconnect the first and the second port signals and a logic circuit configured to generate a select signal. |
| US09653146B2 |
High capacity memory system using standard controller component
The embodiments described herein describe technologies for using the memory modules in different modes of operation, such as in a standard multi-drop mode or as in a dynamic point-to-point (DPP) mode (also referred to herein as an enhanced mode). The memory modules can also be inserted in the sockets of the memory system in different configurations. |
| US09653145B1 |
Semiconductor devices and semiconductor systems including the same
A semiconductor system includes a first semiconductor device and a second semiconductor device. The first semiconductor device outputs first to (M+1)th command/address signals (wherein, “M” denotes a natural number which is equal to or greater than two) and receives a detection signal to detect a normality/abnormality of a temperature sensor. The second semiconductor device enters a test mode in response to the (M+1)th command/address signal and compare first to Nth sensing codes (wherein, “N” denotes a natural number which is equal to or greater than two) generated by the temperature sensor with the first to Mth command/address signals to generate the detection signal. The second semiconductor device also executes a refresh operation in response to a refresh signal including a plurality of pulses whose cycle time is controlled by the first to Mth command/address signals. |
| US09653144B1 |
Apparatuses, methods, and systems for package on package memory refresh and self-refresh rate management
Methods, systems, and apparatuses relating to package on package memory refresh and self-refresh rate management are described. In one embodiment, an apparatus includes a processor die, a dynamic memory die mounted to and overlapping the processor die, a first thermal sensor of the processor die disposed adjacent to a first hot spot from a first type of workload and a second thermal sensor of the processor die disposed adjacent to a second hot spot from a second type of workload, and a hardware control circuit of the processor die to cause a refresh of a capacitor of the dynamic memory die when either of an output of the first thermal sensor exceeds a first threshold value and an output of the second thermal sensor exceeds a second threshold value. |
| US09653142B1 |
Volatile semicondcutor memory device, refresh control circuit and method thereof
A refresh control circuit of a volatile semiconductor memory device is provided, where the volatile semiconductor memory device includes a plurality of memory cells respectively having a select transistor and a memory element, and the refresh control circuit of the volatile semiconductor memory device includes: a first comparison part, which compares a memory voltage of the memory cell of the volatile semiconductor memory device that is different to a general-memorizing memory cell with a specified threshold voltage, and outputs a comparison result signal, and stops self refresh of the memory cell until the memory voltage is decreased to be smaller than the specified threshold voltage. The memory cell is formed in a region adjacent to an array of the general-memorizing memory cell. |
| US09653139B1 |
Simultaneous plural wordline within a bank refreshing control device and memory device including the same
A refresh control device and a semiconductor device including the same, for preventing a row hammer failure from occurring, may include an enable signal generator configured to generate an enable signal for performing a smart refresh operation and a plurality of active controllers configured to generate a plurality of refresh signals for refreshing word lines located at different positions within one bank, based on receiving the enable signal. |
| US09653138B1 |
Magnetic memory and method of writing data
A memory includes a first magnetic layer, a second magnetic layer, a nonmagnetic layer between the first and second magnetic layers, a third magnetic layer synthetic-antiferromagnetic-coupled with the second magnetic layer, and a controller controlling a read operation and a write operation. The write operation includes a first operation, a second operation and a third operation. A first potential of the first magnetic layer is larger than a second potential of the third magnetic layer in the first operation. A third potential of the third magnetic layer is larger than a fourth potential of the first magnetic layer in the second operation. A fifth potential of the first magnetic layer is larger than a sixth potential of the third magnetic layer in the third operation. |
| US09653137B2 |
STT-MRAM bitcell for embedded flash applications
A spin transfer torque magnetic random access memory (STT-MRAM) device and a method to perform operations of an embedded eFlash device are disclosed. The STT-MRAM device is configured to include an array of STT-MRAM bitcells. The array includes a plurality of bitlines (BLs) and a plurality of word lines (WLs), where the bitlines form columns and the wordlines form rows of STT-MRAM bitcells. Each STT-MRAM bitcell includes a magnetic tunnel junction (MTJ) element coupled in series to an access transistor having a gate terminal and source and drain terminals. The array includes a plurality of source lines (SLs) coupled to the source terminals of the access transistors. A SL of the plurality of SLs is coupled to source terminals of access transistors of two or more adjacent columns of the STT-MRAM cells. The shared SL is parallel to the plurality of BLs. The operations of such a STT-MRAM bitcell are configured to include: an initialization operation, a program operation, and a sector erase operation. |
| US09653135B2 |
Multi-port non-volatile memory
A multi-port memory cell including: first and second magnetoresistive elements, each of which is programmable so as to adopt at least two resistive states, in which: the first magnetoresistive element is coupled with a first output line and is programmable by the direction of a current which is passed through same; and the second magnetoresistive element is coupled with a second output line and is arranged so as to be magnetically coupled with the first magnetoresistive element, the second magnetoresistive element being programmable by a magnetic field generated by the first magnetoresistive element. |
| US09653126B2 |
Digital ramp rate control for charge pumps
Methods for controlling a ramp rate of an output voltage derived from one or more charge pumps and reducing variation in the ramp rate due to process, voltage, and temperature (PVT) variations are described. In some embodiments, the ramp rate of the output voltage from one or more charge pumps may be controlled using a ramp rate control circuit that uses a digital counter to adjust (or step up) the output voltage from the one or more charge pumps based on a ramp rate schedule. The ramp rate schedule may specify varying output voltage levels for the one or more charge pumps during a time period in which the output voltage charges up from a first voltage to a second voltage greater than the first voltage. |
| US09653123B2 |
Direct data connectors for a sealed device and methods for forming a direct data connector for a sealed device
According to various embodiments, a method for forming a direct data connector for a sealed device may be provided. The method may include: providing a substrate with a hole; and filling the hole with a filling material using a plating process. |
| US09653121B1 |
Heat-assisted magnetic recording device capable of detecting head malfunction based on different currents of sensors
A method comprises storing a first laser current value in response to a photodetector sensing that a threshold current for a laser diode of a HAMR head has been reached, the photodetector situated proximate the laser diode. The method also comprises storing a second laser current value in response to a sensor sensing that the threshold current for the laser diode has been reached, the sensor situated away from the laser diode. The method further comprises determining a difference (delta) between the first and second laser current values, repeating the storing and determining processes during subsequent use of the laser diode, and detecting a change in the delta indicative of a malfunction of the head. |
| US09653118B1 |
System and method for scheduling clips
An example method involves: accessing a first list that includes ordered clip identifiers C1 . . . Cn; accessing a second list that includes ordered player identifiers P1 . . . Px; making a determination that a clip identifier Cm is an initial one of the clip identifiers C1 . . . Cn to have a player-identifier assignment-restriction; responsive to making the determination, (i) determining that the clip identifier Cm is restricted to being assigned a player identifier Pz from the player identifiers P1 . . . Px, and (ii) assigning to each clip identifier C1 . . . Cm in reverse order a respective one of the player identifiers P1 . . . Px selected in a reverse ordered and looping fashion starting with the player identifier Pz; and traversing the clip identifiers C1 . . . Cm, and for each traversed clip identifier, causing a player identified by the one of the player identifiers P1 . . . Px assigned to the traversed clip identifier to load a clip identified by the traversed clip identifier. |
| US09653117B2 |
Interconnected multimedia systems with synchronized playback of media streams
Synchronous playback of time-based media received from one or more locations remote from a primary editing/mixing studio is achieved by time-stamping media samples with a local presentation time before streaming them to the primary studio. At the primary studio, samples having the same presentation timestamp are played back at the same time, independently of the samples' arrival time at the playback system. Media stored locally to the playback system may also be included as part of the synchronous playback using locally computed presentation times. In order to accommodate media streaming transmission delays, the playback system negotiates a suitable delay with the remote systems such that samples corresponding to a given presentation time are received at the playback system from remote locations prior to playback of media corresponding to the given presentation time. |
| US09653116B2 |
Video pin sharing
Techniques are provided for assisting users to share specific locations within videos. Specifically, controls are provided to enable a viewer of a video to drop a “video pin” on a location within a video. In response to the user dropping a video pin at a particular location in the video, a “video pin record” that indicates the selected location is automatically generated by a video pin application. The video pins may be used to identify specific time points in the video and/or specific time segments of the video. Video pin records may be shared with other users to allow the other users to immediately jump to the locations, within the video, at which the corresponding video pins were dropped. |
| US09653115B2 |
Systems and methods for creating linear video from branched video
Computer-implemented methods and systems for creating non-interactive, linear video from video segments in a video tree. Selectably presentable video segments are stored in a memory, with each segment representing a predefined portion of one or more paths in a traversable video tree. A linear, non-interactive video is automatically created from the selectably presentable video segments by traversing at least a portion of a first path in the video tree and, upon completion, is provided to a viewer for playback. |
| US09653102B1 |
Data reader with pinned front shield
A data reader may have a magnetoresistive stack consisting of at least magnetically free and magnetically fixed structures. The magnetically fixed structure can be set to a first magnetization direction by a first pinning structure separated from an air bearing surface by a front shield portion of a magnetic shield. The front shield portion may be set to a different second magnetization direction by a second pinning structure. |
| US09653100B1 |
Magnetic head for perpendicular magnetic recording capable of preventing unwanted erasure
A magnetic head includes a coil, a main pole, a write shield, and a return path section. The coil includes a coil element located on the trailing side of the main pole. The coil element has a front end face facing toward the medium facing surface. The return path section includes a first portion, a second portion, and an intermediate film interposed between the first portion and the second portion. Part of the first portion is interposed between the medium facing surface and the front end face of the coil element. Part of the second portion is interposed between the first portion and the front end face of the coil element. |
| US09653098B2 |
Tape head modules for performing azimuth recording and reading of tape media using a linear format
A tape head module for performing azimuth recording and reading of tape media (e.g., where data bands are disposed at an angle to the direction of media travel) to increase the storage density of tape media. An array of read and/or write elements of the tape head module is oriented along an axis different than those of first and second lateral (e.g., overwrapped) edges of the tape head module. Positioning the first and second lateral edges of the disclosed tape head module to be perpendicular to the direction of tape motion (e.g., so that the tape moves over the first and second lateral edges perpendicularly to the first and second lateral edges) automatically positions the array of read and/or write elements at an azimuth angle (e.g., non-perpendicular angle) to the direction of tape motion. Also disclosed are methods for fabricating such tape head modules and related tape head assemblies. |
| US09653094B2 |
Methods and systems for performing signal analysis to identify content types
Systems and methods are configured to process audio signals to identify content-types. Audio content is received at an audio decoder which decodes the audio content. The decoded audio content is segmented into frames by applying a windowing function to a given audio frame using a window having a time width related to a delay time of the decoder. A power spectrum estimate of a given frame is determined. A mel filter bank is applied to the power spectrum of the frame. A DCT matrix is applied to filter bank energies to generate a DCT output. A log of the DCT output is used to generate a mel coefficient 1. A threshold for the content is dynamically determined. The mel coefficient 1 and the dynamically determined threshold are used to detect a near silence between content-types and to identify the content-types. |
| US09653093B1 |
Generative modeling of speech using neural networks
Features are disclosed for using an artificial neural network to generate customized speech recognition models during the speech recognition process. By dynamically generating the speech recognition models during the speech recognition process, the models can be customized based on the specific context of individual frames within the audio data currently being processed. In this way, dependencies between frames in the current sequence can form the basis of the models used to score individual frames of the current sequence. Thus, each frame of the current sequence (or some subset thereof) may be scored using one or more models customized for the particular frame in context. |
| US09653092B2 |
Method for controlling acoustic echo cancellation and audio processing apparatus
A method for controlling acoustic echo cancellation and an audio processing apparatus are described. In one embodiment, the audio processing apparatus includes an acoustic echo canceller for suppressing acoustic echo in a microphone signal, a jitter buffer for reducing delay jitter of a received signal, and a joint controller for controlling the acoustic echo canceller by referring to at least one future frame in the jitter buffer. |
| US09653090B1 |
Complex exponential modulated filter bank for high frequency reconstruction
An apparatus and method are disclosed for filtering and performing high frequency reconstruction of an audio signal. The apparatus includes an analysis filter bank, a phase shifter, a high frequency reconstructor, and a synthesis filter bank. The analysis filterbank receives real-valued time domain input audio samples and generates complex valued subband samples. The phase shifter shifts a phase of the complex-valued subband samples by an arbitrary amount. The high frequency reconstructor modifies at least some of the complex valued subband samples. A phase shifter unshifts a phase of the modified complex-valued subband samples by the arbitrary amount. The synthesis filter bank receives the modified complex valued subband samples and generates time domain output audio samples. The analysis filter bank comprises analysis filters that are complex exponential modulated versions of a prototype filter with an arbitrary phase shift. |
| US09653089B2 |
Encoder, decoder and methods for encoding and decoding data segments representing a time-domain data stream
An apparatus for decoding data segments representing a time-domain data stream, a data segment being encoded in the time domain or in the frequency domain, a data segment being encoded in the frequency domain having successive blocks of data representing successive and overlapping blocks of time-domain data samples. The apparatus includes a time-domain decoder for decoding a data segment being encoded in the time domain and a processor for processing the data segment being encoded in the frequency domain and output data of the time-domain decoder to obtain overlapping time-domain data blocks. The apparatus further includes an overlap/add-combiner for combining the overlapping time-domain data blocks to obtain a decoded data segment of the time-domain data stream. |
| US09653085B2 |
Reconstructing an audio signal having a baseband and high frequency components above the baseband
A method and system for reconstructing an original audio signal is disclosed. The original audio signal has a baseband up to a cutoff frequency and high-frequency components not included in the baseband above the cutoff frequency. The system includes a bitstream deformatter that extracts a representation of the baseband, an estimated spectral envelope, and noise-blending parameters from an audio bitstream. The system also includes a spectral component regenerator that copies or translates all or at least some of the baseband spectral components to non-overlapping frequency ranges of the high-frequency components not included in the baseband to generate regenerated spectral components. The system further includes a gain adjuster that modifies a spectral envelope of the regenerated spectral components based at least in part on the estimated spectral envelope and the noise-blending parameters to generate gain-adjusted regenerated spectral components. |
| US09653078B2 |
Response generation method, response generation apparatus, and response generation program
A response generation method includes a step of recognizing a voice of a user, a step of analyzing a structure of the recognized voice, a step of generating a free response sentence in response to the voice of the user based on the analyzed voice structure and outputting the generated free response sentence, a step of generating the recognized voice of the user as a repeat response sentence, and a step of outputting the generated repeat response sentence before outputting the free response sentence based on the voice structure. |
| US09653077B2 |
Message processing device
A speech input recognition unit, an event processing unit, which processes an event including a speech recognition result or a command, an expert unit including a plurality of expert modules each of which processes the event in cooperation with the event processing unit, and an execution history management unit, which manages execution history of the expert modules are provided. The expert unit is, for recording a user speech as message text, provided with a speech processing expert module for producing standard format text and a speech processing expert module for producing free format text and a transmission expert module for sending the message text. |
| US09653075B1 |
Voice commands across devices
Aspects of the subject technology relate to a method for using a voice command for multiple computing devices. First voice input data is received from a first computing device associated with a user account, where the first voice input data comprises a first voice command captured at the first computing device. Second voice input data is received from a second computing device associated with the user account where the second voice input data comprises a second voice command captured at the second computing device. An intended voice command is determined based on the obtained first and second voice input data. Based on the intended voice command, a first target computing device is determined. First instructions associated with the intended voice command are provided to the first target computing device for execution. |
| US09653067B2 |
Interpretation of natural communication
A computer-implemented method, including receiving by one or more computer systems input information that represents a multi-dimensional communication; detecting, based on contents of the input information, a plurality of communication inputs; applying one or more weighted values to one or more of the communication inputs; assigning, based on application of the one or more weighted values, confidence levels to the communications inputs; determining which of the confidence levels are below a confidence threshold; executing one or more disambiguation rules to disambiguate the communication inputs with confidence levels below the confidence threshold; and generating a communication instruction to perform an action that is specified by the multi-dimensional communication. |
| US09653063B2 |
Acoustic reflectors
An acoustic reflector comprises a shell surrounding a solid elastomeric core free of joints. The shell transmits acoustic waves incident on the surface of the shell partially into the core to be focused and reflected from an area of the shell located opposite to the area of incidence so as to provide a reflected acoustic signal output from the reflectorpartially around the circumference of the shell and to combine constructively with the reflected acoustic signal output. The ratio of the speed of sound wave transmission in the shell to the average speed of the wave transmission in the core is preferably in the range of 2.74 to 3.4 best results being in the range of 2.74 to 2.86 inclusive. |
| US09653062B2 |
Method, system and item
A method of enabling a hearer to hear desired sound while also being able to be aware of ambient sound, comprises providing a first non-sound signal representative of said desired sound, deriving a second non-sound signal from said ambient sound, combining the first and second non-sound signals in providing a third non-sound signal, and converting said third non-sound signal into sound. |
| US09653061B2 |
Acoustic device, and electronic device and image forming apparatus incorporating same
An acoustic device includes an opening; a flange forming the opening; a first member including the opening and the flange; and a second member joined to the first member, thereby forming a cavity. The second member is formed of a material with a density lower than a material of the first member. |
| US09653060B1 |
Hybrid reference signal for acoustic echo cancellation
An echo cancellation system that uses a combined reference signal using a playback reference signal and an adaptive reference signal. The playback reference signal is generated from a playback signal sent to a loudspeaker and the adaptive reference signal is generated using beamforming on microphone inputs corresponding to audio received from the loudspeaker. The system applies a low pass filter to the playback reference signal and applies a high pass filter to the adaptive reference signal to generate the combined reference signal. The system may remove the combined reference signal from target signals associated with the microphone inputs to isolate speech included in the target signals. |
| US09653058B2 |
Reverberation-induced magnetic field alteration to enhance sound
A passive feedback mechanism by which sound produced by a musical instrument is enhanced by utilizing the reverberations from the sound to dynamically and passively alter the magnetic field in the vicinity of an electronic pickup is disclosed. This is accomplished by utilizing a component or material adhered to the instrument with the property to alter the magnetic field as the material vibrates in response to sound reverberation, one embodiment being a ferromagnetic surface coating. An electromagnetic pickup, sensitive to these variations in the magnetic field, is installed on or within the instrument. The changes in the magnetic field, in response to the music, are captured by the pickup and transformed into an electric signal with thus produce a unique and enhanced sound. |
| US09653057B2 |
Electronic wind instrument
An electronic musical instrument includes: a contact sensor that generates lip detection information from an operation by a performer; and a controller that derives a lip contact area from the lip detection information generated by the contact sensor, and performs musical note control of an electronic sound source in accordance with the derived lip contact area. |
| US09653049B2 |
Device for altering the tension of the strings of a stringed musical instrument
The invention relates to a device for altering the tension of the strings of a stringed musical instrument, of the type comprising a structural element, with at least one element for securing to the body of the instrument, said structural element comprising at least two runners each secured to at least one string of the instrument, and an actuation mechanism for actuating the runners in order to alter the tension of the strings of the instrument, comprising at least one slide carriage that can be moved by the action of at least one lever. |
| US09653047B2 |
Finger-pressed auxiliary device for a stringed instrument
A finger-pressed auxiliary device for a stringed instrument is provided. The stringed instrument comprises a body, a neck connected to the body, a fingerboard disposed on the neck, a plurality of frets disposed on the fingerboard at spaced intervals, and a plurality of strings extending along the length direction of the neck. The finger-pressed auxiliary device comprises: a plurality of finger-pressed plates extending along the length direction of the strings and each being disposed to correspond to a respective string; an upper support secured to the top of the neck; and a lower support secured to the bottom of the neck or the body. As the fingers only have to contact the surfaces of the finger-pressed plates, the pain associated with holding strings with fingertips is avoided. |
| US09653044B2 |
Interactive display system
A display system comprises a head-mounted projector including an exit aperture and a projection engine to project image light through the exit aperture. The image light is projected onto a retro-reflective display that reflects image light in a first dimension at above 90% efficiency within a 25 degree exit angular spread and reflects image light in the first dimension below 10% efficiency outside of a 35 degree exit angular spread. |
| US09653043B2 |
Input device for magnifying a screen content and method thereof
A method for magnifying a screen content executed by an input device is disclosed. The method is suitable for magnifying a display content of a computer device and includes that the input device receives an informed command from the computer device. The informed command indicates whether the operation system of the computer device supports a system magnifier. If the operation system supports the system magnifier, the input device outputs a first magnification command to the computer device according to pressing of a function key. The computer device initializes the system magnifier of the operation system and magnifies the screen content according to the first magnification command. If the operation system doesn't support the system magnifier, the input device outputs a second magnification command provided by the input device to the computer device, so that the second magnification command magnifies the screen content according to the second magnification command. |
| US09653042B2 |
Travel path analysis support device and method
A travel path analysis support device includes a processor that executes a procedure. The procedure includes: performing, in accordance with a selected first display color control, change control of display colors of respective regions obtained by mesh-dividing within the geographic region according to a time-wise change in a number of vehicles that pass through the respective regions; when an instruction for enlarged display of a partial region inside the geographic region is received at as given timing of a procedure by which display colors of the respective regions are changed by the change control, displaying the partial region enlarged, and selecting a second display color control based on a total number of vehicles that have entered the partial region within the time range since the given timing; and performing, in accordance with the selected second display color control, change control of the display colors of the respective regions. |
| US09653041B2 |
Image display device and method of displaying image
An image display device comprises an image display unit including first pixels and second pixels arranged in a staggered manner, the first pixels including sub-pixels arranged in a matrix in a first color gamut and second pixels including sub-pixels arranged in a matrix in a second color gamut different from the first color gamut; and a processing unit that determines an output of the sub-pixels corresponding to an input image signal. When sub-pixels including same color component are continuously lit in a straight line and there is a difference between outputs from adjacent sub-pixels including the same color component, the processing unit determines the output of the sub-pixels in the first pixel based on the first component after an adjustment component is eliminated, and determines the output of the sub-pixels included in the second pixel based on the second component and the adjustment component. |
| US09653039B2 |
Method, apparatus and system for changing to which remote device a local device is in communication via a communication medium through use of interruption of the communication medium
A method, apparatus and system for changing to which remote device a local device is in communication via a communication medium, communicates with a matrix switch forming part of the system by interruption of the communication medium by the local device. Upon receipt of a unit of information via interruption of the communication medium, the matrix switch causes the local device to be in communication with another remote device other than the remote device that it was previously in communication. In one embodiment, the switching is to a next available remote device of a plurality of remote devices while in another embodiment, the matrix switch switches the local device to a switch configuration device for further communication therewith via the communication medium, thereby allowing the local device to select which other remote device it desires to be in communication. |
| US09653037B2 |
Optical device and display device provided with same
An optical device (100) includes a first substrate (10) and a second substrate (20), and an optical layer (30) interposed therebetween. The first substrate includes a first electrode (11) and a second electrode (12), and the second substrate includes a third electrode (21). The optical layer contains a medium (31) and anisotropically-shaped particles (32) whose alignment direction changes in accordance with the direction of an electric field applied to the optical layer. The first electrode and the second electrode, which are interdigitated electrodes, are disposed so that their respective branches (11a, 12a) mesh with one another via a predetermined interspace. The relationships w1 |
| US09653036B2 |
Method and system for adjusting gamma voltage, and electronic device
The method for adjusting a gamma voltage comprises: applying a reference common electrode voltage and a to-be-adjusted gamma voltage to a display module; collecting first light intensity data when the display module displays a grayscale test pattern after the reference common electrode voltage and the to-be-adjusted gamma voltage are applied; plotting a testing gamma curve in accordance with the first light intensity data; when the testing gamma curve is not located within the acceptable range of the standard gamma curve, adjusting the to-be-adjusted gamma voltage currently applied to the display module, until the testing gamma curve is located within the acceptable range of the standard gamma curve; and when the testing gamma curve is located within the acceptable range of the standard gamma curve, determining the to-be-adjusted gamma voltage currently applied to the display module as a final gamma voltage. |
| US09653035B2 |
Voltage calibration circuit and related liquid crystal display device
The present disclosure provides a voltage calibration circuit. The voltage calibration circuit includes a coupling voltage detection circuit and a common voltage circuit. The coupling voltage detection circuit is used for detecting a coupling voltage in an initial phase and generating a compensation voltage according to the coupling voltage. The common voltage circuit is used for adjusting a common voltage according to the compensation voltage and outputting the common voltage to a display module in a display phase. |
| US09653031B2 |
Multi-type common voltage driving method, common voltage control apparatus, and display driving circuit
A multiple common voltage driving method adapted for a display is provided. The driving method includes following steps: taking a common-voltage switching time unit as a repeating time unit to provide a common voltage to define a reference voltage of the display. The common-voltage switching time unit has a plurality of different types of common-voltage pattern periods. A time length of each of the common-voltage pattern periods includes at least one frame. During the different types of the common-voltage pattern periods, the provided common voltage has different AC voltage swings or different DC voltage levels. |
| US09653026B2 |
Backlight controlling apparatus, backlight controlling method and program
A timing controller performs control to cause a backlight to emit light at first brightness for a first time in a period that original image data is displayed on a liquid crystal panel, and cause the backlight to emit light at second brightness darker than the first brightness for a second time longer than the first time in a period that intermediate image data generated based on the original image data is displayed on the liquid crystal panel. |
| US09653025B2 |
Display device and electronic apparatus
A display panel including pixels disposed on a substrate, where each of the pixels includes a light emitting element, and a capacitor. The capacitor of a first one of the pixels is partially overlapped, in a vertical direction, by respective pixel areas of two of the pixels. The anode of the capacitor of the first one of the pixels may be disposed closer to the substrate than a cathode of the capacitor, thereby reducing a parasitic capacitance between the capacitor and an anode of the light emitting element of one of the two pixels overlapping the capacitor. |
| US09653023B2 |
Display devices
A display device is disclosed. In one aspect, the display device includes a display panel including a plurality of pixels divided into a plurality of block regions. The block regions are arranged in a scan direction. The display device also includes a display panel driver configured to sequentially drive the block regions and apply a plurality of first emission signals to the pixels. Each of the first emission signals has an activation voltage. The display device further includes a timing controller configured to control the display panel driver. The display panel driver is further configured to incrementally change the activation voltages of the first emission signals applied to the pixels in each of the block regions in the scan direction. |
| US09653018B2 |
Light-emitting diode driving device, driving method and light-emitting diode lighting module comprising the same
A light-emitting diode driving device enabling an excellent heat-dissipation function and high-efficient driving is disclosed. The disclosed LED driving device comprises: a power source unit providing an alternate current voltage; a rectification unit communicatively coupled to the power source and rectifying the alternate current voltage; a driving signal generation unit configured to receive the rectified voltage from the rectification unit and generate a primary driving signal by using the rectified voltage; and an LED driving signal modulation unit communicatively coupled to the driving signal generator, the LED driving signal modulation unit configured to receive the primary driving signal and generating a secondary pulse driving signal by modulating the primary driving signal, and LED groups including LEDs and configured to receive the primary driving signal or the second pulse driving signal such that the LED groups operate responsive to the primary driving signal or the secondary pulse driving signal. |
| US09653016B2 |
Display device
A display device includes: a display panel including a display area, and a peripheral area disposed in the vicinity of the display area; a scan driver including a plurality of stages integrated on the peripheral area; a plurality of gate lines connected to the plurality of stages, respectively; and a plurality of pixel rows in the display area and connected with the plurality of gate lines, respectively. The plurality of stages and the plurality of pixel rows are each arranged in a first direction in a line, the peripheral area includes a fan-out region between the plurality of stages and the plurality of pixel rows, and at least one of the plurality of gate lines in the fan-out region is inclined with respect to the first direction, and a second direction perpendicular to the first direction. |
| US09653015B2 |
Display devices with high resolution and spatial density modulation architecture
Architecture and designs of display devices are described, where the display devices possesses high spatial resolution as well as high intensity resolution and may be readily used in various projection applications, storage and optical communications. According to one aspect of the present invention, a display device includes an array of image elements, each of the image elements further includes an array of sub-image elements. These sub-image elements are driven by PWM as in digital modulation. A portion of an image element area, namely some of the sub-image elements, is turned on, which has the same perceived effect of turning on an entire image element for a specific time. In addition, various designs of an image element or a sub-image element are described. |
| US09653014B2 |
Method of driving an electro-wetting display panel and electro-wetting display apparatus for performing the same
A method of driving an electro wetting display panel includes applying a first data voltage to a pixel part of the display panel during a first section of a frame and applying a second data voltage different from the first data voltage to the same pixel part during a second section of the frame. The first data voltage is converted from display data based on a first gamma curve. The second data voltage is converted from the display data based on a second gamma curve. Light transmittance through the pixel part is changed based on movement of a fluid within the pixel part. |
| US09653005B2 |
Erasable loop scheduler
An erasable loop scheduler with a board and a loop system is disclosed. The board has a first and second side, each having a viewing pane that displays a different portion of the loop system. The loop system includes a grid system that can be configured like a calendar. A user can write out a full month of dates and appointments on the first side of the board and another full month of dates and appointments on the second side of the board. Once a row of events has passed, the loop system can be advanced, at which point the row of past events moves to the second side of the board. The user may then erase that row of events and replace with upcoming dates and appointments. Alternatively, the user may keep the row of events for future reference. |
| US09652995B2 |
Reward/punishment-and-control system
In one embodiment, one or more first computing devices receive, from one or more second computing devices associated with a first person, information concerning an activity, the information describing the activity, a reward associated with the activity, and a condition of the reward; transmit, to one or more third computing devices associated with the second person, the information; receive, from the third computing devices, a first response by the second person; and if the first response is an acceptance to the activity by the second person, then: receive, from the third computing devices, first sensor data relating to the activity; analyze the first sensor data to determine whether the condition of the reward is satisfied; and if the condition of the reward is satisfied, then transmit, to the second computing devices and the third computing devices, a second notice indicating that the condition of the reward has been satisfied. |
| US09652994B1 |
Piano learning guidance system
Disclosed is a piano learning guidance system, comprising a piano and two hand drums, wherein the piano comprises a control module, a storage module, a first LCD display screen, a second LCD display screen, a third LCD display screen, a key recording microphone and a plurality of first LED light bars in one-to-one correspondence to keys of the piano, and each first LED light bar is formed by a plurality of first LEDs; the storage module, the first LCD display screen, the second LCD display screen, the third LCD display screen and the key recording microphone are all electrically connected to the control module; the hand drum comprises a second LED light bar and a pressure sensor, and the second LED light bar is formed by a plurality of second LEDs; and the second LED light bar and the pressure sensor are electrically connected to the control module. |
| US09652987B2 |
Distributed remote sensing system component interface
A distributed remote sensing system including at least one gateway, at least one sensing device and a communication interface providing radio frequency communication through a shared frequency scheme between each sensing device and one of the at least one gateway and between each sensing device and another of the at least one gateway through a different frequency scheme. |
| US09652985B2 |
Vehicle guidance system
A vehicle guidance system (VGS) facilitates interaction between human operated vehicles (HOV), autonomous driverless vehicles (ADV), and/or semi-autonomous vehicles, on the roadway, allowing safe interface with each other and with other elements, for example, weather conditions, traffic control systems, road conditions, obstructions that enter the roadway (people, rocks, animals, debris falling onto roadway from other vehicles), etc. The system provides guidance, communication, and control for the vehicles on the roadway, by using a solar-powered system comprising post assemblies having solar panel(s), sensors, forward and/or downward lighting, and other indicators/alarms to signal to the vehicle or driver regarding road, bridge, weather, accident, speeding, or other conditions of concern in the vicinity for safety and/or operability of the vehicle/driver(s). |
| US09652977B2 |
Calibration technique for automated window coverings
A method for calibrating an automated window covering includes electromechanically actuating a window covering and measuring electrical current required to actuate the window covering. The method further measures movement of the window covering, where such movement includes one or more of a change in position and velocity of the window covering. The method estimates a size (e.g., height, width, area, etc.) of the window covering and/or an amount of force required to actuate the window covering based on the measured electrical current and movement. A corresponding apparatus is also disclosed herein. |
| US09652975B1 |
Integrated building occupant protection system for persons and pets
An integrated building occupant protection system includes alarm units having a controller, one or more sensors, a timer, a transceiver, an audio alert device, and a communication device. When a sensor detects a threat, the audio alert device is activated. The transceiver transmits an event signal to mobile devices associated with the building occupants. The controller uses response signals from those devices to pinpoint the location of the occupants, which may be broadcast by the communication device. The mobile devices may be cellular telephones or pet collar devices. The system is configured to perform periodic self-tests. A system for generating revenue by selling promotional time following the system tests is also provided. |
| US09652972B1 |
Maintenance of telecommunications network infrastructure based on alarm scoring
A method for prioritized action of telecommunication network alarms in a telecommunication network management system. The method comprises setting, by an alarm severity scoring application executing on a computer, an initial alarm severity score for each of the plurality of alarms based on network classification and a geographical location of an alarm, wherein the network classification of the alarms is performed by a network classify application. The method further comprises evaluating, by the alarm severity scoring application executing on the computer, each of the alarms based on a plurality of weighting factors, determining an alarm severity score based on the evaluation and the initial alarm severity score for each of the alarms, and prioritizing actions for the alarms based on the alarm severity scores. |
| US09652971B1 |
System and process for distributed network of redundant central stations
Techniques are described for distributing, to a distributed network of central stations, alarm events detected in monitoring system data collected by sensors included in monitoring systems located at monitored properties. A system receives monitoring system data collected by sensors included in monitoring systems located at monitored properties, tracks alarm events detected within the monitoring system data, and generates, for central station servers in a distributed network of central stations, load profiles that reflect a volume of alarm events being handled at each of the central station servers at a particular period of time. The system determines capacities to handle additional alarm events for the central station servers, determines relative priorities for the central station remote servers based on the determined capacities, and directs subsequent alarm events to the central station servers based on the relative priorities. |
| US09652965B2 |
System and method for transmitting alerts and notifications to a user
A system for transmitting alerts and notifications to a user. The system includes a user wearable portable data communication unit configured to set a predetermined period of time and select a geographical area by using a mapping software integrated with the user wearable portable data communication unit for geo-fencing the selected geographical area, an alerting unit configured in the user wearable portable data communication unit to transmit notifications and alerts to predefined list of contacts on determining the crossing of the user from the selected geo-fence area and exceeding the predetermined time period set by the user and a web based server unit in communication with user wearable portable data communication unit through a data communication network configured to store the predefined list of contacts, threshold levels, frequency, way points, current location of the user and software versions. |
| US09652964B2 |
Notification method and electronic device
An operation method and a device related to emergency situations are provided. A method for controlling an electronic device includes determining a designated situation, based on at least one piece of information obtained from outside the electronic device and information obtained from at least one sensor of the electronic device, determining features corresponding to the designated situation, and controlling the electronic device, based on at least one of the features and user status information. |
| US09652963B2 |
Provisioning and managing autonomous sensors
A autonomous sensor includes a sensor configured to measure one or more events, a network interface, and a processor. The autonomous sensor is configured to communicate with a plurality of other autonomous sensors using the network interface. The processor is configured to detect, while in a discovery state, if an event has occurred and enter an active state if the event occurred, when an event has occurred, enter an active state, transmit event data to a parent while in the active state, detect the presence of a neighboring sensor; and when the neighboring sensor is detected, while in a nomadic state, monitor the activity of the neighboring sensor. |
| US09652962B1 |
Systems and methods for safety and proximity sensing in industrial environments
A system includes a first electronic device configured to attach to an industrial machine or one or more areas of an industrial facility. The first electronic device is configured to transmit a signal indicative of a potentially hazardous condition with respect to personnel of the industrial facility. The system also includes a second electronic device communicatively coupled to the first electronic device and configured to attach to a hardhat of the personnel of the industrial facility. The second electronic device is configured to receive the signal from the first electronic device, determine whether a parameter of the signal is above a threshold, and generate an alarm when the parameter of the signal is above the threshold. The alarm is configured to indicate the potentially hazardous condition to the personnel. |
| US09652960B2 |
Device and method for routing a medical alert to a selected staff member
A method for routing a medical alert to a selected staff member 151-153, the method comprising receiving an alert signal generated by an alert generation device 121-126, obtaining the current location and identity of multiple staff members from a location tracking system 141-146 configured to track the locations of the multiple staff members, upon receiving the alert signal, selecting from the multiple staff members a selected staff member by at least determining that the distance between a location of the alert generation device and the location of the selected staff member is shorter than the distance between the location of the alert generation device and the location of at least one of the multiple staff members other than the selected staff member, and sending an alert signal to an individually addressable mobile device associated with the selected staff member. |
| US09652959B2 |
Smart wake
Methods and systems for security and/or automation systems are described. In some embodiments, the methods may include identifying an area of a premises associated with an occupant, identifying a wake up time associated with the occupant, identifying a location associated with the occupant, and initiating one or more automated actions based at least in part on the wake up time and the area. |
| US09652953B2 |
Surveillance of a secure area
Embodiments of the invention are directed to a system, method, and computer program product for surveillance of a secure area. The present invention typically includes a memory, a processor, and a module configured to monitor the secure area. In this regard, an embodiment of the present invention may receive an indication that a user is within the secure area and determine, using an authentication device sensor, whether the user has the authentication device to remain within the confines of the secure area. The user may have continued access to the secure area if the authentication device detected. On the other hand, the security personnel associated with the secure area may be notified of an unauthorized user when the authentication device is not detected. |
| US09652949B1 |
Sensor experience garment
The present invention includes systems and methods for enhancing audience sensory experience. Light-emitting diodes and vibrators may activate on an audience member shirt when an actor receives a hit while wearing a shirt having sensors. The audience member may choose to receive input from a particular actor's shirt. The audience member may also choose to view a replay of an event and activate the associated light-emitting diodes and vibrators. |
| US09652948B2 |
Haptic actuator including circuitry for generating drive waveforms based upon a beat frequency and related methods
A haptic actuator may include a housing, at least one coil carried by the housing, and a field member movable within the housing responsive to the at least one coil. The housing, at least one coil, and field member may define a resonant frequency. The haptic actuator may also include drive circuitry coupled to the at least one coil and being capable of generating first and second drive waveforms having respective different frequencies spaced about the resonant frequency to drive the field member at a beat frequency lower than the resonant frequency. |
| US09652943B1 |
Electronic play calling device, system, and process
An electronic play calling device, system, process is disclosed for calling plays displaying encoded representations associated with the plays is displayed on an electronic display board adjacent to a playing field. The electronic play calling device includes a play calling board, a power source, and several LED lights attached to the board and configured to illuminate a translated signal that is visible to a set of players on the playing field. |
| US09652939B2 |
System and method of conducting games of chance as a proxy or basis for another player
To bring the excitement to the people (majority, who are not experts in games), we present the examples, described here, for one person to be able to bet on and be part of the deal and excitement for a third party, as his agent, proxy, or shadow, to bet for him, or instead of him, or as if the first person was doing the game directly, or one betting for another, or one playing for another with the other person's money. That generates more excitement on the game or casino, with more participation, transactions, income, profit, loyalty, and repeat customers. This brings a lot of variations on the game, e.g., stock market model, or derivatives model, or hedge model. This can be applied to sports and table games or fantasy sports. This can be applied to online, real, mobile, fantasy, simulation, computer generated, human based, or casino games or settings. |
| US09652938B2 |
Game live auction system and method of operation
A method for conducting a raffle comprising reading an item identifier from an identification tag affixed to an item at an equipment management system, prior to an event related to the item. The raffle notification data is then transmitted to users after the event has occurred. A plurality of raffle ticket purchase requests are then received from the plurality of devices and are processed. The raffle tickets are then delivered to the plurality of devices, such as in electronic form. One of the raffle tickets is then selected, and winning notification data is transmitted to the associated device. The winner can authenticate the winning item by reading the identification tag affixed to the item after the event at the equipment management system. |
| US09652933B2 |
Slot machine game with expanding positions
Systems, methods, and program products are taught which provide a slot machine game that increases the size of the symbol array as a mystery feature. As the player spins the reels, the number of positions available on each reel grows randomly to allow more paylines. Other embodiments may include free spin bonuses, as well as bonus features that further increase the number of positions on each reel, and adjust the probability of reel expansions based on the current array size. |
| US09652932B2 |
Account adjusting system
An account adjusting system according to an embodiment of the invention comprises a game machine that pays an award corresponding to a kind of a prize of a game; and an account adjusting apparatus that adjusts an account for a user. The game machine has a paying section for determining an award corresponding to a kind of a prize of a game and a determining section for determining whether or not tax payment is required based on the award determined by the paying section, and when determining that tax payment is required, transmitting award information indicative of the award to the account adjusting apparatus. The account adjusting apparatus has a receiving section for receiving the award information; a tax payment amount calculating section for calculating a tax payment amount based on the award information; and a tax payment certificate providing section for producing an output to prepare a tax payment certificate based on the tax payment amount. |
| US09652931B2 |
Collusion detection
Various embodiments that may generally relate to collusion are described. Collusion detection may be used to prevent players in a wagering environment from violating the integrity of a game. Player actions may be tracked to develop a wagering profile that is specific to various game situations. A player acting in a manner that would be against their interest and against their defined profile may be considered a colluding action. Information about collusion actions may be presented for evaluation and/or anti-collusion actions may be automatically taken in response to such collusion actions being determined. |
| US09652930B2 |
Systems, methods, and apparatus for a bingo game having special ball functions
Systems, apparatus, methods and articles of manufacture provide for a bingo game including at least one special ball having an associated special function. In one embodiment, one or more special functions may have persistent effects on one or more bingo spaces (e.g., of a bingo card) and/or may be combined with the effects one or more other special functions. |
| US09652928B2 |
Gaming machine, gaming machine display and method
A gaming device, gaming device display and method are set forth which includes a first electronic, video display including L-shaped sub-displays mated to define a frame surrounding an opening which accommodates a second display. The second display may be a mechanical component extending through the opening to operate for example a pointer operating with the first video display to provide a game function. The opening may also be configured to reveal a mechanical, electro-mechanical or video display. |
| US09652925B1 |
Infection control systems and methods
Hygiene control stations and methods are shown and described. In one embodiment, the control station includes picking compartments with corresponding automated inventory control. Further, the control stations may include user instructions and best hygiene practices. In particular examples, the control stations include sensors and alarms to ensure proper usage. The result is control systems and methods to improve hygiene care, infection control, inventory management, and the like. |
| US09652922B1 |
Vending machine remote sensing of contents apparatus
A vending machine remotes contents sensing apparatus collects information from the actual delivery of a product, sends it on to an MCU, then to a CPU, to the internet, to a remote receiver with a web interface application on a web page for access by a service person for real time delivery information. |
| US09652921B2 |
Coin chute with anti-fishing assembly
A coin chute for a vending machine may include one or more anti-fishing assemblies located in the vicinity of the coin chute's opening for receiving coins. The anti-fishing assemblies may include one or more rotatable anti-fishing fingers that project into a coin channel. The anti-fling fingers may rotate out of the coin channel to allow inserted coins to pass. In addition, the anti-fishing fingers prevent withdrawal of inserted coins out of the coin channel. The anti-fishing assemblies may be in addition to anti-pull back assemblies that prevent inserted coins from being withdrawn back past a coin discriminator. |
| US09652914B2 |
Methods and systems for secure pass-set entry
Methods and systems for secure pass-set entry are disclosed. In one example, an authenticator device is configured to generate a pass-set menu to output in visual format on the display. An I/O device is configured to output audio corresponding to the pass-set menu to the user. A user input interface is configured to receive user actions to navigate the pass-set menu and receive user menu selections. |
| US09652911B2 |
Entry control system
An integrated security system which seamlessly assimilates with current generation logical security systems. The integrated security system incorporates a security controller having standard network interface capabilities including IEEE 802.x and takes advantage of the convenience and security offered by smart cards and related devices for both physical and logical security purposes. The invention is based on standard remote authentication dial-in service (RADIUS) protocols or TCP/IP using SSL, TLS, PCT or IPsec and stores a shared secret required by the secure communication protocols in a secure access module coupled to the security controller. The security controller is intended to be a networked client or embedded intelligent device controlled remotely by to an authentication server. In another embodiment of the invention one or more life cycle management transactions are performed with the secure access module. These transactions allow for the updating, replacement, deletion and creation of critical security parameters, cryptographic keys, user data and applications used by the secure access module and/or security token. In another embodiment of the invention a security access module associated with the security controller locally performs local authentication transactions which are recorded in a local access list used to update a master access list maintained by the authentication server. |
| US09652905B2 |
Diagnostic reporting for sensor integrated circuits
A sensor integrated circuit comprising a controller and a diagnostic module in communication with the controller. The controller is configured for providing a diagnostic reporting signal being a periodic superposition signal on a sensing output of the sensor integrated circuit and/or on a supply current of the sensor integrated circuit. The periodic superposition signal has periodic pulses with a predetermined fixed pulse duration and a predetermined periodicity. The controller furthermore is configured for altering the predetermined periodicity or predetermined fixed pulse duration of the periodic superposition signal upon a fault detection in the diagnostic module communicated to the controller. |
| US09652898B2 |
Mail creation system with improved control of print-data downloading
An apparatus includes a printer and a buffer coupled to the printer for temporarily storing sheets fed out from the printer. The apparatus further includes a control mechanism for monitoring the buffer to determine a number of sheets currently stored in the buffer. The apparatus also includes a data source device that is separate from the printer and is coupled to the printer for selectively providing pages of print data to the printer. The data source device is coupled to the control mechanism and is operative to provide the pages of print data to the printer in response to control signals from the control mechanism. |
| US09652897B2 |
Color fill in an augmented reality environment
A method for operation a head-mounted computing device that includes capturing an image of a three-dimensional environment external to the head-mounted computing device and identifying a surface within the captured image that is eligible for color fill operation, based on similarities in color parameters of contiguous pixels in the captured image. The method further includes receiving a color fill request via user input at the head-mounted computing device, the request being for a predetermined color and performing a color fill operation on the identified surface in response to receiving the color fill request by (a) generating a fill hologram having the predetermined color and a shape that conforms to the shape of the identified surface, (b) displaying the fill hologram in a world-locked manner so as to overlay the identified surface as viewed through the see-through holographic display of the head-mounted display device. |
| US09652894B1 |
Augmented reality goal setter
A method implemented on an augmented reality (AR) device includes receiving an image of an object at the AR device. The image is displayed on a display screen of the AR device. One or more activating actions are received at the AR device. As a result of the one or more activating actions: the object is identified, an identity of the object is sent to a server computer, information is received from the server computer regarding a percentage of completion towards a goal relating to the object and a representation of the percentage of completion towards the goal relating to the object is visually displayed on the image of the object. |
| US09652893B2 |
Stabilization plane determination based on gaze location
Embodiments are described herein for determining a stabilization plane to reduce errors that occur when a homographic transformation is applied to a scene including 3D geometry and/or multiple non-coplanar planes. Such embodiments can be used, e.g., when displaying an image on a head mounted display (HMD) device, but are not limited thereto. In an embodiment, a rendered image is generated, a gaze location of a user is determined, and a stabilization plane, associated with a homographic transformation, is determined based on the determined gaze location. This can involve determining, based on the user's gaze location, variables of the homographic transformation that define the stabilization plane. The homographic transformation is applied to the rendered image to thereby generate an updated image, and at least a portion of the updated image is then displayed. |
| US09652885B2 |
Method and system for x-ray image generation
A method for generating a virtual radiograph for display on a display device, including providing an image generation system having a processing circuit including a processor and a memory device, the image generation system coupled to the display device. The method further including retrieving three-dimensional image data of an anatomy stored in the memory and retrieving a three-dimensional bone model corresponding to a portion of the anatomy stored in the memory. The method further including associating the three-dimensional bone model with the three-dimensional image data such that the three-dimensional bone model defines first boundary containing a first bounded volume within the three-dimensional image data corresponding to the portion of the anatomy, and performing a volume ray casting process on the three-dimensional image data. |
| US09652884B2 |
System and method for generating a reference plane of a head
A method includes receiving a Computed Tomography (CT) image comprising a head of a subject from a CT scanner and detecting a first and a second petrous bone of the head in the CT image. The method further includes determining a nasion of the head in the CT image based on the first and the second petrous bone. The method also includes generating a reference plane of the head based on the nasion and the first and the second petrous bone. |
| US09652875B2 |
Systems and methods for generating a dense graph
Methods and systems for generating a dense graph are described. One of the methods includes receiving a graph and computing a threshold to apply to the graph. The method further includes determining whether the graph includes a first set of at least one node, determining whether a second set of at least one node from the first set meets the threshold, and removing the at least one node of the second set concurrently from the graph upon determining that the at least one node of the second set meets the threshold. The operation of removing is performed to generate an updated graph. The method includes determining whether a density of the updated graph is greater than a density of the graph and replacing the graph within the updated graph upon determining that the density of the updated graph is greater than the density of the density of the graph. |
| US09652872B2 |
System and method of medical imaging
A system of medical imaging including a marking module, a classifying module, a region-of-interest determining module, a curve acquiring module and a delay calculating module. The marking module is used for marking one or more feature regions from pre-scanned images; the classifying module is used for classifying the feature regions by using a classification algorithm model; the region-of-interest determining module is used for selecting a feature region of the same type as a specific diagnostic tissue as a region of interest; the curve acquiring module is used for acquiring a curve of CT values of the region of interest in function of time, based on a relationship between the CT values and scanning time points; the delay calculating module is used for detecting a peak value of the curve and calculating a scan delay time based on a time point corresponding to the peak value. |
| US09652868B2 |
Automatic color palette based recommendations
Systems and methods are provided for determining whether certain color image metadata is accurate. A color image and associated color image metadata provided by a source for inclusion in an electronic catalog are accessed. A color palette corresponding to the color image is generated. A color name associated with the color palette is determined. A determination is made as to whether the image metadata comprises a color name. If the image metadata comprises a color name, a determination is made as to whether the color name included in the image metadata corresponds to the color name associated with the color palette. If the color name included in the image metadata does not correspond to the color name associated with the color palette or if the image metadata does not comprise a color name, the color name associated with the color palette is added to the color image metadata. |
| US09652866B2 |
Electronic device and image processing method
An image processing method is provided. A first image is obtained at a first time point, the first image includes a first object image and a first background image, the first object image corresponds to the position of an object at the first time point. A second image is obtained at a second time point, the second image includes a second object image and a second background image, the second object image corresponds to the position of the object at the second time point, and the first and the second images are shot within substantially the same shooting range. A sum motion vector of the object is obtained according to the first and the second object images. The second object image is kept, and a process is applied to each pixel of the second background image in the second image to generate a third image. |
| US09652864B2 |
Three-dimensional object recognition device and three-dimensional object recognition method
A 3D-object recognition device includes: a matching unit to compare a 3D-object in an image based on the image data with a 3D-shape model corresponding to the 3D-object to associate correlated feature points with each other by pattern matching; a model updating unit to update the 3D-shape model based on the feature points associated by the matching unit; a motion estimation unit to estimate motion of the 3D-object based on a history of the position and attitude of the 3D-shape model updated by the model updating unit to estimate a 3D-shape model at an arbitrary time in the future; and a validity determination unit to compare the feature points associated by the matching unit with the 3D-shape model estimated by the motion estimation unit and cause the model updating unit to update the 3D-shape model based on only the feature points determined to be valid. |
| US09652863B2 |
Multi-mode video event indexing
Multi-mode video event indexing includes determining a quality of object distinctiveness with respect to images from a video stream input. A high-quality analytic mode is selected from multiple modes and applied to video input images via a hardware device to determine object activity within the video input images if the determined level of detected quality of object distinctiveness meets a threshold level of quality, else a low-quality analytic mode is selected and applied to the video input images via a hardware device to determine object activity within the video input images, wherein the low-quality analytic mode is different from the high-quality analytic mode. |
| US09652862B1 |
System and method for dynamic device tracking using medical imaging systems
A system and method are provided for generating images that track a position and shape of a medical device within a subject. The method includes acquiring image data from a subject along at least two disparate view angles, each view angle including a deformable medical device arranged in the subject. The method also includes receiving images reconstructed from the image data and exploring a search space to compare the images with a dynamic three-dimensional (3D) model at least using a deformation parameter to determine a position and shape of the deformable medical device within the subject. The method further includes displaying an image of the subject and deformable medical device arranged within the subject based on the position and shape of the deformable medical device within the subject. |
| US09652861B2 |
Estimating device and estimation method
An estimation method executed by a computer includes: extracting, from an image, a plurality of characteristic points satisfying a certain requirement regarding changes in gray levels between the plurality of characteristic points and surrounding points; identifying, as map points from the plurality of characteristic points, characteristic points existing on planes, by excluding corners of an object depicted on the image; extracting, from another image, another plurality of characteristic points satisfying the certain requirement; executing matching of the another plurality of characteristic points with the map points based on a region including the map points; and estimating, based on results of the matching, a position and an orientation of an imaging device while the another image is captured. |
| US09652855B2 |
Image processing apparatus that identifies image area, and image processing method
An image processing apparatus including: an acquisition unit configured to acquire a boundary between a target area and a non-target area from an image; a setting unit configured to set an undefined area on the periphery of the boundary in a width based on feature quantities of peripheral pixels of the boundary; and a generating unit configured to define an area excluding the undefined area from the target area as the foreground area, define an area excluding the undefined area from the non-target area as the background area, and generate area information that specifies the foreground area, the background area, and the undefined area. |
| US09652854B2 |
System and method for identifying an object in an image
A method for processing image data includes identifying a background scene in a background frame of an image. Each of a plurality of pixel locations in the background frame is set as a respective background pixel. For each of the pixel locations, a respective running mean and a respective running variance are determined based on a brightness component of the background frame at the pixel location. A subsequent frame is identified as a current frame. For each of the pixel locations in the current frame identified as a background pixel, the running mean is updated based on one of a plurality of mean weights and the running variance is updated based one of a plurality of variance weights. For each of the pixel locations in the current frame, an identification is made if the current pixel location is one of a background pixel and a foreground pixel based on a brightness component of the current pixel location in the current frame, the running mean of the current pixel location, and the running variance of the current pixel location. |
| US09652852B2 |
Automated generation of a three-dimensional scanner video
A method for automatically generating a three-dimensional (3D) video of a scene by measuring and registering 3D coordinates at a first position and a second position of a 3D measuring device, the 3D video generated by combining two-dimensional images extracted at trajectory points along a trajectory path. |
| US09652850B2 |
Subject tracking device and subject tracking method
A subject tracking device includes a processor; and a memory which stores a plurality of instructions, which when executed by the processor, cause the processor to execute, detecting at least one subject candidate area in which it is probable that a tracking target subject appears on an image that is received from an imaging unit; calculating a degree of blur of the subject candidate area for each of the subject candidate areas; determining that the subject appears in a subject candidate area having a degree of blur in accordance with a moving speed of the subject, out of the subject candidate areas; and deciding movement of the subject depending on a movement direction from an area in which the subject appears on a previous image that is captured by the imaging unit before capturing the image, to the subject candidate area in which the subject appears on the image. |
| US09652849B2 |
Techniques for rapid stereo reconstruction from images
Stereo image reconstruction techniques are described. An image from a root viewpoint is translated to an image from another viewpoint. Homography fitting is used to translate the image between viewpoints. Inverse compositional image alignment is used to determine a homography matrix and determine a pixel in the translated image. |
| US09652848B2 |
Image stitching in a multi-camera array
Images captured by multi-camera arrays with overlap regions can be stitched together using image stitching operations. An image stitching operation can be selected for use in stitching images based on a number of factors. An image stitching operation can be selected based on a view window location of a user viewing the images to be stitched together. An image stitching operation can also be selected based on a type, priority, or depth of image features located within an overlap region. Finally, an image stitching operation can be selected based on a likelihood that a particular image stitching operation will produce visible artifacts. Once a stitching operation is selected, the images corresponding to the overlap region can be stitched using the stitching operation, and the stitched image can be stored for subsequent access. |
| US09652847B2 |
Method for calibrating a digital optical imaging system having a zoom system, method for correcting aberrations in a digital optical imaging system having a zoom system, and digital optical imaging system
The invention relates to a method for calibrating a digital optical imaging system, comprising at least one motorized or coded zoom system and an image sensor, to a method for correcting aberrations in such an imaging system, and to an optical imaging system which is configured to carry out the methods according to the invention. During the calibration method, a reference object is recorded in various zoom settings and the image is corrected pixel-wise with digital-optical means using a previously determined model. To this end, distortion correction coefficients and image stability correction coefficients are ascertained. The real total magnification of the system is ascertained from the corrected image. The model ascertained in the calibration process also serves for correcting aberrations during operation of the imaging system. |
| US09652842B2 |
Method, apparatus and equipment of inspecting quality of LCD
A method, an apparatus and an equipment of inspecting the quality of an LCD are provided, the method includes: obtaining optical parameters of the LCD; capturing images of the LCD; and determining that the LCD is defective after determining that the optical parameters are not in the range of the preset optical parameters and/or the captured images of the LCD are not consistent with the pre-stored images. Through the technical solution of the present invention, it can effectively differentiate the defect types of a product and record the defect position of the product, thereby it can effectively reduce misjudgment or miss test caused by the visual differences between operators to improve the quality and yield of manufactured LCD. |