| Document | Document Title |
|---|---|
| US09654544B2 |
Time-out management for session dependent applications
A method, system and apparatus for time-out management for session-dependent applications. A time-out management system can include one or more of pages defining a session-dependent application. The system further can include a server-side time-out manager configured for use in a content server in detecting a time-out condition in the session-dependent application when the session-dependent application has been distributed to a content client. Finally, the system can include at least one client-side time-out manager configured to detect activity for the session-dependent application and to notify the content server when activity is detected in the session-dependent application when the session-dependent application has been distributed to the content client. |
| US09654543B2 |
Communication method and communication program
A communication method includes, when a first communication packet transmitted from a first terminal which is deployed in a second physical machine group and included in a first segment is received, storing identification information of the first communication packet transmitted from the first terminal, first transmitting the first communication packet transmitted from the first terminal to the first network device based on path information included in the configuration information when the first communication packet transmitted from the first terminal is a communication packet to a second terminal included in a second segment, when the first communication packet is transmitted from the first network device, and second transmitting the received first communication packet transmitted from the first network device to the second terminal and updating the path information so as to transmit a communication packet transmitted from the first terminal without passing through the first network device. |
| US09654542B2 |
Adaptive accelerated application startup
Embodiments of the present invention include methods and systems for accelerated application startup. A method for accelerating startup of an application is provided. The method includes persistently storing a number of uniform resource locator (URL) hostnames based on one or more hostname requests made by one or more users during use of the application. The method further includes, upon startup of the application, making a DNS lookup call for at least one of the stored hostnames prior to a hostname request initiated by the application, wherein a resolution result for at least one of the stored hostnames is cached in the operating system DNS cache in preparation for the hostname request. A system for accelerating startup of an application is provided. The system includes a hostname storage device, a DNS pre-fetcher and a startup DNS pre-cacher. |
| US09654540B2 |
Load balancing among network servers
Apparatus for performing load balancing among network servers connected to an internal IPv6 network. The apparatus comprises a first interface coupled to an external IPv4 or IPv6 network for receiving packets sent across the external network and an IP packet creator coupled to said first interface. This IP packet creator is configured, for each received packet at that interface, to select a network server to be allocated to the packet or identify an already allocated network server. The IP packet creator is further configured to create a corresponding IPv6 packet for transmission over said internal network to the selected or identified network server. The apparatus further comprises a second interface coupled to said internal IPv6 network for transmitting created IPv6 packets across the internal network towards respective selected or identified network servers. |
| US09654534B2 |
Video broadcast invitations based on gesture
In an example embodiment, a gesture indication generated by a mobile device in response to a user gesture on a user interface of the mobile device with respect to a video currently being recorded by the mobile device is received. Availability notifications are then issued to the one or more potential visitors in the listing. A visit request is received from one of the one or more potential visitors, and then a host invitation is issued to the mobile device. In response to an indication that the user device has permitted the potential visitor corresponding to the visit request to view the video currently being recorded as a live video broadcast, the video currently being recorded is broadcast to the potential visitor corresponding to the visit request. |
| US09654532B2 |
System and method for sharing file portions between peers with different capabilities
An electronic device with one or more processors, memory and a display obtains information that enables distribution of content between clients operating as peers in a peer-to-peer network. A first subset of the clients have first file format processing capabilities and a second subset of the clients have second file format processing capabilities. The peer-to-peer network enables access to a first set of file portions corresponding to the first file format and a second set of file portions corresponding to the second file format. The first set of file portions and the second set of file portions both include one or more shared file portions. The device provides, to one or more clients, information that enables the respective content to be shared over the peer-to-peer network that enables shared file portions be obtained either clients in the first subset of clients or clients in the second subset of clients. |
| US09654528B1 |
Dynamic bitrate selection for streaming media
A bitrate selector on a user device monitors a first stream of a plurality of bitrate media streams of a media file, the first media stream having a first bitrate, these plurality of bitrate media streams comprising a first subset of bitrate media streams including the first media stream and a second subset of bitrate media streams having a bitrate higher than the first bitrate. The bitrate selector calculates an expected download time for a subsequent chunk of the media file in each bitrate media stream of the second subset of bitrate media streams. The bitrate selector selects a bitrate media stream of the second subset of bitrate media streams for the subsequent chunk based on the expected download times and downloads the subsequent chunk from the selected bitrate media stream. |
| US09654524B2 |
System and method to customize a multipoint control unit
Various disclosed embodiments include methods and systems for constructing a multipoint control unit (MCU). The method includes generating an abstract multipoint control unit (MCU) process at an electronic device, the abstract MCU process comprising an identification of MCU resources for instantiating the abstract MCU process. The method includes transmitting, from the electronic device, the abstract MCU process to a server, and receiving, from the server in response to the transmitted abstract MCU process, a concrete MCU process at the electronic device, the concrete MCU process comprising the identified plurality of MCU resources. |
| US09654523B2 |
Information processing system, and non-transitory computer readable medium for displaying electronic stickey notes transmitted from a participant device to a board of a shared device
An information processing device includes a receiver, an association unit, and a controller. The receiver receives an instruction to associate one first device from among multiple first devices that display a board as well as stickies pasted onto that board with a second device that creates a sticky. The association unit associates the first device and the second device according to an instruction received by the receiver. The controller controls transmission of information related to a board and stickies pasted onto that board in the first device associated by the association unit to the second device. |
| US09654520B1 |
Internet SIP registration/proxy service for audio conferencing
To enable internet softphone users to join to calls hosted at an audio conferencing bridge, a SIP Invite may be received at a bridge interface layer of an audio conferencing system. Parameters of the SIP Invite may be extracted, e.g. from one or more X-header fields and processed to enable the internet softphone to be joined to an audio conferencing bridge. The bridge interface layer may receive a SIP Refer message from the audio conferencing bridge that indicates a second audio conferencing bridge external to the system. The bridge interface layer may forward the SIP Invite to the second audio conferencing bridge and the RTP media may be established through the session border controller (SBC) of the audio conferencing system. |
| US09654516B2 |
Method and device for negotiating media capability
A method includes sending, by a first device, a first message to a second device, sending a third message to the second device, where the first message includes information about at least one media capture capability supported by the first device, and at least one first association identifier, the third message includes at least one configuration item supported by the first device and at least one second association identifier, and the at least one first association identifier corresponds to the at least one second association identifier in a one-to-one manner, and receiving, a second message and a fourth message sent by the second device, where the second message includes at least one media capture capability that is selected by the second device according to the first message and the third message, and at least one third association identifier corresponding to the at least one media capture capability. |
| US09654515B2 |
Service oriented architecture-based SCIM platform
Service Capability Interaction Manager (SCIM)-type functionality is provided at a horizontal service layer in an Service Oriented Architecture (SOA)-based approach. SCIM composition is provided at multiple levels, including the level of composition where servlets have full access to the context information of the service layer. SCIM composition also occurs at the level of an application dispatching messages to multiple applications/services for processing the messages. The functionality at the service layer also can be programmed using policies, such that routing decisions can be made dynamically as the result of processing conditions and actions. An incoming message can result in a Web service being triggered that in turn triggers a BPEL or SOA workflow, the workflow calling multiple operations to process the message as a result of a routing table or header, environmental and contextual information at the service level, and other information such as user preference or presence information. |
| US09654514B1 |
Trust level modifier
A computer establishes normal activity levels of a factor associated with an application, system, network, or computing environment. The computer receives rules prescribing the trust levels assigned to users or devices during normal and abnormal activity levels exhibited by the factor. The computer monitors the activity level exhibited by the factor and determines whether the activity is normal or abnormal. If the computer determines that the factor is exhibiting abnormal activity, the computer modifies the trust level of associated users and devices according to the rules. The computer continues to monitor the activity of the factor until the computer determines that normal activity levels of the factor have returned, at which point the computer modifies the trust level of associated users or devices according to the rules. |
| US09654510B1 |
Match signature recognition for detecting false positive incidents and improving post-incident remediation
The present disclosure relates to using signatures in a data loss prevention system. According to one embodiment, a DLP system identifies an occurrence of a data loss prevention (DLP) incident triggered by content and a DLP rule. The DLP system generates a first signature representing the DLP incident based on a specific pattern inherent to the content which triggered the DLP incident. The DLP system compares the first signature to one or more second signatures generated from other DLP incidents associated with the DLP rule. Upon determining the first signature matches at least one of the second signatures, the DLP system assigns an event status of the second matching signature to the first signature. |
| US09654509B2 |
Method and apparatus for providing distributed policy management
An approach is provided for distributed policy management and enforcement. A policy manager determines one or more domains of an information system. The one or more domains are associated at least in part with respective subsets of one or more resources of the information system. The policy manager also determines one or more respective access policies local to the one or more domains. The one or more respective access policies configured to enable a determination at least in part of access to the respective subsets, the one or more resources, or a combination thereof. At least one of the one or more respective access policies is configured to operate independently of other ones of the one or more respective schemas. |
| US09654494B2 |
Detecting and marking client devices
Methods, apparatus, connection systems, and client devices are described. The apparatus receives a multiplicity of DNS query messages from multiple client devices. For each received DNS query message to a malware domain name or a particular domain name, the apparatus sends a marker DNS response message to the corresponding client device for use in detecting whether the client device is infected with malware or is accessing the particular domain name. The connection system receives a connection request from a client device of the multiple client devices for access to the communication network, and sends marker detection information to the client device for use in identifying whether client device is marked as infected with malware or accessing a particular domain name. It is determined whether the client device is infected with malware or accessed the particular domain name. The client device may be blocked or granted access to the communication network. |
| US09654493B2 |
Network accountability among autonomous systems
In one kind of DoS attack, malicious customers may try to send a large number of filter requests against an innocent customer. In one implementation, a Filter Request Server (FRS) may allow a customer against who a filter request is made to dispute the implicit accusation of the filter request or stop sending malicious traffic. If the customer claims innocence, the FRS may log destination addresses of data packets sent by the customer and identify and ignore false filter requests if these filter requests come from customers who do not correspond to one or more of the destination addresses that have previously been logged by the FRS. |
| US09654492B2 |
Malware detection system based on stored data
A malware detection system based on stored data that analyzes an electronic message for threats by comparing it to previously received messages in a message archive or to a contacts list. Threat protection rules may be generated dynamically based on the message and contacts history. A message that appears suspicious may be blocked, or the system may insert warnings to the receiver not to provide personal information without verifying the message. Threat checks may look for unknown senders, senders with identities that are similar to but not identical to previous senders or to known contacts, or senders that were added only recently as contacts. Links embedded in messages may be checked by comparing them to links previously received or to domain names of known contacts. The system may flag messages as potential threats if they contradict previous messages, or if they appear unusual compared to the patterns of previous messages. |
| US09654490B2 |
System and method for fuzzing network application program
A system and method for fuzzing a network application program, which use a captured packet upon fuzzing a network application program, and thus neither a protocol analysis procedure nor the production of a fuzzer program is required. The system for fuzzing a network application program includes a fuzzing performance client program unit for generating a packet to be transmitted from a captured packet, applying a fuzzing rule to the packet to be transmitted, and outputting a resulting packet. A fuzzing supervisor program unit provides the packet from the fuzzing performance client program unit to a target program to be fuzzed, monitors an event and abnormal termination of the target program to be fuzzed, and analyzes a situation of termination to verify security vulnerabilities if abnormal termination has occurred. |
| US09654488B2 |
Method and system for detecting restricted content associated with retrieved content
In embodiments of the present invention improved capabilities are described for detecting restricted content associated with retrieved content. The method and system may include receiving a client request for content, saving contextual information from the client request, presenting retrieved content in response to the client request, and presenting the contextual information from the client request, and retrieved content, to a scanning facility. The scanning facility may utilize the contextual information from the client request to aid in the detection of restricted content associated with retrieved content. |
| US09654487B2 |
Method and product for providing a predictive security product and evaluating existing security products
A method, product and computer program product for providing evolutionary selection of malware variants, the method including the steps of: receiving a malware specimen; generating a first generation of variants corresponding to the malware specimen; evaluating each variant of the first generation of variants for one or more evasiveness characteristics and one or more maliciousness characteristics; based on the evaluating, selecting variants of the first generation of variants for further mutation; and generating a second generation of variants from each of the selected variants. |
| US09654484B2 |
Detecting DGA-based malicious software using network flow information
Detecting DGA-based malware is disclosed. In an embodiment, a number of domain name server requests originating from a particular host among a plurality of hosts is determined. The number of domain name server requests are directed to one or more domain name servers. A number of internet protocol addresses contacted by the particular host is determined. Based on the number of domain name server requests and the number of internet protocol addresses contacted existence of malware on the particular host is determined. |
| US09654482B2 |
Overcoming circular dependencies when bootstrapping an RPKI site
In one embodiment, a validation server in a computer network determines that an edge router of the computer network has blocked access to a desired server address based on the edge router not having authentication information for the desired server address. In response, the server creates a white-listing policy to temporarily allow access to the desired server address at the edge router, and sends the white-listing policy to the edge router. The validation server may then proceed with performing server fetching operations to the desired server address from the validation server while the white-listing policy is in effect, and instructs the edge device to remove the white-listing policy once the server fetching operations are completed. |
| US09654480B2 |
Systems and methods for profiling client devices
Systems and methods are provided for providing generating and managing profiles. Such systems and methods may be implemented to control access to a function of a web server or site based on a level of trust associated with a user or device profile. According to one exemplary method, session information associated with a request to access a function of a web server is identified. At least one processor determines whether the request is associated with a trusted device profile based on the at least the session information. Access to the requested function is provided when the request is associated with a trusted device profile. |
| US09654478B2 |
Methods, media, and systems for securing communications between a first node and a second node
Methods, media, and systems for securing communications between a first node and a second node are provided. In some embodiments, methods for securing communication between a first node and a second node are provided. The methods comprising: receiving at least one model of behavior of the second node at the first node; and authorizing the first node to receive traffic from the second node based on the difference between the at least one model of behavior of the second node and at least one model of behavior of the first node. |
| US09654476B2 |
Management of drone operations and security in a pervasive computing environment
A method to provide negotiation control to data such that a person or entity can negotiate the use of data gathered beyond what is needed for a particular use by a third party transaction. The method also provides negotiation for the control and operation of autonomous vehicles such as drones operating in non-public space. |
| US09654475B2 |
Client behavior control in adaptive streaming file
A computer-implemented method for controlling adaptive streaming media access includes requesting a first portion of media content from a content server and requesting authorization corresponding to a second portion of media content from an authorization server. The method further includes submitting evidence to the authorization server that the first portion of media content has been received by a client device and receiving a representation of authorization to access the second portion of media content in response to the evidence complying with a requirement. The method also includes requesting the second portion of media content from the content server, presenting the representation of authorization to the content server, and receiving the second portion of media content in response to the representation of authorization being accepted by the content server. The method can effectively control client behavior to prevent the client from skipping past required media content, such as a commercial advertisement. |
| US09654473B2 |
Authentication proxy agent
An authentication engine may be configured to receive an authentication request and credentials from a client. The authentication engine may then generate a proxy agent configured to interact with an identity provider to authenticate the client on behalf of the client, using the credentials. In this way, the authentication engine may receive an assertion of authentication of the client from the identity provider, by way of the proxy agent. |
| US09654471B2 |
Identifying peers by their interpersonal relationships
According to this disclosure, a user is identified (and selectively granted access to protected resources) by using information that describes the user's interpersonal relationships. This information typically is stored in a datastore, such as a digital address book, an online profile page, or the like. The user's digital address book carries an “acquaintance pattern” that changes dynamically in time. This pattern comprises the information in the user's contact list entries. In this approach, the entropy inherent in this information is distilled into a unique acquaintance digest (or “fingerprint”) by normalizing the contact list data, and then applying a cryptographic function to the result. |
| US09654469B1 |
Web-based user authentication techniques and applications
A system, apparatus, method, and machine readable medium are described for performing user authentication. For example, one embodiment of a system comprises: media capture logic implemented as a component within a browser executed on a client, the media capture logic configured to capture a user's voice from a microphone on a client or images of the user's face or other portion of the user's body from a camera on the client, the media capture logic exposing an application programming interface (API); and a web authentication application implemented as another component within the browser for communicating with an authentication server to perform biometric authentication of a user, the web authentication application making calls to the API of the media capture logic to capture raw biometric data comprising the user's voice from the microphone and/or images of the user's face or other portion of the user's body from the camera, the web authentication application to implement a biometric authentication process to authenticate the user with the raw biometric data. |
| US09654468B2 |
System and method for secure remote biometric authentication
Systems and methods for secure remote biometric authentication are provided. A network-based biometric authentication platform stores biometric templates for individuals which have been securely enrolled with the authentication platform. A plurality of sensor platforms separately establishes secure communications with the biometric authentication platform. The sensor platform can perform a biometric scan of an individual and generate a biometric authentication template. The sensor platform then requests biometric authentication of the individual by the biometric authentication platform via the established secure communications. The biometric authentication platform compares the generated biometric template to one or more of the enrolled biometric templates stored in memory at the biometric authentication platform. The result of the authentication is then communicated to the requesting sensor platform via the established secure communications. |
| US09654467B1 |
Time synchronization solutions for forward-secure one-time authentication tokens
Methods and apparatus are provided for improving resilience to forward clock attacks. A token generates a passcode from a user authentication token for presentation to an authentication server by detecting a forward clock attack; and communicating an indication of the forward clock attack to the authentication server. The generation of the user authentication passcodes is optionally suspended upon detecting the forward clock attack. The detection may be based on a comparison of a current device time of the token and a last used device time during a generation of a user authentication passcode. |
| US09654466B1 |
Methods and systems for electronic transactions using dynamic password authentication
Methods and systems for performing electronic transactions using dynamic password authentication involve, for example, sending, using a backend processor, a unique random or pseudorandom character string to the user's mobile device processor. Thereafter, also using the backend processor, a user identifier and a challenge string consisting at least in part of the user identifier and the random or pseudorandom character string encrypted with a unique encryption key may be received from the user's mobile device processor. Using the backend processor, a cipher input consisting at least in part of the user identifier and the random or pseudorandom character string is encrypted with the unique encryption key. The received encrypted challenge string is authenticated if the received encrypted challenge string matches the encrypted cipher input. |
| US09654462B2 |
Late binding authentication
A late-binding token (LBT) is securely generated and provided to a device application. When the LBT is presented and validated, a resource associated with the presentation is bound to the LBT and authenticated for access to a service and provided valid credentials for accessing that service. |
| US09654451B2 |
Method and system for securing communication
A method for generating one or more secrets for use by members. The method includes sending a first request for connection with a second member, and sending a second request to connection with a third member. The method further includes receiving, by the first member from the second member, a second input after the first request is sent and after communication is initiated between the first member and the second member and receiving, by the first member from the third member, a third input after the second request is sent and after communication is initiated between the first member and the third member. The method further includes generating, using an n-bit generator executing on the first member, a message digest using a first input, the second input, and the third input, extracting a secret from the message digest, and storing the secret in a secrets repository on the first member. |
| US09654447B2 |
Customized handling of copied content based on owner-specified similarity thresholds
Making a determination of originality of content is disclosed. At least one originality factor related to the content is analyzed, wherein the originality factor is independent of a time when the content is detected. Based on the analysis of the at least one originality factor, automatically the determination is automatically made. The determination is outputted. |
| US09654446B2 |
On-the fly pattern recognition with configurable bounds
Some embodiments of on-the-fly pattern recognition with configurable bounds have been presented. In one embodiment, a pattern matching engine is configured based on user input, which may include values of one or more user configurable bounds on searching. Then the configured pattern matching engine is used to search for a set of features in an incoming string. A set of scores is updated based on the presence of any of the features in the string while searching for the features. Each score may indicate a likelihood of the content of the string being in a category. The search is terminated if the end of the string is reached or if the user configurable bounds are met. After terminating the search, the scores are output. |
| US09654445B2 |
Network traffic filtering and routing for threat analysis
Implementations disclosed herein provide a managed security service that distributes processing tasks among a number of network security modules working in parallel to process component portions of a replayed network traffic stream. If a network security module detects a potential security threat, the network security module may generate a delivery request specifying other information potentially useful in further investigation of the potential security threat. The delivery request is communicated to a plurality of other processing entities, such as the other network security modules, and any processing entity currently receiving the requested information may respond to the delivery request. Once a source of the requested information is determined, the requested information is routed to the origin of the request. |
| US09654443B2 |
Local device identity allocation for network assisted device-to-device D2D communication
A method of a network node adapted to provide assistance of device-to-device communication is disclosed. The method comprises receiving, from a first wireless communication device adapted to perform device-to-device communication, one or more first global device identities associated with the first wireless communication device and allocating one or more first local device identities to the first wireless communication device based on the received global device identities (330). The method also comprises storing, in association to the network node, a mapping between each received one or more first global device identity and each allocated one or more first local device identity, transmitting information indicative of the allocated one or more first local device identities to the first wireless communication device, and transmitting information indicative of at least one of the allocated one or more first local device identities to a first group of one or more other wireless communication devices (350). A method of a wireless communication device adapted to perform device-to-device communication is also disclosed. The method comprises receiving, from a network node, information indicative of at least one local device identity allocated to another wireless communication device, and monitoring device-to-device communication beacon signaling based on the received at least one local device identity. |
| US09654434B2 |
Message originating server, message orginating method, terminal, electric appliance control system, and electric appliance
A control server (1) causes an analyzing section (15) to analyze (i) at least either of sensor information from a household sensor (10) and operation information on a household electric appliance and (ii) external information, and then originates a message to be directed to a user, the message being generated by a message generating section (16) in correspondence with the result of the analysis. |
| US09654431B1 |
Automated email account verification
A system and method of verifying a registered contact path associated with a user account is provided. The disclosed techniques utilize a message sent via the registered contact path, wherein the message contains, among other content, a link. The link is instrumented to identify the registered contact path when activated, e.g., by the recipient or otherwise, allowing a determination as to whether the registered contact path is active. User login data for the user account received subsequently includes a login contact path, and the registered contact path may be further flagged as verified if it is determined that the login contact path and the registered contact path are the same. |
| US09654430B2 |
Communicating with recipient email server while composing email
Provided are techniques for the transmission of electronic mail (email). While a user composes an email message and once an intended recipient has been entered, negotiation modules associated with client and server computers check both the recipient and attributes of the message as they are entered. The user is notified if there is an issue with the intended recipient and alternative recipients may be suggested. The user is also notified if a particular attribute exceeds a defined limit. In this manner, the user may alter the message so that the attribute conforms to the limit to ensure delivery. Tests may be provided to enable a user to exceed a limit and some users may be pre-authorized to exceed a limit. |
| US09654428B2 |
Systems and methods for supporting social productivity using a history buffer
Systems and methods provide a social productivity platform to create or modify documents and other data content objects using collaborative efforts, possibly where the efforts are received through a social networking service. The systems and methods can, for example, create, review and share documents, spreadsheets and presentations from any device, using any cloud storage provider. When teams of users collaboratively work on a document or other file, systems and methods connect each the team users to the document or file, and maintain a history buffer of comments, changes, or other events. The systems and methods enable a user to create, review, edit, or otherwise access content and capture information regarding changes implemented during individual or group-based editing to the content. |
| US09654427B2 |
Presenting instant messages
Methods and systems for presenting instant messaging contacts are provided. At a computing device having one or more processors that execute one or more programs stored in memory of the computing device there is obtained, from a first electronic device, a first online status of an instant messaging contact. The instant messaging contact is logged-in, at the first electronic device, with respect to an instant message application. Further there is obtained a second online status of the instant messaging contact from a second electronic device. The instant messaging contact is also logged-in, at the second electronic device, with respect to the instant message application. There is determined, with respect to the instant messaging application, an overall online status for the instant messaging contact using the first online status and the second online status. |
| US09654426B2 |
System and method for organizing messages
A system and method for sorting messages within an interface including providing a navigational menu with at least three menu options of at least three message collections, the menu options ordered according to an ordered horizontal virtual arrangement of a set of message collections; upon receiving user selection of one of the menu options, activating the message collection corresponding to the user selected menu option, which comprises—displaying the message collection of the selected menu option and virtually positioning the remaining set of message collections off screen; within the active message collection of the set of message collections, detecting a gesture swipe in a horizontal direction; selecting a sorting option corresponding to a message collection virtually positioned in the horizontal direction relative to the active message collection; and transferring the message to the message collection of the selected sorting option. |
| US09654420B2 |
Relay device
One external ports of the line cards are set as member ports of the same LAG. When monitoring a continuity between the member ports of the LAG and an outside of the device, a management card generates a first monitoring frame and transmits it to any line card corresponding to the LAG. The line card transmits the first monitoring frame to the outside of the device from the external port. When the line cards corresponding to the LAG receive a second monitoring frame from the outside of the device by the LAG, the line cards transmit the second monitoring frames to the management card. |
| US09654419B2 |
Fabric channel control apparatus and method
A method for receiving packet data at a communication channel and transmitting the packet data over serial links of the communication channel. The packet data is sliced into n-bit data portions which are concatenated with a header prior to transmitting an n-bit portion across one of the serial links of the communication channel. The header may include an invert bit to alter the majority sign of an n-bit portion. Other aspects of the present invention are also described herein. |
| US09654418B2 |
Method and system of supporting operator commands in link aggregation group
A method is disclosed that is to be executed for supporting operator commands in a link aggregation group at a network device. The method starts with receiving a local operator command for changing aggregation port priority of the link aggregation group, where the local operator command contains operator command attributes including an operator command aggregation port prioritized list. The method continues with determining that the operator command aggregation port prioritized list is different from a remote aggregation port prioritized list used at the remote network device. The network device then transmits a set of operator command attributes associated with the local operator command to the remote network device and performs the local operator command by setting a local aggregation port prioritized list to be consistent with the operator command aggregation port prioritized list for the link aggregation group. |
| US09654414B2 |
Scheduling cost efficient datacenter load distribution
A method for scheduling cost efficient data center load distribution is described. The method includes receiving a task to be performed by computing resources within a set of data centers. The method further includes determining, all available data centers to perform the task. The method further includes determining lowest computing cost task schedule from available data centers. The method further includes scheduling the task to be completed at an available data center with the lowest cost computing. |
| US09654412B2 |
Method and system for directing user between captive and open domains
A method for limiting user access to a captive domain or an open domain. The captive domain may include electronically accessible content that is selected/controlled by a service provider and the open domain may include electronically accessible content that is not completely selected/controlled by the service provider. The method may include configuring a modem or other user device in such a manner as to limit use access to the desired domain. |
| US09654410B2 |
Virtual quantized congestion notification
Congestion management for data traffic in a virtual domain identifies a congestion source and sends a message to the source to adjust data traffic rates. The source may be a virtual machine hosted by a physical server with one or more virtual servers incorporated. A congestion manager may identify the source and send the message to the source without affecting other data sources hosted by the physical server or the virtual servers. In some embodiments, information about the congestion source may be encapsulated in a packet payload readable only by the congestion source so only the congestion source receives the instruction to adjust the transmission rate. |
| US09654406B2 |
Communication traffic processing architectures and methods
Communication traffic processing architectures and methods are disclosed. Processing load on main Central Processing Units (CPUs) can be alleviated by offloading data processing tasks to separate hardware. |
| US09654404B2 |
On-board wireless device and communication system
An on-board wireless device used in a subject vehicle and transmitting a vehicle information of the subject vehicle to a periphery vehicle positioned around the subject vehicle, includes a transmitting circuit successively transmitting the vehicle information of the subject vehicle via a vehicle-to-vehicle communication at a transmission interval, a transmission interval setting section setting the transmission interval that is variable for transmitting the vehicle information, and a generation section generating the vehicle information to be transmitted by the transmitting circuit. The generation section includes, in the vehicle information, a transmission interval related information based on which the transmission interval set by the transmission interval setting section is specified. The transmitting circuit transmits the vehicle information that includes the transmission interval related information to the periphery vehicle. |
| US09654403B1 |
Unfusing operators from a streaming processing element to avoid congestion
A streams manager determines when congestion is happening or is predicted to happen in a streaming application, and in response, unfuses one or more operators in the streaming application from its processing element. The selection of which operators to unfuse in which processing elements is made using suitable unfuse criteria, which may include selecting operators that do not maintain state, selecting operators that have a threaded port or queue preceding the operator, selecting operators at natural boundaries, and inserting queues before operators to be unfused. Once one or more operators are unfused, the streams manager can take action to enhance performance of the unfused operator(s). For example, the streams manager can allocate additional resources to the unfused operators, can create clones of unfused operators that process tuples in parallel, can move one or more unfused operators to a public cloud, etc. |
| US09654398B2 |
Computer system, controller, switch, communication method and recording medium storing a network management program
A computer system according to the present invention includes: a switch which transfers test data to a different switch via each of a plurality of networks to obtain a transfer performance of each of the plurality of networks; and a controller which configures a flow entry onto a flow table of the switch, the flow entry defining a network with a transfer performance equal to or higher than a threshold value as a transfer route to the different switch. This achieves load balancing in the computer system by using the OpenFlow technology. |
| US09654397B2 |
Method for looking up data in hash tables and associated network device
A network device is provided. The network device includes: a hash memory and a controller. The hash memory has a plurality of hash tables, wherein each hash table includes a plurality of entries, and each entry in each hash table has a signature field, and a key field. The controller is configured to map a search key to a plurality of entries of the hash tables and perform longest prefix matching (LPM) on the search key based on the signature field and the key field of each mapped entry in the mapped hash tables. |
| US09654396B2 |
Controller-less peer-to-peer distributed switch
In one embodiment, a device (e.g., a sync daemon) connects to peer nodes in a communication network. Each of the peer nodes has a switch that supports a flow table and an action table. The device facilitates a connection between a switch of a first peer node and a switch of a second peer node, and maintains the flow table and the action table of each of the peer nodes, such that the flow tables and the action tables are kept in synchronization with one another across each of the peer nodes via a distributed hash table. |
| US09654395B2 |
SDN-based service chaining system
A method for providing service chaining in a software-defined network (SDN)-based network system, the method including: receiving, at a controller, a first packet-in message from a first switch of a plurality of switches, which has received a service request packet from a user, to indicate that the first switch does not have a corresponding entry in a field extracted from the service request packet; extracting from the packet-in message both a service identifier that identifies a type of a service requested through the service request packet and a user identifier that identifies the user; and searching an entry database for an entry list that enables the service request packet to be forwarded to a network function list that corresponds to the service identifier and the user identifier, with reference to a service table, a user table, and a network function table which are associated with one another. |
| US09654394B2 |
Multi-tenant system, switch, controller and packet transferring method
A multi-tenant system is realized by the Tunneling protocol. The multi-tenant system includes a server apparatus on which a virtual machine with tenant identification data operates; an equipment whose tenant identification data cannot be recognized; a plurality of switches configured to transfer a packet based on flow entries; and a controller configured to set the flow entries to the switches. The plurality of switches includes a first switch connected with the server apparatus and a second switch connected with the equipment. The second switch rewrites the header of the packet sent from and received by the equipment based on an address translation table. Thus, the equipment becomes available. |
| US09654393B2 |
Method for transmitting information and device for carrying out the method
An electric motor and a motor control unit exchange information using at least one transfer signal, the information including motion state information of the electric motor and additional information transmitted via a transmission channel, where the motion state information is in the form of at least one base signal and the additional information is transmitted with the aid of the base signal. |
| US09654390B2 |
Method and apparatus for improving cloud routing service performance
In one embodiment, a method includes creating a logical router on a first router, the first router being supported on a first node, the logical router being created for a tenant. The method also includes determining whether a mode change is indicated, and migrating the logical router from the first router to the second router when it is determined that the mode change is indicated. The mode change is associated with migrating the logical router from the first router to a second router, where the second router is also supported on the first node. |
| US09654389B2 |
Order-sensitive communications in packet reordering networks
In one embodiment, a device in a network determines that a particular packet flow in the network is sensitive to packet reordering. The device determines whether a particular packet of the packet flow is to be routed differently than an immediately prior packet in the packet flow, in response to determining that the particular packet flow is sensitive to reordering. The device marks the particular packet as taking a different route than the immediately prior packet in the packet flow, prior to forwarding the marked packet and in response to determining that the particular packet is to be routed differently than the immediately prior packet in the packet flow. |
| US09654387B2 |
Techniques for privileged network routing
Techniques for privileged network routing are provided. As traffic is received at a gateway of a network backbone provider environment it is interrogated for predefined criteria. If the traffic satisfies the predefined criteria, then the information is routed within the network backbone provider environment to use a set of reserved and restricted resources to provide premium service for the traffic being routed through the network backbone provider environment. |
| US09654386B2 |
Apparatus, system, and method for reconfiguring point-to-multipoint label-switched paths
An apparatus may include a processor and a control plane that directs the processor to (1) detect that at least a portion of an initial branch path of a point-to-multipoint label-switched path has failed over to a failover route that rejoins the initial branch path at a network node and (2) establish an alternate branch path that merges with the initial branch path at the network node. The apparatus may also include a network interface and a data plane that uses the network interface to transmit data via the alternate branch path, where after the data plane begins transmitting data via the alternate branch path, the control plane instructs the network node to forward data from the alternate branch path rather than from the failover route. Various other apparatuses, systems, and methods are also disclosed. |
| US09654385B2 |
Multicast multipathing in an IP overlay network
The subject technology addresses the need in the art for improving utilization of network bandwidth in a multicast network environment. More specifically, the disclosed technology addresses the need in the art for extending multipathing to tenant multicast traffic in an IP overlay network, which enables the network to fully utilize available bandwidth for multicast traffic. In some examples, nodes in the overlay network may be connected by virtual or logical links, each of which corresponds to a path, perhaps through many physical links, in the underlying network. |
| US09654382B2 |
Use of alternate paths in forwarding of network packets
In non-minimal routing, a switch determines outgoing links for preferred paths (e.g. shortest paths). Then, for another node in a preferred path, the switch determines outgoing links for paths to that node in a modified network in which each link in a previously determined path to the node is cut off. Packets can be tunneled on non-preferred paths to that node. Other features and embodiments are also provided. |
| US09654376B2 |
System and method for managing virtual link state
A system and method of managing virtual link state includes receiving, at a first device, a first status update associated with the virtual link from a second device. The first status update includes a first management status value (RM) and a first operational status value (RO). The system and method further includes determining a second management status value (LM) associated with the first device, determining a second operational status value (LO) based on the first status update and the RM, transmitting a second status update for the virtual link to the second device, the second status update including the LM and the LO, and determining a state of the virtual link based on the RM, the RO, the LM, and the LO. The first device is configured to be coupled to the second device using a physical network link partitioned into a plurality of first virtual links including the virtual link. |
| US09654368B2 |
Network cost analysis
Embodiments generally disclosed herein include methods and systems for calculating incremental network costs between logical city pairs in a network (each city pair being in communication across the network via one or more physical links). For example, the method includes a cost analyzer that, for each physical link in the network, determines a steady state capacity allocation associated with each city pair in the network and, in the same vein, determines a restoration capacity allocation associated with each city pair in the network. The cost analyzer is capable of calculating an incremental cost per unit of traffic for a given city pair based on: i) the steady state capacity allocation and a restoration capacity allocation associated with a given city pair, as compared to, ii) the aggregate steady state capacity allocations and restoration capacity allocations associated with each city pair in the network. |
| US09654366B2 |
Apparatus and method for managing mobile device servers
A method that incorporates teachings of the present disclosure may include, for example, receiving at a media resource center a first pairing key from a first mobile device server and enabling the first mobile device to access at least one media device based on the first pairing key, where the at least one media device is operably coupled with the media resource center, where the first mobile devices provides media services by executing a web server application that utilizes the at least one media device, and where the first mobile device communicates with a second mobile device server to provide the media services. Other embodiments are disclosed. |
| US09654364B2 |
Bandwidth measuring device and non-transitory computer readable medium
A mobile terminal obtains a measurement value of a round-trip time in a communication channel used for communication with a server and a measurement value of a packet loss ratio in the communication channel (S502 and S503). Then, the mobile terminal determines whether or not a retransmission timeout is occurring in the server (S504, S505, and S506). If a retransmission timeout is occurring in the server, the mobile terminal calculates an estimate value of the bandwidth in the communication channel by using a special throughput equation including a timeout time (S507). On the other hand, if a retransmission timeout is not occurring in the server, the mobile terminal calculates an estimate value of the bandwidth by using a normal throughput equation which does not include a timeout time. |
| US09654363B2 |
Synthetic loss measurements using session numbers
A method and system for performing synthetic loss measurements (SLM) includes methods for single-ended and dual-ended synthetic loss measurements. The methods include maintaining a session number indicative of a physical network component at each maintenance point used to perform synthetic loss measurements. The session numbers are maintained according to a novel protocol and are used to detect a change in the network component, such as resulting from a protection switch event. The session numbers enable the synthetic loss measurements to continue irrespective of changes in the values for the session numbers and to remove errors when computing frame loss that may arise when physical network components change. The disclosed methods and systems may be used when a link aggregation group exists between a local maintenance point and a remote maintenance point. |
| US09654362B2 |
Methods, radio base station and radio network controller
A method performed in a first radio base station, RBS, in communication with a radio network controller, RNC. The RNC is configured for multi-flow HSDPA, High-Speed Downlink Packet Access, operation and packet data units, PDUs, are communicated toward a user equipment, UE, node via the first RBS and at least one second RBS. The method comprises: detecting PDU drop events and/or loss events; and communicating information from the RBS to the RNC, notifying of each detected PDU drop event and/or loss event. A corresponding RBS and RNC are also presented. |
| US09654356B2 |
Devices and methods supporting content delivery with adaptation services
A device supporting content delivery is configured to run at least one content delivery (CD) service of a plurality of CD services. The plurality of CD services include adaptation services. |
| US09654355B2 |
Framework supporting content delivery with adaptation services
A framework supporting content delivery includes a plurality of devices, each device configured to run at least one content delivery (CD) service of a plurality of CD services. The plurality of CD services include adaptation services. |
| US09654352B2 |
Brokering data access requests and responses
The present invention extends to methods, systems, and computer program products for brokering data access requests and responses. Aspects of the invention include a brokering pipeline that sequentially processes data access requests and data access responses. The brokering pipeline manages access authentications, request brokering, response rewrite, cache, and hosting multiple (e.g., business) entities. |
| US09654351B2 |
Granular permission assignment
A system and method for storing role definitions for cloud provider systems, receiving a first request to assign a user to a first role specifying a first cloud computing resource of a respective resource type, identifying a role definition corresponding to the first role that includes an action set permitted, and creating the first role for the user on the first cloud computing resource by associating the identified role definition with the first cloud computing resource and the user. A second request to assign the user to a second role is received specifying a second cloud computing of the respective resource type, and the second role is created for the user on the second cloud computing resource, where the identified role definition corresponds to the first and second roles, and wherein creating the second role includes associating the identified role definition with the first cloud computing resource and the user. |
| US09654350B2 |
Network device
Here, we have the following examples: (1) Integrating the NID functionality in to the small foot-print of an SFP Module, with one or more of the features below: a) Mounting a NID SoC IC to an existing SFP Printed Circuit Board (PCB); b) Using the power from the SFP module, without requiring separate external power; c) NID SoC having only 2 ports, each with its own MAC and possibly PHY layer; d) NID SoC having an embedded microprocessor, RAM and ROM; e) Running a Web portal or other remote login and management software on the NID SoC; f) Miniaturizing the NID to make it cheaper, with reduced cost of inventory, shipment, and installation; and/or g) Supporting one or more (multiple of/ many) functions in NID SoC, e.g., OAM or Shaping. (2) Building the NID functionality in a Dongle. Many other examples, configurations, applications, and variations are provided. |
| US09654349B2 |
System and method for functional elements
Systems and methods whereby, for example, one or more functional elements can be established and/or employed. Such functional elements might serve a number of purposes. For instance, such functional elements might be employable in interoperating with devices, software, and/or the like, in working with entities, and/or the like. Such functional elements may, for example, be arrangeable in an associative and/or hierarchical manner. |
| US09654341B2 |
Client device awareness of network context for mobile optimzation
In one embodiment, a method comprises obtaining, by a client device via a wireless data link with a wireless access point, information from a network device within a data network reachable via the wireless access point, the information describing network conditions associated with a service provided to the client device via the data network; and the client device optimizing a transmission control protocol (TCP) communication, via the wireless data link, for optimization of the service provided by the client device. |
| US09654340B2 |
Providing private access to network-accessible services
Techniques are described for managing communications for a managed virtual computer network overlaid on a distinct substrate computer network. The techniques may be used in situations in which a configurable network service provides managed virtual computer networks for clients and also provides one or more network-accessible services that are available to the managed virtual computer networks, with particular managed virtual computer networks being configured to provide local private access to at least one of the provided network-accessible services, despite those provided network-accessible services being located externally to the particular managed virtual computer networks. In some situations, a Lightweight Directory Access Protocol (“LDAP”) network-accessible service is provided, and a logical endpoint for the LDAP service is created within a managed virtual computer network to enable the multiple computing nodes of the managed virtual computer network to communicate with one or more LDAP computer servers from the LDAP service. |
| US09654338B2 |
CPE device installation and operation
Techniques described herein may be used to provide a self-installing customer premise equipment (CPE) device that is capable of automatically registering with, and participating in, a network of CPE devices in response to being powered on. The CPE device may be capable of logically combining a connection with a wireless cellular network and a wired network to increase bandwidth and reliability. The CPE device may also detect a power failure and report the power failure to a centralized server in order to facilitate the diagnosis and correction of performance issues caused by the power failure. |
| US09654337B2 |
Method and system for supporting distributed relay control protocol (DRCP) operations upon communication failure
A method supporting a distributed resilient network interconnect (DRNI) in a link aggregation group upon communication failure at a network device is disclosed. The method starts with determining that the network device no longer communicates with its neighbor network device. The network device then determines that its partner network device no longer communicates with the partner network device's neighbor network device. The network device determines that the first portal that the network device belongs to has a higher portal priority than the second portal that the partner network device belongs to, wherein each portal is assigned a portal priority, and it determines that the network device has a lower network device priority than the neighbor network device, wherein each network device is assigned a network device priority. Then the network device halts transmitting and receiving frames of the link aggregation group at the network device. |
| US09654335B2 |
System and method for provision and management of segmented virtual networks within a physical communications network
A network management method comprises configuring network domains (NDs) of a host communications network (HCN). Each ND provides a virtual network (VN) provisioned within the HCN for an enterprise customer, which forms a virtual communications subnetwork from which the enterprise customer provisions communications services. The HCN provides bandwidth over outroute and inroute channels of the HCN for the VNs. Outroute partitions are configured via outroute channels of the HCN and inroute partitions are configured via inroute channel groups configured within inroute channels of the HCN. Each outroute partition supports outroute bandwidth and each inroute partition supports inroute bandwidth. The outroute capacity partitions and the inroute capacity partitions are allocated to VNs to provide outroute and inroute capacity to the VN. Operator classifications are configured within the ND associated with the VC. Each classification specifies network operator capabilities allocated to VN operators assigned to that classification. |
| US09654329B2 |
Content distribution over a network
Distributive content delivery techniques are applied in a content delivery system. A content delivery overlay is generated as a function of delay times, bandwidth requirements, and throughput of a network. Helpers are added to the content delivery network as a function of delay times, bandwidth requirements, and throughput. Further, content can be transmitted without exchanging buffermaps or waiting for whole packets to be transmitted. |
| US09654322B2 |
Wireless communication device, integrated circuitry, and wireless communication method
A wireless communication device has an analog control loop circuitry that generates an analog control signal to adjust a phase of a voltage controlled oscillation signal, in accordance with a phase of a reception signal, a digital control loop circuitry that generates a digital control signal having a frequency determined by a frequency of a reference signal and a predetermined frequency setting code signal and having a phase opposite to a phase of the analog control signal, a voltage controlled oscillator that generates the voltage controlled oscillation signal, on the basis of the analog control signal and the digital control signal, and a data slicer that generates a digital signal obtained by digital demodulation of the reception signal, on the basis of a comparison result of the digital control signal and a predetermined threshold value. |
| US09654321B2 |
Method for reception improvement of a FM tuner in a common channel situation
Embodiments of methods and systems for reception improvement of FM tuners are provided. An example method according to the disclosure includes receiving one or more FM broadcast signals in a common channel (Co-C) situation and provides for receiving one or more FM broadcast signals, selecting a preferred signal and outputting said signal as an IF signal. When a Co-C situation occurs, the method calculates a correlation of the one or more signals and outputs the signal showing a larger consistency value. |
| US09654319B2 |
Non-contact communication apparatus
Provided is a non-contact communication apparatus which uses a conventional IC chip without any change, while eliminating the need to transmit power to the IC chip and allowing an increase in communication range. A non-contact communication apparatus connectable to an IC chip includes an antenna section, a first detection section that retrieves a first detection signal from a signal received by the antenna section, an amplitude modulating section that amplitude-modulates a clock signal using the first detection signal retrieved by the first detection section and that inputs the amplitude-modulated signal to the IC chip, a second detection section that retrieves a second detection signal from an output signal from the IC chip, a load modulating section that load-modulates a carrier retrieved from the antenna section using the second detection signal retrieved by the second detection section and that inputs the load-modulated carrier to the antenna section, and a power supply section. |
| US09654318B2 |
Apparatus and method for switching between receivers in communication system
An apparatus for switching between receivers according to a characteristic of a received signal in a communication system includes a radio frequency unit that modulates at least two signals received from transmission devices, and a Channel Impulse Response (CIR) shape comparison unit that determines characteristics of the modulated signals by using a CIR and selects a receiver according to the determined characteristics of the modulated signals. |
| US09654313B2 |
Wireless interference mitigation
Embodiments relate to apparatus for wireless interference mitigation within a first User Equipment (UE). The apparatus comprises at least one channel estimator for estimating a first channel transfer function associated with a first received signal designated for the first UE, and for estimating a second channel transfer function associated with a second received, interference, signal. A symbol estimator is responsive to the at least one channel estimator to process at least the first received signal to produce a symbol estimation. A demodulator, which is responsive to the channel estimator, demodulates the symbol estimation to an output representing a received data unit corresponding to the symbol estimation. The demodulator has a processing unit arranged to demodulate the symbol estimation using the first channel transfer function, the second channel transfer function and a respective modulation scheme for at least the first received signal. |
| US09654312B2 |
Layered detection method and apparatus for QAM-FBMC system
The present invention relates to a frequency region equalization method and an apparatus therefor in a cellular environment on the basis of a QAM-FBMC system. A method for receiving a signal by a receiver according to one embodiment of the present invention may include: performing channel estimation; comparing a minimum channel gain with a predetermined first threshold value; and performing layered detection when the minimum channel gain is smaller than the first threshold value. According to one embodiment of the present invention, a gain can be acquired in terms of a BER even while a structure of a symbol level equalizer is maintained. |
| US09654308B2 |
Systems and methods for carrier frequency offset estimation for long training fields
This disclosure describes systems, and methods related to determining carrier frequency offset of a wireless communication channel based on a determined phase difference. In some embodiments, an access point is caused to receive one or more streams comprising one or more encoded long training field (LTF) symbols over the wireless communication channel from one or more user devices. The access point then determines a first phase of the wireless communication channel upon receipt of a first LTF symbol, and determines a second phase of the wireless communication channel upon receipt of a second LTF symbol. The access point next determines a phase difference between the first phase and the second phase. Based on the determined phase difference, the access point determines a carrier frequency offset of the wireless communication channel. Lastly, the access point modifies the wireless communication channel based at least in part on the determined CFO. |
| US09654303B2 |
Method and apparatus for emulating network devices
Methods, apparatuses, data structures, and computer readable media are disclosed that perform emulated processing of packets communicated via a physical port between emulated network devices and real network devices. The emulated processing performs forward equivalence class classification on the packets. The forward equivalence class classification varies with the contents of the packets, and subsequent to the forward equivalence class classification the emulated processing varies with particular successful classifications resulting from the forward equivalence class classification. |
| US09654300B2 |
N-way virtual port channels using dynamic addressing and modified routing
Systems, methods, and non-transitory computer-readable storage media for dynamic addressing of virtual port channels is described. In some implementations, a virtual IP address can be dynamically generated based on which links in a virtual port channel are active. If the numbers of active links in the virtual port channel changes, the virtual IP address can be dynamically changed. The virtual IP address can be dynamically adjusted by changing the values of individual bits in the virtual IP address that correspond to links in the virtual port channel. The virtual IP address can be used as a tunnel end point address in a VXLAN environment. |
| US09654299B2 |
Execution framework for policy management
Embodiments of the present invention provide systems and methods of designing and implementing service policies in a telecommunications network. The policy management system includes interfaces operable to receive different subscriber information, an execution framework which includes policies which can be dynamically customized using one or more custom execution blocks, wherein the policies can receive the subscriber information through the interfaces and execute each policy based on the subscriber information. The method enables a network operator to dynamically update policies using customizable execution blocks and thereby change services associated with a particular policy as well as change the input factors (subscriber location, profile, etc.) available to that policy. |
| US09654297B2 |
Systems, methods and apparatuses for secure time management
The systems, methods and apparatuses described herein provide a computing environment that includes secure time management. An apparatus according to the present disclosure may comprise a non-volatile storage to store a synchronization time and a processor. The processor may be configured to generate a request for a current time, transmit the request to a trusted timekeeper, receive a digitally signed response containing a current, real-world time from the trusted timekeeper, verify the digital signature of the response, verify that the response is received within a predefined time, compare a nonce in the request to a nonce in the response, determine that the current, real-world time received from the trusted timekeeper is within a range of a current time calculated at the apparatus and update the synchronization time with the current, real-world time in the response. |
| US09654296B2 |
Handling sensor data
An apparatus, a system and a method for securing sensor data by a security engine circuitry of a system on chip (SoC). For example, the security engine may receive from a processor circuitry of the SoC an inter processor communication (IPC) request to secure sensor data, and may send to an integrated sensor hub (ISH) of the SoC an IPC request to receive sensor data. The ISH may collect sensor data from one or more internal and/or external sensors, and may send the collected sensor data to the security engine. The security engine may receive the collected sensor data from the ISH, may secure the collected sensor data, and may send secured sensor data to the processor circuitry. |
| US09654294B2 |
Non-repudiable atomic commit
Various examples are directed to systems and methods for coordinating a non-repudiable atomic commit transaction. A client may direct a transaction request to a transaction manager, where the transaction request comprises a transaction origin token. The transaction manager may create a transaction submission token and provide it to the client. The transaction manager may create a digest of a first work item to be executed by a first resource manager and send the digest to the first resource manager. The first resource manager may send the transaction manager a work item receipt token. The transaction manager may send the resource manager the transaction origin token. |
| US09654291B2 |
Authentication server, authentication system, authentication method, and program
In an authentication system, a mobile communication client transmits to an authentication server a bit signal that includes an image capture bit sequence obtained by capturing an image of a self-aware two-dimensional code having authentication information embedded in a correction area, and a number bit sequence that indicates a serial number of an authentication application program being stored in storage. The authentication server authenticates the user of the mobile communication client and the self-aware two-dimensional code. Subsequently, the authentication server transmits designated information expressed by the self-aware two-dimensional code to the mobile communication client, on the condition that the user and the self-aware two-dimensional code are successfully authenticated. Consequently, the mobile communication client is able to acquire the designated information expressed by the self-aware two-dimensional code. |
| US09654278B2 |
Data processing device, data processing method, and recovery device
A data processing device includes a signal processing unit that performs timing recovery of sampling timing, in such a manner that a sampled value is obtained at sampling timing which is set as a target by phase interpolation processing according to a feed-forward control, with respect to sampling data which is obtained from a recovery signal. |
| US09654275B2 |
Resource management method and system thereof
The present invention provides a resource management method and system thereof. The resource management method includes: judging whether the variation degree of work state of a communication system will result in the change of resource management information of the communication system or not, if so, then the resource management information is re-collected, wherein the resource management information includes the state, the interference state among links and service stream information relating to each node in the communication system; and determining the resource allocation strategy of the communication system according to the resource management information. |
| US09654274B2 |
Systems and methods for mitigating self-interference
Systems and methods for mitigating self-interference at a wireless device in a cellular communications network are disclosed. In one embodiment, a network node obtains one or more self-interference parameters for self-interference at the wireless device within a downlink frequency band utilized by the wireless device. In one embodiment, the one or more self-interference parameters include a frequency location of the self-interference, a strength of the self-interference, or both the frequency location and the strength of the self-interference. The network node then controls uplink transmission by the wireless device, downlink reception by the wireless device, and/or downlink transmission to the wireless device in such a manner that the self-interference at the wireless device is mitigated. |
| US09654273B2 |
Method of transmitting control signals in wireless communication system
A method of transmitting control signals in a wireless communication system includes multiplexing a first control signal with a second control signal in a slot, the slot comprising a plurality of orthogonal frequency division multiplexing (OFDM) symbols in time domain, the plurality of OFDM symbols being divided into a plurality of data OFDM symbols and a plurality of reference signal (RS) OFDM symbols, wherein the first control signal is mapped to the plurality of data OFDM symbols after the first control signal is spread by a base sequence in the frequency domain, the RS is mapped to the plurality of RS OFDM symbols, the second control signal is mapped to at least one of the plurality of RS OFDM symbols, and transmitting the first control signal and the second control signal in the slot. |
| US09654263B2 |
Method, apparatus, and system for transmitting control information
Embodiments of the present invention disclose a method, an apparatus, and a system for transmitting control information. The method includes: determining enhanced resource element group numbers in resource blocks, and determining, according to the resource element group numbers, positions of resource elements corresponding to enhanced resource element groups; interleaving the enhanced resource element group numbers, and determining an enhanced control channel element; determining, according to the enhanced control channel element and the positions of the resource elements corresponding to the enhanced resource element groups, positions of resource elements corresponding to the enhanced control channel element; and transmitting corresponding control information on the positions of the resource elements corresponding to the control channel element. The present invention alleviates a problem that channel frequency diversity is poor, and lowers the probability of loss of information of a terminal device. |
| US09654262B2 |
Methods providing benefit metrics for inter base station coordinated multipoint communications
A method may be provided to operate a first base station in a Radio Access Network including the first base station and a second base station. According to this method, a Reference Signal Received Power (RSRP) measurement list, a Coordinated Multipoint (CoMP) hypothesis, and a Benefit Metric may be communicated between the first and second base stations. |
| US09654258B2 |
Methods and systems for HARQ protocols
Methods described herein are for wireless communication systems. One aspect of the invention is directed to a method for a HARQ process, in which the HARQ process includes a first transmission of an encoder packet and at least one retransmission. The method involves allocating a transmission resource for each respective transmission. The method involves transmitting control information from a base station to a mobile station for each respective transmission. The control information includes information to uniquely identify the HARQ process and an identification of one of a time resource, a frequency resource and a time and frequency resource that is allocated for the transmission. In some embodiments of the invention, specific control information is signalled from a base station to a mobile station to enable RAS-HARQ operation. In some embodiments of the invention, retransmission signaling in included as part of regular unicast signaling used for both first transmission and retransmissions. In some embodiments of the invention, a 3-state acknowledgement channel and associated error recovery operation enables the base station and mobile station to recover from control signaling error and reduce packet loss. |
| US09654254B2 |
Method and device for reducing bit error rate in CDMA communication system
A method and a device for reducing a bit error rate in a Code Division Multiple Access (CDMA) communication system are described, wherein this method includes: a sample sequence Iin of an in-phase component signal I, and a sample sequence Qin of a quadrature component signal Q are obtained, and the signals are sent by a signal sending end; the obtained sample sequence Iin and the sample sequence Qin are divided into different groups according to a sample number Ns of a chip, a sum-average operation is performed on a signal in each group, and a corresponding signal group is determined, wherein, the signal group determined by performing the sum-average operation on the sample sequence Iin is WI, the signal group determined by performing the sum-average operation on the sample sequence Qin is WQ; and a signal in the signal group WI and the signal group WQ is grouped to determine a signal belonging to the same chip in the sample sequence which experiences the sum-average operation, and the determined signal is output. The disclosure solves a problem in the related art that a CDMA synchronization method possesses a wrong sampling situation, which results in a high bit error rate of a receiving end, and reduces the bit error rate. |
| US09654253B1 |
Apparatus and method for communicating data over an optical channel
An optical module processes first FEC (Forward Error Correction) encoded data produced by a first FEC encoder. The optical module has a second FEC encoder for further coding a subset of the first FEC encoded data to produce second FEC encoded data. The optical module also has an optical modulator for modulating, based on a combination of the second FEC encoded data and a remaining portion of the first FEC encoded data that is not further coded, an optical signal for transmission over an optical channel. The second FEC encoder is an encoder for an FEC code that has a bit-level trellis representation with a number of states in any section of the bit-level trellis representation being less than or equal to 256 states. In this manner, the second FEC encoder has relatively low complexity (e.g. relatively low transistor count) that can reduce power consumption for the optical module. |
| US09654251B1 |
Joint crosstalk-avoidance and error-correction coding for parallel data busses
System, methods, and apparatus are described that facilitate transmission/reception of data over a multi-line parallel bus. In an example, the apparatus transmits data bits over a parallel bus includes determining from a prior bus state, a plurality of free wires in the bus for a current bus state, where each free wire satisfies a crosstalk-avoidance constraint in the current bus state for all values of a bit transmitted on the free wire. The apparatus may encode a plurality of data bits using a crosstalk avoidance encoder to obtain a CAC-encoded word, compute an error detection or correction code for the CAC-encoded word, assign bits of the error detection or correction code to the plurality of free wires for transmission during the current bus state, and assign the CAC-encoded word to unassigned wires of the bus for transmission during the current bus state. |
| US09654245B2 |
Optimizing optical systems using code division multiple access and/or orthogonal frequency-division multiplexing
An optical receiver comprises an optical port configured to receive an encoded optical signal, and a demodulation block indirectly coupled to the port and comprising a multiplexer, wherein the multiplexer is configured to receive an encoded electrical signal, wherein the encoded electrical signal is associated with the encoded optical signal, and wherein the encoded electrical signal is encoded using a code division multiple access (CDMA) scheme, receive a code associated with the scheme, perform a dot multiplication of the encoded electrical signal and the code, and generate a differential voltage based on the dot multiplication. |
| US09654241B2 |
Systems and methods for signal frequency division in wireless communication systems
A system may include at least one antenna for receiving a first receive signal having a first signal diversity property and a second receive signal having a second signal diversity property. A first signal path may include a first frequency converter for downconverting the first receive signal to a first intermediate frequency signal having a first intermediate frequency. A second signal path may include a second frequency converter for downconverting the second receive signal to a second intermediate frequency signal having a second intermediate frequency. A transducer module may route the first receive signal to the first signal path, and route the second receive signal to the second signal path. A first N-plexer may select the first intermediate frequency signal or the second intermediate frequency signal for transmission to a cable, and to provide a data signal based on a selected intermediate frequency signal to the cable. |
| US09654240B1 |
Situation-based broadcast messages
An aspect includes receiving, by a computer processor, a sign up request from a mobile device for a message service. The message service is configured to distribute messages spanning a time period that corresponds to an event at which the mobile device is present. A further aspect includes determining, during the course of the time period, an occurrence of a condition for triggering a first message and sending the first message to the mobile device during the time period using a wireless internet browser based protocol. The first message is transmitted over a wireless network. A further aspect includes cancelling the message service at the expiration of the time period. |
| US09654228B2 |
Signal reception processing apparatus and method for processing received signal
A signal reception processing apparatus includes a digital signal processing unit that calculates a first Q value based on distribution of the symbols of the demodulated signal and distance between the symbols of the demodulated signal, and an error correction unit that outputs corrected signal as a demodulation electric signal, and calculates a second Q value based on an error rate at the time of the correction, and a control unit that calculates a penalty that indicates degradation quantity of signal quality caused by a nonlinear optical effect of an optical fiber based on the first Q value and the second Q value. |
| US09654222B1 |
Transmitters for optical narrowcasting
Systems and methods for optical narrowcasting are provided for transmitting various types of content. Optical narrowcasting content indicative of the presence of additional information along with identifying information may be transmitted. The additional information (which may include meaningful amounts of advertising information, media, or any other content) may also be transmitted as optical narrowcasting content. Elements of an optical narrowcasting system may include optical transmitters and optical receivers which can be configured to be operative at distances ranging from, e.g., 400 meters to 1200 meters. Moreover, the elements can be implemented on a miniaturized scale in conjunction with small, user devices such as smartphones, thereby also realizing optical ad-hoc networking, as well as interoperability with other types of data networks. Optically narrowcast content can be used to augment a real-world experience, enhance and/or spawn new forms of social-media and media content. |
| US09654219B2 |
Optical transceiving using self-homodyne detection (SHD) and remote modulation
A first optical transceiver node comprises: a laser configured to emit an input optical signal; a first splitter coupled to the laser and configured to split the input optical signal into a local oscillator (LO) optical signal and an unmodulated optical signal; and a receiver coupled to the first splitter and configured to: receive the LO optical signal from the first splitter; receive a modulated optical signal from a second optical transceiver node, wherein the modulated optical signal is a modulated version of the unmodulated optical signal; and perform phase noise cancellation of the modulated optical signal using the LO optical signal. |
| US09654218B2 |
RF ingress in fiber-to-the-premises
In a communication network, a node at a subscriber premises includes an input/output (I/O) port, and a device for monitoring a subscriber premises. The device includes an upstream signal path including a first switch, a downstream signal path, and a controller having an input/output (I/O) port coupled to the I/O port of the node, and a first output port. The first switch is coupled to the first output port selectively to complete the upstream signal path. |
| US09654213B2 |
Method and apparatus for testing transmission lines normally propagating optical signals
A portable apparatus for measuring optical powers of optical signals propagating concurrently in opposite directions in an optical transmission path between two elements, at least one of the elements being operative to transmit a first optical signal (S1) only if it continues to receive a second optical signal (S2) from the other of said elements, comprises first and second connector means for connecting the apparatus into the optical transmission path in series therewith, and propagating and measuring means connected between the first and second connector means for propagating at least the second optical signal (S2) towards the one of the elements, and measuring the optical powers of the concurrently propagating optical signals (S1, S2). The measurement results may be displayed by a suitable display unit. Where one element transmits signals at two different wavelengths, the apparatus may separate parts of the corresponding optical signal portion according to wavelength and process them separately. |
| US09654207B2 |
Modifying mobile device operation using proximity relationships
Described is a technology by which a mobile computing device such as a mobile telephone operates differently based on detected proximity to another mobile device with which the first mobile device has a defined relationship. For example, the first mobile device may transfer content to the second mobile computing device when proximity corresponds to a non-cellular communications coupling, such as Bluetooth® or Wi-Fi coupling. In this manner, content transfer is deferred until a non-cellular coupling exists. The mobile device (or both devices) may output a notification to indicate that the other mobile computing device has been detected within a threshold proximity, such as via GPS data or by being within the same cellular tower. The type and/or settings of an output notification may vary based on different thresholds. |
| US09654205B1 |
Systems, methods and apparatus for assembling a transport stream from satellite transponder signals
Various embodiments of systems, apparatus, and methods are described for assembling at least one transport stream from satellite transponder signals. In one example, the method includes capturing at least one satellite feed, the at least one satellite feed including a plurality of transponder signals; demodulating each of the plurality of transponder signals, each demodulated transponder signal corresponding to a transport stream including a plurality of input streams; parsing one or more selected streams from the plurality of input streams; assembling at least one new transport stream from the one or more selected streams; modulating the at least one new transport stream to generate at least one new transponder signal; adding the at least one new transponder signal to a channel stack; and transmitting the channel stack to a receiving device. |
| US09654204B2 |
Method and apparatus for content protection and billing for mobile delivery of satellite content
A satellite dish assembly may comprise a reflector, feed horn, receive module, and wireless module. The reflector and feed horn may be operable to receive satellite signals. The receive module may be operable to recover content from the received satellite signals. The wireless module may be operable to communicate the content directly to a mobile device via a wireless connection between the mobile device and the system. The wireless module may be operable to communicate directly with a service provider network via a wireless connection between the satellite dish assembly and the service provider network. The communications with the service provider network may be to obtain security information for descrambling and/or decrypting the content and/or for providing billing information. |
| US09654202B2 |
Satellite resource reservation and demand based pricing for satellite data broadcast services
A method of scheduling a transmission with a multi-beam satellite system receives, at a dynamic pricer, a request parameter that is associated with a request to transmit data via a multi-beam satellite system. The method determines a plurality of transmission solutions that satisfy the request parameter. The plurality of transmission solutions are transmitted, from the dynamic pricer, to a transmission requesting device. An indication is received, at the dynamic pricer, as to which particular transmission solution is selected by the transmission requesting device. The multi-beam satellite system is scheduled to transmit a payload in accordance with the selected particular transmission solution. A system is provided that operates the method. |
| US09654201B2 |
Method and a system of providing multi-beam coverage of a region of interest in multi-beam satellite communication
A method of providing multi-beam coverage of a Region of Interest (ROI) in a multi-beam satellite communication system in which a non-uniform traffic demand density is defined over said Region of Interest, the method including partitioning the Region of Interest into N>1 non-overlapping cells (V1-V10, Vi); and generating N satellite beams, each of the satellite beams providing coverage of a respective cell. The step of partitioning the Region of Interest into N>1 non-overlapping cells is performed in such a way that the traffic demand associated to the cells is substantially uniform. Advantageously, the cells form a Voronoi diagram defined over the Region of Interest, the satellite beams being pointed towards the cells of the Voronoi diagram. A satellite communication system implementing the method is also provided. |
| US09654199B2 |
Relay apparatus and communication method
An apparatus includes a memory; and a processor coupled to the memory and configured to execute a process, the process comprising, transferring a first acknowledge packet to the first device from the second device, the first acknowledge packet indicating that the second device anticipates receiving a first packet among the plurality of packets having been transferred from the first device to the second device; determining whether a second acknowledge packet indicates that the second device anticipates receiving the first packet, when the apparatus receives the second acknowledge packet from the second device after receiving the first acknowledge packet, and delaying transferring the second acknowledge packet to the first device when it is determined that the second device anticipates receiving the first packet. |
| US09654198B2 |
Node in a communication system with switchable antenna functions
Systems and methods of a node in a wireless communication system with switchable antenna functions are provided. In one exemplary embodiment, a method by a controller for configuring a switching network may include configuring the switching network for a first mode of operation associated with multiple-input, multiple-output (MIMO) communications. Further, the method may include configuring the switching network for a second mode of operation associated with beamforming communications. |
| US09654196B2 |
Methods of transmitting and/or receiving data transmissions using information relating to other data transmissions and related network nodes
A method may be provided to receive communications at a first node operating in a wireless communication network from a second node. The method may include receiving first information from the second node operating in the wireless communication network, wherein the first information is for a first data transmission from the second node to the first node. Second information may be received from the second node, wherein the second information is for a second data transmission to a third node operating in the wireless communication network. The first data transmission may be received at the first node from the second node using the first information for the first data transmission received from the second node and using the second information for the second data transmission received from the second node. Related transmission methods, network nodes, and wireless terminals are also discussed. |
| US09654194B2 |
Pre-coding method and pre-coding device
Disclosed is a precoding method comprising the steps of: generating a first coded block and a second coded block with use of a predetermined error correction block coding scheme; generating a first precoded signal z1 and a second precoded signal z2 by performing a precoding process, which corresponds to a matrix selected from among the N matrices F[i], on a first baseband signal s1 generated from the first coded block and a second baseband signal s2 generated from the second coded block, respectively; the first precoded signal z1 and the second precoded signal z2 satisfying (z1, z2)T=F[i] (s1, s2)T; and changing both of or one of a power of the first precoded signal z1 and a power of the second precoded signal z2, such that an average power of the first precoded signal z1 is less than an average power of the second precoded signal z2. |
| US09654186B2 |
Portable terminal
A portable terminal includes an antenna, a communication unit, an N-bit counter, and a gain change unit. The communication unit has two modes of an active mode in which the communication unit itself outputs carrier waves and a passive mode in which carrier waves output from another device are used, and is configured to attempt communication through electromagnetic induction by using the antenna with switching between the two modes being alternately made and to communicate without switching between the modes while communication is established. The N-bit counter is configured to output a value which varies by a unit number each time switching to at least one of the two modes is made in the communication unit. The gain change unit is configured to change a gain of a signal received at the antenna by the communication unit in accordance with a value output from the N-bit counter. |
| US09654185B2 |
Interactive method for communication with smart mobile device and interactive communication system using the same
An interactive method for communication with a smart mobile device and an interactive communication system using the same are provided. The interactive communication system comprises an external device and a smart mobile device. The external device comprises a microprocessor circuit and an AC magnetic emitter. The microprocessor circuit is for encoding specific data into an encoded signal. The AC magnetic emitter is for converting the encoded signal into an AC magnetic signal. The smart mobile device comprises an E-compass sensor. In addition, the smart mobile device stores a specific application program for acquiring a magnetic variation of the E-compass sensor. When the magnetic variation of the E-compass sensor is greater than a threshold variation, the AC magnetic signal is decoded through the specific application program to obtain the specific data. |
| US09654177B2 |
Power line data transmitter
A power line data transmitter includes a power circuit including a transistor and a modulation circuit. The transistor has an input terminal to which a voltage of a DC power source is inputted from a DC power line, a control terminal applied with a constant voltage bias, and an output terminal supplied with an electric power. The modulation circuit includes a power supply node, operates when the electric power is inputted, and outputs a data modulation signal. The power circuit functions as a data transmitter to perform a power line transmission. When the data modulation signal is outputted, (i) a potential of the output terminal changes, (ii) the power circuit changes a voltage between the control terminal and the output terminal, (iii) the power circuit changes another potential of the input terminal, and (iv) the power circuit superimposes the data modulation signal on the DC power line. |
| US09654176B2 |
Measurement, control and harvest optimization device for solar modules requiring fewer connections
System and method for enabling communications via a power line conveying DC power from multiple DC power sources such as solar panels. Power and communications are provided using a single combined power and communications line. Data communication signals received over the power line are detected and compared against power line voltage for processing received data and generating data for transmission. Remote units are self-powered using power harvesting of the data communication signals. |
| US09654174B2 |
Method and apparatus for managing a power line communication network in multi-flow environments
A method for managing a power line communication network in a multi-flow environment. The method includes determining an average throughput between each pair of nodes acting in isolation within the power line communication network, defining logical zones by grouping each pair of nodes if the average throughput between the pair of nodes exceeds a first threshold, wherein the logical zones include a plurality of strongly coupled zones. The method further includes determining an aggregate throughput for a pair of flows between randomly selected pairs of nodes acting concurrently between the plurality of strongly coupled zones, determining a plurality of pair of flows that can be concurrently operated when the aggregate throughput exceeds the average throughput, estimating a resulting throughput of the plurality of pair of flows that can be concurrently operated, and optimizing a schedule for the plurality of pair of flows based on the resulting throughput. |
| US09654167B1 |
Smartphone case system
A smartphone case system includes an electronic device that has a transceiver. The transceiver is in electrical communication with a communication network. A case is provided and the electronic device is positioned in the case. Thus, the case protects the electronic device. A strap is coupled to the case and the strap is spaced from the case. Thus, a hand may be passed between the strap and the case thereby facilitating the case to be gripped. A security chip is embedded within the case. The security chip is electrical communication with the communication network. Moreover, the security chip inhibits an unauthorized user from electronically gaining identity data from the electronic device. |
| US09654164B2 |
Removable electronic device case with supplemental wireless circuitry
A removable case may receive an electronic device. A male connector in the case may mate with a female connector in the device. A battery in the case may supply power to the device through the male connector. The electronic device may have an antenna formed from peripheral conductive housing structures and an antenna ground. The antenna may include a slot antenna resonating element. The case may have supplemental antenna structures such as a metal patch that overlaps an end of the slot antenna resonating element to retune the slot antenna resonating element to a desired operating frequency after being detuned by dielectric loading from the case. The supplemental antenna structures may overlap antennas of other types and may include tunable circuitry that is adjusted based on information received from the electronic device. |
| US09654163B2 |
Visible light transceiver glasses
An LED light and communication system includes Visible Light Communication Transceiver Glasses having at least one projector, lense(s), and optical transceiver, the optical transceiver including a light support and a processor. The light support has at least one light emitting diode and at least one photodetector attached. The processor is in communication with the at least one light emitting diode and the at least one photodetector. The processor is capable of illuminating the at least one light emitting diode to create at least one light signal which is not observable to the unaided eyes of an individual. The second light signal includes at least one data packet. The processor may generate a signal for the projector to display information on the lense(s). |
| US09654158B2 |
Circuits and methods for reducing an interference signal that spectrally overlaps a desired signal
Under one aspect, a method is provided for processing a received signal, the received signal including a desired signal and an interference signal that spectrally overlaps the desired signal. The method can include obtaining an amplitude of the received signal. The method also can include obtaining an average amplitude of the received signal based on at least one prior amplitude of the received signal. The method also can include subtracting the amplitude from the average amplitude to obtain an amplitude residual. The method also can include, based upon an absolute value of the amplitude residual being less than or equal to a first threshold, inputting the received signal into an interference suppression algorithm so as to generate a first output including the desired signal with reduced contribution from the interference signal. |
| US09654156B2 |
Nonlinear compensating apparatus and method, transmitter and communication system
A nonlinear compensating apparatus and method, a transmitter and a communication system are provided. The apparatus includes a preprocessor configured to preprocess a transmitted signal according to a pre-obtained preprocessing coefficient and a predistorter configured to perform predistortion for the preprocessed signal, and a result of comparison of a characteristic parameter of the signal that has been preprocessed and then predistorted with that of the transmitted signal satisfies a predetermined condition. By preprocessing the transmitted signal at the transmitter end, the embodiments of the present disclosure may perform efficient nonlinear compensation only needing to measure at the transmitter end and without needing to perform many times of measurement at the receiver end, and may lower complexity of circuits of the communication system and complexity of calculation. |
| US09654153B2 |
Microwave radio transmitters and related systems and methods
This disclosure provides a microwave radio transmitter apparatus comprising an antenna arrangement and a precoder module connected to the antenna arrangement. The precoder module comprises an estimation module. The precoder module is configured to receive a number N of signals s1, . . . , sN and to generate N phase-adjusted transmit signals TX1, . . . , TXN. The antenna arrangement comprises N antenna elements ai, i=1, 2, . . . , N. Each antenna element ai is configured to obtain a respective phase-adjusted transmit signal TXi from the pre-coder and to transmit the respective phase-adjusted transmit signal TXi. The precoder module is configured to obtain an observation receive signal RX, the observation receive signal comprising signals transmitted from the N antenna elements. The estimation module is configured to estimate for each antenna element ai a phase difference between the corresponding transmit signal TXi and the observation receive signal RX. The precoder module is configured to adjust each transmit signal based on the estimated phase difference. |
| US09654151B2 |
Radio frequency front end circuitry with improved primary transmit signal isolation
RF front end circuitry includes primary transceiver circuitry associated with a primary antenna and secondary receiver circuitry associated with a secondary antenna. Generally, the primary transceiver circuitry and the primary antenna are located on one end of a mobile communications device, while the secondary receiver circuitry and the secondary antenna are located at an opposite end of the device. Cross-coupling connection lines run between the antenna switching circuitry for the primary antenna and the secondary antenna, and are reused to send a portion of primary RF transmit signals from the primary transceiver circuitry to the secondary receiver circuitry so that primary RF transmit signals coupled into the secondary receiver path via antenna-to-antenna coupling can be reduced. |
| US09654150B2 |
Module with duplexers coupled to diplexer
A module includes: a first duplexer including a common terminal coupled to a first terminal of a diplexer, the diplexer including an antenna terminal coupled to an antenna, the first terminal, and a second terminal; and a second duplexer including a common terminal coupled to the second terminal of the diplexer and having a passband different from a passband of the first duplexer, wherein a frequency at which a reactance component of an impedance is approximately zero and the impedance is less than a reference impedance is not located in a passband of the first duplexer, the impedance being an impedance when the second duplexer is viewed from a node at which the antenna terminal is divided into the first terminal and the second terminal in the diplexer. |
| US09654148B2 |
Reconfigurable ECC for memory
According to one general aspect, an apparatus may include a memory and a reconfigurable error correction array. The memory may be configured to store data. The reconfigurable error correction array may be configured to provide a plurality of levels of error correction to the memory based, at least in part, upon a number of errors detected within the memory. |
| US09654143B2 |
Consecutive bit error detection and correction
Embodiments of an invention for consecutive bit error detection and correction are disclosed. In one embodiment, an apparatus includes a storage structure, a second storage structure, a parity checker, an error correction code (ECC) checker, and an error corrector. The first storage structure is to store a plurality of data values, a plurality of parity values, and a plurality of ECC values, each parity value corresponding to one of the plurality of data values, a first bit of each parity value corresponding to a first of a plurality of portions of a corresponding data value, wherein the first of the plurality of portions of the corresponding data value is interleaved with a second of the plurality of portions of the corresponding data value, wherein a second bit of each parity value corresponds to a second of the plurality of portions of the corresponding data value, each ECC value corresponding to one of the plurality of data values. The parity checker is to detect a parity error in a data value stored in the first storage structure using a parity value corresponding to the data value. The ECC checker is to generate a syndrome. The error corrector is to detect and correct consecutive bit errors in the data value using the syndrome. |
| US09654141B2 |
Memory devices and systems configured to adjust a size of an ECC coverage area
Memory devices and systems having an array of memory cells arranged in a plurality of sectors and a plurality of ECC coverage areas, and control circuitry configured to adjust a size of one or more of the ECC coverage areas. |
| US09654137B1 |
Elastic data packer
This disclosure relates to compressing and/or decompressing a group of similar data units, such as a table or queue of data units processed by a networking device or other computing apparatus. Each data unit in the group may only have values for fields in a master set. The described systems are particularly suited for hardware-level processing of groups of sparsely-populated data units, in which a large number of the data units have values for only a small number of the fields. In an embodiment, non-value carrying fields in a data unit are compressed based on a compression profile selected for the data unit. The compression profile indicates, for each master field, whether the compressed data unit includes a value for that field. Non-value carrying fields are omitted from the compressed data unit. The compression profile also permits compression of value-carrying fields using variable-width field lengths specified in the profile. |
| US09654133B2 |
Microprocessor-assisted calibration for analog-to-digital converter
Analog-to-digital converters (ADCs) can have errors which can affect their performance. To improve the performance, many techniques have been used to compensate or correct for the errors. When the ADCs are being implemented with sub-micron technology, ADCs can be readily and easily equipped with an on-chip microprocessor for performing a variety of digital functions. The on-chip microprocessor and any suitable digital circuitry can implement functions for reducing those errors, enabling certain undesirable artifacts to be reduced, and providing a flexible platform for a highly configurable ADC. The on-chip microprocessor is particularly useful for a randomized time-interleaved ADC. Moreover, a randomly sampling ADC can be added in parallel to a main ADC for calibration purposes. Furthermore, the overall system can include an efficient implementation for correcting errors in an ADC. |
| US09654131B1 |
Capacitor order determination in an analog-to-digital converter
An analog-to-digital converter (ADC) includes a digital-to-analog converter (DAC) that has a configurable capacitor array. Based on measurements of differential nonlinearity (DNL) and/or integral nonlinearity (INL) error by an external test computer system, an order for use of the DAC's capacitors can be determined so as to reduce DNL error aggregation, also called INL. The DAC includes a switch matrix that can be programmed by programming data supplied by the test computer system. |
| US09654129B2 |
Signal processing device
There is provided a signal processing device comprising a combination unit (3) configured to combine plural element signals based on plural physical quantity signals including signal components in accordance with desired physical quantities, respectively, by the number of times equal to or greater than a number of the plural physical quantity signals, and to output combined signals different from each other; a measuring unit (4) configured to sequentially receive the combined signals output from the combination unit (3); and a computing unit (5) configured to compute signal components based on the desired physical quantities from signals that are generated based on the combined signals sequentially output from the measuring unit. |
| US09654126B2 |
Systems and methods for providing a pipelined analog-to-digital converter
Systems comprising: a first MDAC stage comprising: a sub-ADC that outputs a value based on an input signal; at least two reference capacitors that are charged to a Vref; at least two sampling capacitors that are charged to a Vin; and a plurality of switches that couple the at least two reference capacitors so that they are charged during a sampling phase, that couple the at least two sampling capacitors so that they are charged during the sampling phase, that couple at least one of the reference capacitors so that it is parallel to one of the at least two sampling capacitors during a hold phase, and that couple the other of the at least two sampling capacitors so that it couples the at least one of the reference capacitors and the one of the at least two sampling capacitors to a reference capacitor of a second MDAC stage. |
| US09654123B1 |
Phase-locked loop architecture and clock distribution system
One embodiment relates to an integrated circuit including multiple PMA modules, a plurality of multiple-purpose PLLs, multiple reference clock signal inputs, and a programmable clock network. Another embodiment relates to a fracture-able PLL circuit. The fracture-able PLL circuit includes a first phase-locked loop circuit generating a first frequency output, a second phase-locked loop circuit; arranged to generate a second frequency output, and a plurality of shared output resources. Reconfigurable circuitry is arranged so that either of the first and second frequency outputs is receivable by each of the plurality of shared output resources. Another embodiment relates to an integrated circuit including a first strip of PLL circuits on a first side of the integrated circuit, and a second strip of PLL circuits on a second side of the integrated circuit which is opposite from the first side. Other embodiments and features are also disclosed. |
| US09654122B2 |
Dither-less multi-stage noise shaping fractional-N frequency synthesizer systems and methods
A fractional-N divider of a frequency synthesizer is driven by a dither-less and seed-less multi-stage noise shaping (MASH) modulator to alleviate fractional spurious tones introduced by the cyclic train of division ratios from delta-sigma modulators. The MASH modulator includes at least two cascaded dither-less delta-sigma modulators where each modulator includes a first feedback loop the generates the modulator feedback signal, a second feedback loop that disrupts fractional spurious tones and a third feedback loop that provides approximately zero static error. The MASH modulator further includes a combining circuit delays at least one code sequence from at least one of the delta-sigma modulators and that combines the code sequence generated by each of the delta-sigma modulators and at least one delayed code sequence. |
| US09654121B1 |
Calibration method and apparatus for phase locked loop circuit
An integrated circuit apparatus for calibrating a phase locked loop (PLL) circuit that includes a phase comparator configured to receive a reference clock signal and a feedback clock signal and generate a phase error signal, a variable frequency oscillator configured for receiving the phase error signal and generating a corresponding fast clock signal at an output of the variable frequency oscillator, and a divider that is configured to divide the fast clock signal by a divisor (N) so as to generate the feedback clock signal, includes a calibration circuit. The calibration circuit is coupled to receive the reference clock signal and the fast clock signal and to provide a frequency band selection signal to the variable frequency oscillator. The calibration circuit includes a counting circuit for counting a number of cycles of the fast clock signal over a period of time defined by a number of cycles (M) of the reference clock signal. The calibration circuit also includes a selection block for performing a convergence test using the counted number of fast clock cycles, N, and M. The selection block generates the frequency band selection signal in accordance with the results of the convergence test to select a next candidate calibrated frequency band. |
| US09654118B2 |
Phase-rotating phase locked loop and method of controlling operation thereof
A phase-rotating phase locked loop (PLL) may include first and second loops that share a loop filter and a voltage controlled oscillator in order to perform the operation of a phase-rotating PLL, the first and second loops configured to activate in response to an enable signal. The PLL may further include a phase frequency detection controller configured to provide the enable signal to the first and second loops in response to a transition of a coarse signal that may be applied as a digital code. |
| US09654117B1 |
Digital phase-locked loop having de-coupled phase and frequency compensation
An integrated circuit device implementing a digital phase-locked loop includes a measure period component, an averager component, a generator component, and a compensator component. In the digital phase-locked loop implementation, phase compensation and frequency compensation are separated from one another. |
| US09654116B1 |
Clock generator using resistive components to generate sub-gate delays and/or using common-mode voltage based frequency-locked loop circuit for frequency offset reduction
A clock generator has a multi-phase controllable oscillator. The multi-phase controllable oscillator includes oscillator core circuits, and has phase nodes at which clock signals with different phases are generated, respectively. Each oscillator core circuit includes a resistive component and an inverter. The resistive component is coupled between a first phase node and a second phase node of the multi-phase controllable oscillator, wherein clock signals generated at the first phase node and the second phase node have adjacent phases. The resistive components of the oscillator core circuits are cascaded in a ring configuration. The inverter receives an input feedback clock signal from one phase node of the multi-phase controllable oscillator, and generates an output feedback clock signal to the second phase node according to the input feedback clock signal. |
| US09654111B1 |
Systems and methods for protecting data using reconfigurable logic paths
Various embodiments of the invention allow to protect data in a logic circuit from being detected by commonly known observation methods. In certain embodiments, this is accomplished by selecting a set of reconfigurable logic blocks within the logic circuit to form a routing path in such a manner that the circuit performs a given function while making it virtually impossible to follow data through the circuit as the data is being processed. The routing path may be selected in a random or pseudorandom fashion, for example, in response to detecting an environmental change. In some embodiments, known data is injected into the logic path and the output is compared to a known value. If the result is incorrect, for example, because a section of the hardware ceased to properly perform due to a faulty circuit component, signals are routed through an operational part of the circuit to provide a different and valid logic path, while avoiding faulty logic gates. |
| US09654106B1 |
Dynamic digital input filtering
A dynamic digital filtering system for detecting electrical noise in a discrete I/O circuit. The dynamic digital filtering system has a controller for monitoring the logic signal produced by a logic device monitoring a remote I/O device. The logic device includes a circuit for dynamically adjusting the impedance across a power terminal and a terminal receiving a binary signal from the I/O device. Upon a change of state of the monitored logic signal the controller commands the impedance adjusting circuit to momentarily change its input impedance to determine if the binary signal responsible for the monitored change of state of the logic signal was true or false. If the monitored logic signal does not change state during the momentary change in impedance the binary signal will be verified as “true”. If the monitored logic signal does change state during the momentary change in impedance the binary signal will be considered as “false”. |
| US09654104B2 |
Resistive force sensor with capacitive discrimination
A resistive force sensor with capacitive discrimination is disclosed. According to an example of the disclosure, a sensor is directed to detect resistance and capacitance in an alternating fashion, the resistance indicating a force being applied to an input area of a device, and the capacitance indicating a proximity of a body part to the input area of the device, and the detected resistance and capacitance are utilized to determine whether the body part has pressed the input area of the device. |
| US09654103B2 |
Proximity switch assembly having haptic feedback and method
A proximity switch assembly and method for detecting activation of a proximity switch assembly and providing feedback is provided. The assembly includes a plurality of proximity switches each comprising a proximity sensor providing a sense activation field. The assembly also includes control circuitry processing a signal associated with the activation field of each proximity sensor and detecting a finger located between two proximity switches. The assembly further includes a feedback device generating a feedback when the finger is detected between the two proximity switches. In addition, the assembly may detect speed of movement of a finger interfacing with the proximity switches and vary the feedback based on the detected speed. |
| US09654101B2 |
Integrated circuit power rail multiplexing
An integrated circuit (IC) is disclosed herein for power management through power rail multiplexing. In an example aspect, an IC includes a first power rail, a second power rail, and a load power rail. The IC also includes a first set of transistors including first transistors that are coupled to the first power rail and a second set of transistors including second transistors that are coupled to the second power rail. The IC further includes power-multiplexer circuitry that is configured to switch access to power for the load power rail from the first power rail to the second power rail by sequentially turning off the first transistors of the first set of transistors and then sequentially turning on the second transistors of the second set of transistors. |
| US09654100B2 |
Output buffer, and source driver and display device including the same
Disclosed is an output buffer. The output buffer includes a first amplifier configured to amplify an input signal, and output first to fourth amplified signals according to results of the amplification, a first transistor to receive the first amplified signal, a second transistor to receive the second amplified signal, a third transistor to receive the third amplified signal, a fourth transistor to receive the fourth amplified signal, a first node, connected to drains of the first and second transistors, a second node, connected to drains of the third and fourth transistors, an output node connected to the first and second nodes, and a first controller configured to selectively supply a control voltage to the gates of the first to fourth transistors in response to a control signal. |
| US09654097B2 |
Signal transmission circuit, switching system, and matrix converter
A signal transmission circuit includes an input terminal to which an input signal is input, a high-frequency oscillation circuit that outputs a high-frequency wave, a switching mixing circuit that modulates the high-frequency wave according to the input signal to generate modulated signals including first to third modulated signals, a first output terminal from which the first modulated signal is output, a second output terminal from which the second modulated signal is output, and a third output terminal from which the third modulated signal is output. While the first modulated signal is output from the first output terminal, the second and third modulated signals are not output. While the second modulated signal is output from the second output terminal, the first and third modulated signals are not output. While the third modulated signal is output from the third output terminal, the first and second modulated signals are not output. |
| US09654096B1 |
Low variation power-on-reset circuit
A power-on-reset (POR) circuit for a system-on-chip (SOC) includes a biased switching element having a source, drain, and gate, with the source being connected to a supply voltage and the drain and gate being connected to a control line. The POR circuit further includes a first delay switching element having a source connected to a reduced supply voltage, a gate connected to the control line, and a drain, and an inverter having an input and an output, with the input being connected to the drain of the first delay switching element. The inverter includes a first CMOS inverter coupled between the supply voltage and a reference voltage. A first capacitor is coupled between the inverter input and the reference voltage. A second capacitor coupled between the inverter input and an output of the first CMOS inverter. |
| US09654094B2 |
Semiconductor switch circuit and semiconductor substrate
According to one embodiment, a semiconductor switch circuit includes a semiconductor substrate, an insulating film, a semiconductor layer, a first wiring line, a semiconductor switch unit, and a first conductor. The insulating film is provided on the semiconductor substrate. The semiconductor layer is provided on the insulating film. The first wiring line is provided above the insulating film. The semiconductor switch unit is provided on the semiconductor layer and is electrically connected to the first wiring line. The first conductor is provided between the first wiring line and the semiconductor substrate. |
| US09654090B2 |
Systems and methods for clock distribution in a die-to-die interface
Circuits for die-to-die clock distribution are provided. A system includes a transmit clock tree on a first die and a receive clock tree on a second die. The transmit clock tree and the receive clock tree are the same, or very nearly the same, so that the insertion delay for a given bit on the transmit clock tree is the same as an insertion delay for a bit corresponding to the given bit on the receive clock tree. While there may be clock skew from bit-to-bit within the same clock tree, corresponding bits on the different die experience the same clock insertion delays. |
| US09654089B2 |
Window reference trimming for accessory detection
This document discusses, among other things, a detection circuit configured to receive an output of a window comparator over a range of input values and to measure a difference between first and second thresholds of the window comparator, and a trim circuit configured to adjust at least one of the first or second thresholds using the measured difference between the first and second thresholds. |
| US09654088B2 |
Hysteresis circuit
A hysteresis circuit includes a current comparator arranged to receive an input current signal. A reference current source is coupled to the current comparator and arranged to provide a reference current. A hysteresis current source is arranged to provide a hysteresis current. A switch is coupled between the reference current source and the hysteresis current source. At least one buffer is coupled to the current comparator and arranged to provide an output voltage signal. The output voltage signal has a first voltage if the input current signal is greater than a sum of the reference current and the hysteresis current and the output voltage signal has a second voltage if the input current signal is less than the reference current. |
| US09654086B1 |
Operational amplifier with current-controlled up or down hysteresis
Disclosed is an op-amp circuit with current-controlled hysteresis that is insensitive to PVT variations. In the circuit, a digital output signal is output from an output buffer based on the output voltage at an output node of an op-amp. A current source is connected to the input side of the op-amp or one of multiple current sources is selectively connected to the input side and enabled when the digital output signal has a high value to provide falling edge hysteresis. Alternatively, a current source is connected to the reference side of the op-amp or one of multiple current sources is selectively connected to the reference side and enabled when the digital output signal is low to provide rising edge hysteresis. Alternatively, current sources are connected to both the input and reference sides and selectively controlled to provide either falling or rising edge hysteresis. |
| US09654083B2 |
Resonator element having a pair of vibrating arms with wide portions and arm portions
A resonator element includes a base portion and a pair of vibrating arms that are provided integrally with the base portion, are aligned in an X-axis direction, and extend in a Y-axis direction from the base portion. Each of the vibrating arms includes an arm portion and a wide hammerhead that is located on the free end side of the arm portion and has a greater length in the X-axis direction than the arm portion. Assuming that the length of the vibrating arm in the Y-axis direction is L and the length of the hammerhead in the Y-axis direction is H, the relationship of 1.2% |
| US09654082B2 |
Vibrator, oscillator, electronic device for controlling internal resonance between inherent vibration modes
A vibrator includes a vibrator element and a base on which the vibrator element is installed. In addition, when n is set to a natural number equal to or greater than 2, and j is set to a natural number equal to or greater than 1 and equal to or less than n, the vibrator element includes n inherent vibration modes having resonance frequencies different from each other, and when a resonance frequency of a main vibration of the vibrator element in the n inherent vibration modes is set to ω1 in a relationship between an arbitrary integer kj and a resonance frequency ωj corresponding to each of the n inherent vibration modes, the following three expressions are all satisfied. Δω ≡ ( ∑ j = 2 n k j ω j - k 1 - ω 1 ) / ω 1 ω 1 ≥ 0.1 3 ≤ ∑ j = 1 n k j ≤ 10 |
| US09654077B2 |
Method and apparatus for reducing noise due to path change of audio signal
A method and an apparatus for reducing noise due to a path change of an audio signal output from a device are provided. The method includes determining an input period for canceling the noise by using a time point, at which the path change is sensed, as a reference, when sensing the path change of the audio signal; low-pass filtering the audio signal in the determined input period; and interpolating a first partial signal, which is the low-pass filtered audio signal in a first predetermined period that starts from a start time point of the determined input period, and a second partial signal, which is the low-pass filtered audio signal in a second predetermined period that ends at an end time point of the determined input period, within the determined input period. |
| US09654069B2 |
Reduced crosstalk and matched output power class D audio amplifier with oppositely polarized triangle waves
A multi-channel Class D audio amplifier is provided to substantially reduce channel-to-channel crosstalk by employing in each channel a local triangle ramp generator controlled by a single global digital timing signal. The noise critical timing/integrating capacitor for the triangle ramp generator resides locally in each channel and adjacent to the PWM comparator of that channel and referenced to the local ground of that channel. The amplifier can also include a duty cycle limitation circuit to limit output power availability depending on the impedance of any attached loads (speakers). |
| US09654062B2 |
Return path noise reducing amplifier with bypass signal
An amplifier system an amplified path and a bypass path for carrying an RF signal. A switch in the amplified system routes the RF signal through the amplified path in response to a normal condition in the amplifier system, and routes the RF signal through the bypass path in response to an abnormal condition in the amplifier system. The amplified path includes an amplified forward circuit and a return circuit. The amplified forward circuit has an amplifier, and the return circuit has a return amplifier and detection circuitry for providing power to the return amplifier. The detection circuitry provides power to the return amplifier in response to a normal condition in the return circuit, and removes power from the return amplifier in response to an abnormal condition in the return circuit. |
| US09654056B2 |
Switched mode converter with low-voltage linear mode
A power converter may include a power inductor, a plurality of switches arranged to sequentially operate in a plurality of switch configurations, an output for producing the output voltage, wherein a first switch is coupled to a first output terminal of the output and a second switch is coupled to a second output terminal of the output, and a linear amplifier coupled to the output. The controller may be configured to, in a linear amplifier mode of the power stage, enable the linear amplifier to transfer electrical energy from an input source of the power stage to the load, and in at least one mode of the power stage other than the linear amplifier mode, sequentially apply switch configurations from the plurality of switch configurations to selectively activate or deactivate each of the plurality of switches in order to transfer the electrical energy from the input source to the load. |
| US09654055B2 |
Radio-frequency high power amplifier with broadband envelope tracking by means of reversed buck converter
A radio-frequency power amplifier with envelope tracking, having a power RF amplifying device for amplifying a RF signal and a switching DC/DC converter for providing the power RF amplifying device with a DC power supply at a voltage level (VSUPP) proportional to an envelope of the RF signal, wherein the switching DC/DC converter has a reversed buck topology. Advantageously the switching device is a N-type GaN Field Effect Transistor having its drain connected to the ground. |
| US09654054B1 |
Device and method for saturation prevention by transfer function modulation associated with conditioning of electrical current or voltage
The present general inventive concept is directed to provide a saturation prevention method that utilizes transfer function modulation to continuously and precisely condition signals over more than four orders of magnitude from a signal source. To avoid signal conditioning error and large transient behavior due to range switching, continuous conditioning of all ranges without saturation over the entire large input dynamic range is employed. The use of transimpedance amplifiers in an example embodiment induces negligible loading on the signal source such that the integrity of the original signal is fully maintained, enabling precise signal conditioning. The ratio of gain to input impedance with a transimpedance amplifier is orders of magnitude larger than other typical methods of signal conditioning, making these amplifiers optimum for the saturation prevention method. An example embodiment utilizes the saturation prevention method to maintain the expected signal gain and a low impedance load for the signal source to ensure the desired accuracy of the signal conditioning. |
| US09654046B2 |
Reduced size power inverter suitable for a vehicle
A power inverter comprises at least a box-shaped housing; and a power module, a smoothing capacitor, a base plate made of a flat plate, and a rotating electric machine control circuit board arranged in order in the housing. The base plate is arranged with the fringes fixed to the inner wall surfaces of the housing, and the smoothing capacitor and rotating electric machine control circuit board are fixed. |
| US09654044B2 |
Impact rotation tool
An impact rotation tool includes a motor, a switching element that performs a switching operation based on a PWM control signal, and a controller that performs PWM control on the motor with the switching operation of the switching element. The controller includes a PWM control unit that generates the PWM control signal, an impact detector that detects whether or not an impact has been generated, and a control frequency switch unit that selects a control frequency of the PWM control signal from a first control frequency, which is in an audible range, and a second control frequency, which is higher than the frequency in the audible range. The controller outputs a PWM control signal having the second frequency when detecting that an impact has not been generated and outputs a PWM control signal having the first frequency when detecting that an impact has been generated. |
| US09654042B2 |
Apparatus for controlling induction machine
An apparatus for controlling an induction motor is provided, the apparatus generates generating a d-axis current command and a q-axis current command of a torque command, estimating speed of a rotor of the motor, and correcting the d-axis and q-axis current commands by using the estimated speed, to enhances the rotor speed and position estimation performance by increasing the slip frequency. |
| US09654041B2 |
Control apparatus for internal combustion engine
A control apparatus for an internal combustion engine is provided. The control apparatus includes an ECU. The ECU is configured to change, in a stepped manner, an air-fuel ratio of the internal combustion engine so as to change over a combustion mode of the internal combustion engine between lean combustion and stoichiometric combustion, when an operating point of the internal combustion engine satisfies a first changeover condition that is defined by a rotational speed and a torque of the internal combustion engine. The first changeover condition is defined by the rotational speed and the torque that correspond to a predetermined intake air amount at which a thermal efficiency of the internal combustion engine is maintained before and after changeover of the combustion mode. |
| US09654038B2 |
Control device and method for controlling electric motor
A control device of an electric motor includes: an operating state setting unit configured to set an operating state; a maximum output acquiring unit configured to acquire maximum output of the electric motor that is preset according to the operating state set; a speed detecting unit configured to detect a speed of the electric motor; a torque limit value calculating unit configured to calculate a torque limit value based on the speed and the maximum output; and a torque limiting unit configured to limit torque of the electric motor by the torque limit value when accelerating the electric motor. |
| US09654037B2 |
Multi-phase motor control method and device using the same
A multi-phase motor control method controls a multi-phase motor which includes multiple nodes respectively receiving a corresponding number of driving voltage signals to control a rotation of a rotor. The motor control method includes: sensing a signal phase of a current signal corresponding to at least one node, for example by sensing a zero-crossing point of the current signal; determining a reference phase for the current signal; calculating a phase difference between the signal phase and the reference phase; and controlling a phase switching frequency of the stator according to the phase difference, such that the signal phase is close to or in phase with the reference phase, to thereby obtain an optimum rotation speed of the rotor corresponding to a given driving voltage. The present invention also provides a multi-phase motor control device using the motor control method. |
| US09654036B2 |
Power conversion device and power conversion method
There is provided a power conversion device including a plurality of Direct Current (DC) power sources (VB) that converts an output voltage of each of the DC power sources into an Alternating Current (AC) voltage, and outputs the converted AC voltage in series connection, and the device includes: a DC/DC converter (21) connected to each of the DC power sources (VB) to convert the output voltage of the DC power sources; a control device (31) that controls an output voltage of the each DC/DC converter (21); and an H-bridge circuit (22) provided on the output side of the DC/DC converter (21) to convert the voltage output from the DC/DC converter (21) into an AC voltage. |
| US09654033B2 |
Controlling an electrical consumer of an aircraft
An electrical consumer of an aircraft comprises an electric motor and an inverter for producing an alternating voltage for the electric motor. A method for controlling the electrical consumer comprises determining a rotational frequency for the electric motor. The method also includes establishing whether the rotational frequency leads to oscillations in the input current of the inverter which are below a predefined threshold, the oscillations being produced by the inverter when producing a supply voltage for the electric motor, and changing the rotational frequency if it has been established that the rotational frequency leads to oscillations below the predefined threshold. |
| US09654030B2 |
Method for starting a variable-speed electric motor
The invention relates to a method for starting a variable-speed electric motor, wherein upon detection of locking of the motor shaft a positive torque is applied to the motor shaft, and wherein the positive torque is continuously modified with different frequencies to overcome the locking. |
| US09654029B2 |
Vibration type driving device
A vibration type driving device includes a vibrator configured to make an elliptic motion of a contact portion by combining vibrations in different vibration modes, and a driven body configured to be rotated relative to the vibrator by the elliptic motion while being in contact with the contact portion. A contact pressure of the contact portion with the driven body is lower on a radial inner side than on a radial outer side in a radial direction of the rotation. |
| US09654022B2 |
Power conversion device and control method thereof
A power conversion device is disclosed herein. The power conversion device includes an AC-DC conversion unit, a switching unit and a bypass circuit. The AC-DC conversion unit is configured to receive an AC input voltage via a power input terminal, and output a DC output voltage to a power output terminal according to the AC input voltage. The switching unit is configured to be switched off according to the AC input voltage received from the power input terminal, and to be switched on according to a DC input voltage received from the power input terminal. The bypass circuit is configured to receive the DC input voltage via the switching unit, and output the DC output voltage to the power output terminal according to the DC input voltage. |
| US09654020B2 |
Smart matching step-down circuits and travel-use power conversion devices
Provided is a smart matching step-down circuit, comprising an alternating current input terminal (10), a rectifier filter circuit (20), a switching circuit (30), a high voltage BUCK control step-down circuit (40), a floating zero potential control circuit (41), a voltage detection and feedback circuit (50), a PWM controller (52), a full-bridge DC/AC converter circuit (60), an alternating current output terminal (70), an output voltage detection circuit (62), and a conversion controller (80); the high voltage BUCK control step-down circuit comprises a step-down inductor (L1) and a step-down capacitor (C18); the first end of the step-down inductor is connected to the output terminal of the switching circuit; the second end of the step-down inductor is connected to the positive electrode of the step-down filter capacitor, and is used for stepping down and filtering the pulse voltage, then outputting a second direct current; the floating zero potential control circuit comprises a flyback diode (D11, D12); the cathode of the flyback diode is connected to the circuit ground, together with the first end of the step-down inductor; the anode of the flyback diode is connected to the floating ground (GND), together with the negative electrode of the step-down filter capacitor; the smart matching step-down circuit can step down a wide voltage, and is broadly adaptable. |
| US09654018B2 |
Deviation compensation method of potential transformer
A deviation compensation method of a potential transformer is provided. The deviation compensation method includes: detecting an output voltage value of a first potential transformer; checking a compensation value applied to the first potential transformer; compensating for the output voltage value based on the compensation value to measure an actual voltage value for a location at which the first potential transformer is installed; verifying the validity of the measured actual voltage value; and resetting a deviation compensator measuring the actual voltage value according to a result of verification on the validity of the actual voltage value. |
| US09654010B2 |
Power converter circuitry with switching frequency control circuitry
Driver circuitry includes power converter circuitry, switching control circuitry, and switching frequency limiting circuitry. The power converter circuitry is configured to receive and selectively provide an input signal to one or more power conversion components via a power converter switching element to produce a regulated output signal. The switching control circuitry is coupled to the power converter switching element and configured to provide a switching control signal for controlling the power converter switching element based on a frequency limited switching trigger signal. The switching frequency limiting circuitry is coupled to the power converter circuitry and the switching control circuitry and configured to receive a switching indicator signal from the power converter circuitry and provide the frequency limited switching trigger signal based on the switching indicator signal and the switching control signal such that the frequency limited switching trigger signal limits the frequency of the switching control signal. |
| US09654007B1 |
Regulation of a multiple stage switch mode power converter through an intermediate voltage control
A multiple phase, multiple stage SMPC system includes at least one single stage phase SMPC circuit that converts an input voltage to an output voltage applied to an electronic load circuit and at least one multiple stage phase SMPC circuit. The at least one multiple stage phase SMPC circuit has at least one primary stage phase SMPC circuit generates, monitors, and controls an intermediate voltage and at least one secondary stage phase SMPC circuit converts the intermediate voltage to the output voltage. The at least one secondary stage phase has a voltage conditioner that transforms the intermediate voltage to a reference voltage that is approximately the level of the output voltage. The at least one primary stage phase SMPC circuit monitors and controls the intermediate voltage to force the at least one secondary stage phase to make its output current a correct portion of the total load current. |
| US09654006B2 |
Semiconductor device and control method thereof
According to one embodiment, a DC-DC converter 1 includes a power supply unit 12 that includes an inductor L1 and a switching unit and generates an output voltage Vout corresponding to a duty of a pulse signal P1, a PID controller 111 that outputs a control signal S corresponding to a difference between a divided voltage of Vout and a target voltage Vcnst, a PI controller 112 that outputs a control signal D corresponding to a difference between the control signal S and an average current flowing through the inductor L1, a PWM generation unit 113 that generates the pulse signal P1 with a duty ratio corresponding to the control signal D, and in step-down mode, the PI controller 112 performs proportional control of the differential signal ei by using a product of the control signal D and a reference proportionality constant KP as a proportionality constant. |
| US09654005B2 |
Battery charge and discharge management circuit and electronic device thereof
An apparatus can include: (i) a first switch coupled to an external interface and an inductor; (ii) a second switch coupled to ground and a common node between the first switch and the inductor; (ii) a third switch coupled to ground and a common node between the inductor and a fourth switch, where the inductor and first, second, third, and fourth switches form a power converter; (iii) a charge and discharge control circuit coupled to the power converter, and being configured to control the first, second, third, and fourth switches; (iv) an internal load coupled to said fourth switch; and (v) a chargeable battery coupled to the fourth switch, where the battery is configured to provide power to the internal load when the external interface is disconnected from the external power supply and the external load. |
| US09654003B1 |
Methods and apparatus for resonant energy minimization in zero voltage transition power converters
In a method arrangement, providing a zero voltage transition circuit including an input node, an output node, a switch node, an output inductor coupling the switch node and output node, an output capacitor coupling the output node and ground, a first switch coupling the input node and switch node, a second switch coupling switch node and ground, a first auxiliary switch coupling the input node to an auxiliary node, a second auxiliary switch coupling the auxiliary node to ground, and an auxiliary inductor coupling the auxiliary node to the switch node; closing the first auxiliary switch to couple the input to the auxiliary node; subsequently, when a current is below a cutoff threshold, opening the second switch; after a first delay period, opening the first auxiliary switch and closing the second auxiliary switch; and after a second delay period, closing the first switch. Apparatus and additional method arrangements are disclosed. |
| US09654002B2 |
Circuits and methods providing dead time adjustment at a synchronous buck converter
An apparatus and method are disclosed for efficiently using power at a voltage regulator, such as a synchronous buck converter. The synchronous buck converter includes a first switch and a second switch operated by a first control signal and a second control signal, respectively, where the first and second control signals have a corresponding phase difference. A logic circuit measures a duty cycle of an input pulse width modulated (PWM) signal against iterative changes of the phase difference between the first control signal and the second control signal. The logic circuit selects a phase difference corresponding to a minimum value of the PWM signal, thereby optimizing dead time at the synchronous buck converter. The logic circuit may include a Digital Pulse Width Modulator. |
| US09654000B2 |
Buck converter and method of operating a buck converter
A buck converter has an output node and a ground node, wherein a load is connected between the output node and the ground node and is arranged to drive an output current I_out through the output node, generating an output voltage V_out. A current control unit arranged to control the output current I_out in dependence on a control voltage V_ctl provided at a control node; and a voltage control unit arranged to provide the control voltage V_ctl. The voltage control unit comprises: an integrator unit arranged to control the control voltage V_ctl in dependence on a time integral of a difference between the output voltage and the reference voltage; at least one of an overshoot detector arranged to detect an overshoot of the output voltage V_out, and an undershoot detector arranged to detect an undershoot of the output voltage V_out. |
| US09653998B2 |
Boost converter and power controling method thereof
A boost converter and a power control method thereof. The boost converter includes an inductor, a first switch unit, a second switch unit, a discharging loop and a detecting circuit. The inductor is electrically connected to a power input end. The first switch unit is electrically connected between the inductor and ground. The second switch unit is electrically connected between the inductor and an output end. The discharging loop is connected with the inductor in parallel and includes a third switch unit. The detecting circuit is used to detect a discharging value of the inductor. When the discharging value exceeds a threshold value, the third switch unit is turned on, and the inductor releases energy via the discharging loop. |
| US09653997B2 |
Ringing suppression method and apparatus for power converters
A method of controlling a power converter for converting a DC input voltage to a DC output voltage is presented The power converter comprises an inductor, one or more switching elements for energizing and de-energizing the inductor, a drive circuit for controlling switching operation of the one or more switching elements in accordance with a control signal, and a feedback circuit for generating the control signal on the basis of a first feedback quantity indicative of an actual output voltage of the power converter and in accordance with one or more circuit parameters of the feedback circuit, the method comprising: detecting an open loop condition of feedback control by the feedback circuit; and modifying at least one of the circuit parameters of the feedback circuit in such a manner that a time until the feedback control by the feedback circuit returns to the closed loop condition is reduced. |
| US09653992B2 |
Constant on-time switching converter with adaptive ramp compensation and control method thereof
A COT switching converter includes a first switch, a second switch, an inductor, an on-time control circuit configured to generate an on-time control signal, a ramp compensation generator configured to generate a compensation signal, a comparing circuit, a logic circuit, a driving circuit and a feed forward circuit configured to generate a compensation control signal based on the input voltage of the switching circuit. The comparing circuit compares the sum of the compensation signal and a feedback signal with a reference signal to generate a comparison signal. Based on the on-time control signal and the comparison signal, the logic circuit generates a control signal with a duty cycle to drive the first and second switches through the driving circuit. The ramp compensation generator adjusts the compensation signal based on the compensation control signal, so the amplitude of the ramp compensation signal can follow a critical value proportional to the difference between the duty cycle and the square of the duty cycle. |
| US09653989B2 |
Suppying an output voltage using unsynchronized direct current to direct current converters
A system that may include a first direct current to direct current (DC) converter that is arranged to determine at a first determination rate whether to alter a parameter of operation of the first DC to DC converter and to selectively alter the parameter of operation of operation of the first DC to DC converter in response to the determination; and a second switched-mode DC to DC converter that is arranged to determine at a second determination rate whether to alter the parameter of operation of the second DC to DC converter and to selectively alter the parameter of operation of operation of the second DC to DC converter in response to the determination. The second determination rate is higher by at least a factor of two than the first determination rate. The first and second DC to DC converters are mutually unsynchronized. |
| US09653988B2 |
Apparatus and system for noise cancellation of power converters
A system having a noise cancellation converter being configured for phase inverted synchronous operation with a primary converter. The primary converter is operable to supply power to at least one device. The primary converter produces a first electromagnetic interference during operation. The noise cancellation converter is further configured with parasitic components matching parasitic components of the primary converter. The noise cancellation converter produces a second electromagnetic interference that is coupleable to the device. The second electromagnetic interference comprises frequency components having an inverted phase relative to frequency components of the first electromagnetic interference for reducing a sum of the first electromagnetic interference and the second electromagnetic interference during coupling to the device. An RC network component is configured to operatively connect the primary converter and the noise cancellation converter being operable to cancel out the sum of the electro-magnetic interference signals. |
| US09653984B2 |
Filter capacitor degradation detection apparatus and method
Power conversion systems and methods are presented for detecting input filter capacitor degradation or approach of end of operational life based on filter capacitor current measurements using single and/or dual threshold comparisons for computed instantaneous sum of squares of filter currents or power values. |
| US09653982B2 |
Power supply systems and methods
Aspects include a power supply system. The system includes an oscillator system configured to generate a clock signal at a clock node. The oscillator system includes a comparator configured to compare a first variable voltage at a first comparator node and a second variable voltage at a second comparator node. The first and second variable voltages can have respective magnitudes that are based on a state of the clock signal. The system also includes a pulse-width modulation (PWM) generator configured to generate a PWM signal based on an error voltage and the clock signal. The system further includes a power stage configured to generate an output voltage based on the PWM signal. |
| US09653980B2 |
Energy harvesting system using several energy sources
An object of the invention is to provide a cheap, efficient and polyvalent energy harvesting system able to exploit several energy sources. The invention proposes an energy harvesting system (100) including a frame, at least one permanent magnet (101) having a North/South direction, and at least one winding (107, 108) wound according to a winding direction around a core (103a-103b) including a high magnetic permeability material, at least said at least one permanent magnet being mounted on the frame to be able to oscillate relatively to the winding, characterized in that the system includes a magnetic flux divider arranged between said at least one permanent magnet and said at least one winding in order to concentrate the magnetic flux at discrete positions of maximum magnetic flux then forming equilibrium positions where the winding faces one of the said discrete positions of maximum magnetic flux. |
| US09653979B2 |
Multidirectional vibration generator using single vibrator and method for the same
Disclosed is a vibration generating method includes providing a vibration generating device which receives a driving power and generates a vibration, and controlling vibration of a vibrator of the vibration generating device, wherein the vibration of the vibrator is controlled by systematizing an inertia matrix and a stiffness matrix of the vibrator, and wherein the inertia matrix and the stiffness matrix simultaneously satisfy diagonalization. A vibration generating device using this method is also disclosed. |
| US09653977B2 |
Synchronous generator of a gearless wind energy turbine
The present invention concerns a synchronous generator of a gearless wind power installation, comprising a stator and a multi-part external rotor. The invention also concerns a wind power installation having such a generator. Furthermore the present invention concerns a transport arrangement for transporting a synchronous generator of a gearless wind power installation. |
| US09653971B2 |
Speed detection circuits for permanent magnet alternators
A permanent magnet alternator (PMA) includes a rotatable shaft, windings, a shunt regulator circuit, and a speed detection circuit. The rotatable shaft is connected electromagnetically to the windings. The shunt regulator circuit is electrically connected to the windings. A current sense transformer with a primary coil is electrically connected to the shunt regulator circuit. A secondary coil is electrically connected to a comparator circuit with reference voltage and generates voltage pulse indicating PMA speed. The voltage pulses form an output corresponding to and indicative of rotation speed of the shaft suitable for processing by a processor to present a PMA speed indication for use in the overall system architecture as a measurement parameter. |
| US09653970B2 |
Rotary capacitor for shunting high frequency bearing currents and reducing EMI in electric machinery
Rotary capacitor assemblies divert or mitigate high-frequency electrical currents and voltages in bearings of electric machinery (e.g., motors and generators) without direct contact with the bearings. The assemblies include rotating capacitors, in which surfaces in close proximity are free to rotate with respect to another while maintaining relative surface area and separation distance. A lubricant (such as air or oil) facilitates capacitive surfaces hydrodynamically “floating” on each other. A shunt body is connected electrically in parallel with the bearings of the machine, providing a non-contact or nearly non-contact electrical pathway for damaging high-frequency currents an voltages to be shunted around the mechanical load carrying bearings. |
| US09653969B2 |
Brush structure with heat dissipation member
To obtain a rotating electrical machine preventing a functional failure and shortening of the life of brushes caused by a temperature rise of the brushes installed to a vehicle AC power generator or a motor generator. A brush holder holding brushes supplying a field current to a rotor is provided with brush temperature suppressing metal members installed substantially parallel to the brushes in the vicinity of abutment portions of the brushes and slip rings in point-, line-, or surface-contact with the brushes at least at one point besides energization terminals. The brush temperature suppressing metal members not only diffuse heat generated at the brushes, but also function as a heat capacity for a case where a large amount of heat is generated in a short time, such as during regenerative power generation and a start-up operation, and thereby prevent an excessive temperature rise of the brushes. |
| US09653967B2 |
Cooling arrangement for an electric motor
An electric motor includes a stator operable to produce a magnetic field and defining an opening, and a rotor at least partially disposed within the opening. The rotor includes a shaft extending along a rotational axis, a first rotor magnetic core portion including a plurality of laminations stacked contiguously on the shaft, and a second rotor magnetic core portion coupled to the plurality of laminations. The first rotor magnetic core portion and the second rotor magnetic core portion cooperate to define the rotor magnetic core. A plurality of windings is coupled to the rotor magnetic core and an air flow path is formed as part of the second rotor magnetic core portion. The air flow path includes an axial portion that passes through the shaft axially along the rotational axis and a radial portion that extends radially outward through the second rotor magnetic core portion. |
| US09653960B2 |
Motor and blower
An inner-rotor motor includes a shaft, a rotor magnet, a stator, a housing including a housing tubular portion extending along a rotation axis, a cap, and a bearing portion. The cap is located above the housing, and includes a cap bottom portion and a cap tubular portion which extends downward from the cap bottom portion. A core back of the stator includes a tubular outer circumferential surface including a plurality of stator contact portions in contact with the housing tubular portion. The stator contact portions are spaced from one another in a circumferential direction. The cap tubular portion includes a plurality of cap contact portions in contact with the housing and spaced from one another in the circumferential direction. At least one of the cap contact portions is located at a circumferential position different from a circumferential position of each stator contact portion. |
| US09653958B2 |
Rotor wedge with arms
A wedge for use in a generator rotor includes a wedge body extending for an axial length and having a generally triangular cross-section, a first side of the wedge body extending for the axial length of the wedge body, a second side of the wedge body extending for the axial length of the wedge body and having a generally flat surface, a third side of the wedge body extending for the axial length of the wedge body and having a generally flat surface, a first arm extending circumferentially away from the wedge body at an interface between the first side and the second side and extending axially along the wedge body, and a second arm extending circumferentially away from the wedge body at an interface between the first side and the third side and extending axially along the wedge body. |
| US09653957B2 |
Stator with coil fixing member and electric motor with the stator
A stator includes: a stator core having a yoke and teeth projecting from the yoke; coils attached to the stator core so as to surround the teeth; and coil fixing members, each of which is arranged at at least one of opposite ends of the stator core in a gap formed between an end face of the tooth and an inner side of the coil facing the end face. The coil fixing member includes a locking part that projects on the opposite side from the end face of the tooth to lock the coil and a projection that projects on the opposite side from the locking part, and the projection is inserted into an insert hole formed on the stator core. |
| US09653948B2 |
Wireless resonant electric field power transfer system and method using high Q-factor coils
A wireless electric field power transmission system comprises: a transmitter comprising a transmitter antenna, the transmitter antenna comprising at least two conductors defining a volume therebetween; and at least one receiver, wherein the transmitter antenna transfers power wirelessly via electric field coupling when the at least one receiver is within the volume. |
| US09653945B2 |
Converter between solar panel, source and load
A system, comprising a solar circuit (2), a coupling circuit (1), a converter circuit (5), a source circuit (3), and a load circuit (4), wherein the coupling circuit (1) couples in a first, charging mode the solar circuit (2) to the source circuit (3) via the converter circuit (5) and couples in a second, feeding mode the source circuit (3) to the load circuit (4) via the converter circuit (5). A power flow through the converter circuit (5) has a same direction in both modes. In the first mode, a charging current is guided from the solar circuit (2) to the source circuit (3) via the converter circuit (5) for charging the source circuit (3). In the second mode, a feeding current is guided from the source circuit (3) to the load circuit (4) via the converter circuit (5) for feeding the load circuit (4). The coupling circuit (1) may comprise a first switch (11) and a second switch (12) and a control circuit (13-21) for controlling the first and second switches (11, 12). The control circuit (13-21) may comprise generators (13, 15), a comparator (14), detectors (16, 17, 19), a manager (18) and a regulator (20). |
| US09653942B2 |
Receiver for wireless charging system
A receiver for a wireless charging system, capable of receiving power energy using non-contact type magnetic induction, includes a coil capable of receiving the power energy and a part for generating a predetermined output power from the power energy received by the coil, a portable terminal, an NFC coil further provided outside of the coil, and a ferrite sheet further provided at the coil and the NFC coil. |
| US09653940B2 |
Headset wireless charging dock
A method and system for a headset wireless charging dock, where the charging dock comprises a radio frequency (RF) radio, a charging induction coil, and a proximity sensor. The method may comprise sensing a presence of a headset using the proximity sensor, wirelessly charging a battery in the headset utilizing the charging induction coil, and wirelessly communicating commands, using the RF radio, to the headset to power down at least a portion of circuitry in the headset. The command may be communicated to the headset utilizing a protocol and a RF radio used by the headset to receive audio signals. The command communicated to the headset may power down audio processing circuitry in the headset. The charging induction coil may be inductively coupled to a coil in the headset to wirelessly charge the battery in the headset. The proximity sensor may comprise a Hall sensor. |
| US09653939B2 |
Non-contact type power charging apparatus
A non-contact type power charging apparatus may include a plurality of power transmitting coils transmitting power in a non-contact scheme, a plurality of switching units connected to the power transmitting coils, respectively, to switch the power transmitted through corresponding power transmitting coils, and a switching controlling unit controlling power switching of the switching units depending on coupling coefficients between each of the power transmitting coils and at least one power receiving coil of a plurality of battery apparatuses. The battery apparatuses may have at least one power receiving coil receiving the power from the power transmitting coils to charge the power in at least one battery cell. |
| US09653935B2 |
Sensing temperature within medical devices
Devices, systems, and techniques for monitoring the temperature of a device used to charge a rechargeable power source are disclosed. Implantable medical devices may include a rechargeable power source that can be transcutaneously charged. The temperature of an external charging device and/or an implantable medical device may be monitored to control the temperature exposure to patient tissue. In one example, a temperature sensor may sense a temperature of a portion of a device, wherein the portion is non-thermally coupled to the temperature sensor. A processor may then control charging of the rechargeable power source based on the sensed temperature. |
| US09653933B2 |
Portable automotive battery jumper pack with detachable backup battery
A Portable automotive battery jumper pack with detachable backup battery. The invention is configured to be user friendly with a flexible compact design. The invention will be used in the portable, automotive electronics area. |
| US09653932B2 |
Portable cathodic protection current interrupter
The portable cathodic protection current interrupter is a programmable, portable current interrupter for selectively controlling current interruption to a cathodic protection system. A processor and a voltage regulator are disposed within a portable housing and are in communication with one another. The voltage regulator is adapted for communication with an external power source. A display and a user interface are each mounted on the portable housing. An onboard clock is in communication with the processor for controlling the frequency and duration of current interruption signals. A global navigation satellite system receiver is provided for synchronizing a time signal of the onboard clock. At least one on-board relay is provided for communication with the cathodic protection current source for selectively interrupting current thereto. The portable cathodic protection current interrupter provides selective switching of the relay(s) between a main interruption channel, a testing interruption channel, and an external interruption channel. |
| US09653929B2 |
Battery charging apparatus and charging method thereof
A battery charging apparatus and charging method thereof are disclosed. In one aspect, the apparatus includes a battery including a battery pack including at least one battery cell, a battery management system (BMS) configured to control the generation of a terminal voltage based on a type of the battery pack, and a terminal unit including electrodes configured to receive the terminal voltage. The apparatus further includes a charger including a controller configured to determine the type of the battery pack based on the terminal voltage and control the generation of a charging voltage corresponding to the type of the battery pack. |
| US09653927B2 |
Composite integrated circuits and methods for wireless interactions therewith
A composite integrated circuit (IC) includes a first circuit layer, a second circuit layer having a first chip and a second chip, and a first wireless power transfer (WPT) device in the first chip or the first circuit layer. The first WPT device generates a power supply voltage by extracting energy from an electromagnetic signal. A first tracking circuit in the second chip or the first circuit layer is powered by the power supply voltage from the first WPT device and stores or outputs tracking data in response to an instruction extracted from the electromagnetic signal. |
| US09653919B2 |
Method for reducing common mode current circulating between the internal ground of an electrical circuit and the earth
A method for reducing the common mode current (i) circulating between the internal ground (13) of an electrical circuit (4) and the earth when electrical energy is exchanged between an electrical energy storage unit of the electrical circuit (4) and an electrical energy source external to said circuit (4),in which method an electronic component (21) is used to apply an electrical quantity (Vs, Is) ata point (26) connected via at least one impedance (28) to an electrical line (5) of said circuit (4) via which electrical energy is exchanged,said electrical quantity (Vs, Is) applied making it possible to reduce the common mode current (i). |
| US09653913B2 |
Resistance change device providing overcurrent protection
An overcurrent protection device may include an input terminal to receive an input current; an output terminal coupled to the input terminal; and a current limiter circuit integrated into the silicon substrate and arranged between the input terminal and output terminal. The current limiter circuit may include a series pass element having a pass state characterized by a first electrical resistance and a limit state characterized by a second electrical resistance higher than the first electrical resistance, the series pass element comprising a series current sense element integrated into the silicon substrate and configured to receive the input current and to output a sense voltage based upon the received input current, wherein the series pass element is configured to place the current limiter circuit into the limit state when the sense voltage indicates that the input current exceeds a predetermined level. |
| US09653912B2 |
Inrush current limiter
An inrush current limiter for electronic fuses detects the type of load connected to the electronic fuse at ignition. By detecting the type of load, the limiter prevents a large peak current from flowing through the fuse. When a short circuit occurs, the limiter ensures that the electronic fuse only operates once in linear mode. |
| US09653903B2 |
Electrically conductive housing with cable strain relief and shield connection
An electrically conductive housing with cable strain relief and shield connection, wherein a cable is introduced into a recess of the housing, wherein the strain relief includes a thrust member that can be displaced radially in the recess of the housing and the thrust member is biased with at least one housing-side clamping screw, presses the cable sheathing of the cable against a housing-side mold surface opposite the thrust member. The recess passes through the device wall of the housing in whose wall area the thrust member is arranged. The housing-side mold surface opposite the thrust member includes an mold surface conformed approximately to the outer shape of the cable sheathing that transitions into the recess in the device wall enlarged in comparison to the mold surface. |
| US09653900B2 |
Outdoor electrical box
An electrical box includes a body, a cover that is movable relative to the body, and an electrical connection point that is mounted to the cover. The electrical connection point may be one or more of an electrical receptacle, a data jack, and/or the like. The cover may be attached to the body by a sliding hinge connection that allows the cover to rotate relative to the body as well as translate relative to the body. An air pocket substantially filling a compartment in the cover is maintained during an opening or closing of the electrical box. |
| US09653896B2 |
Electrical enclosure including an integral exhaust duct and method
An electrical enclosure includes a first wall having an exhaust opening, a second wall, and a third wall. The electrical enclosure also includes at least one circuit breaker compartment, a line compartment arranged between the third wall and the at least one circuit breaker compartment, and an exhaust duct extending through the electrical enclosure between the first wall and the second wall. The exhaust duct is fluidically connected to the exhaust opening and each of the at least one circuit breaker compartments. At least one passage extends between the line compartment and the at least one circuit breaker compartment through the exhaust duct. The at least one passage is substantially fluidically isolated from the exhaust duct. |
| US09653894B2 |
Wire harness and connector
An incorrect fitting of a connector (40) is prevented, and a fitting work is enabled to be performed smoothly. A plurality of connectors (40), each having a housing (41) capable of fitting with its counterpart housing (71), is arranged in a line. Upon fitting of the housings (41, 71), a front face of each housing (41) is arranged so as to face a direction facing its counterpart housing (71), and an aligning direction of the connectors (40) is set to be a direction intersecting a front-rear direction. Through portions (52, 52E) are provided in the housings (41), and upon fitting of the housings (41, 71), each connector (40) is arranged at a position capable of facing its counterpart connector (70) by an aligning member (80, 100) that is passed through the respective through portions (52, 52E). |
| US09653891B2 |
Electrical component for rail mounting
An electrical component that is adapted for being mounted onto a rail comprises a first outward-facing slot for receiving a first brim of a rail of a first type, a first outward-facing snap-lock for fixating a second brim of a rail of the first type, a first inward-facing slot for receiving a first brim of a rail of a second type and a first inward-facing snap-lock for fixating a second brim of a rail of the second type. |
| US09653890B2 |
Metering apparatus for load centers
An apparatus includes a housing configured to be mounted at a breaker position of a load center and supporting at least one electrical connector configured to be electrically coupled to a bus bar of the load center. A graphical display is disposed at a face of the housing. A control circuit is disposed in the housing, electrically coupled to the at least one electrical connector and configured to control the graphical display. The control circuit may be further configured to be coupled to an external sensor, such as a current sensor. The control circuit may be configured to perform an electrical measurement and to display a result of the measurement on the graphical display. |
| US09653889B2 |
Ionizer
The present invention relates to an ionizer mounted to an air outlet of an air conditioner, and includes an ion generating unit for generating ions, and an ion visualizing unit mounted to an air outlet of an air conditioner for notifying whether the ion generating unit generates the ions or not, the ion visualizing unit having the ion generating unit mounted thereto, thereby permitting a user to notice whether the ionizer is mounted or not easily, and to express whether ions are generated or not and intensity of the ion generation. |
| US09653888B2 |
Spark plug
A spark plug including an insulator containing not less than 92 mass % and not greater than 96 mass % of Al component in terms of oxide, wherein the insulator is formed from an alumina sintered body comprising alumina crystal and a grain boundary phase present between crystal grains of the alumina crystal. Assuming that mass contents of an Si component, an Mg component, a Ba component, and a Ca component in terms of oxide are represented by MSiO2, MMgO, MBaO, and MCaO, respectively, and a sum of MSiO2, MMgO, MBaO, and MCaO is represented by Mt, the grain boundary phase contains these components so as to satisfy conditions (1) to (4) as follows: (1) 0.17≦MSiO2/Mt≦0.47; (2) 0.005≦MMgO/Mt≦0.07; (3) 0.29≦MBaO/Mt≦0.77; (4) 0.03≦MCaO/Mt≦0.19. |
| US09653887B1 |
Spark plug for a prechamber internal combustion engine
A spark plug for a prechamber internal combustion engine, having: a body with a passage and a front end; a center electrode located in the passage and that projects past the front end; an insulator that surrounds a section of the center electrode and has a tapering front end that together with the passage forms a free annular space within the body; a ground electrode with an annular ignition section that surrounds a section of the center electrode located outside the body, forming a spark gap; the ground electrode has a mounting section connected to the front end of the body, and at least two web sections connecting the ignition section to the mounting section; located between the web sections are scavenging ports through which the annular space is in connection with the environment outside the spark plug. |
| US09653882B1 |
Wavelength control of an external cavity laser
An optical source is described. This hybrid external cavity laser includes a semiconductor optical amplifier (with a semiconductor other than silicon) that provides an optical gain medium and that includes a reflector (such as a mirror). Moreover, the hybrid external cavity laser includes a photonic chip with: an optical waveguide that conveys an optical signal output by the semiconductor optical amplifier; and a ring resonator (as a wavelength-selective filter), having a resonance wavelength, which reflects at least a resonance wavelength in the optical signal. Furthermore, the photonic chip includes an interferometer that provides optical signals on arms of the interferometer. Control logic in the hybrid external cavity laser thermally tunes the resonance wavelength to match a cavity mode of the hybrid external cavity laser based on measurements of the optical signals from the interferometer. |
| US09653880B2 |
Tunable, narrow linewidth single transversal mode light source using a quasi-incoherent broadband pump source
A light source is disclosed, having a quasi-incoherent broadband pump source configured to produce a longitudinally and transversally multi-mode pump beam. The light source may include a means for narrowing the linewidth of the pump beam. The light source includes an optical parametric oscillator with an optical cavity containing a crystal. The optical parametric oscillator is configured to receive light from the pump source and produce a first output light beam and a second output light beam. An optical coupler is disposed between the pump source and the optical parametric oscillator. At least one of the first and second output light beams is a substantially single transversal mode light having a narrower linewidth than the pump source. |
| US09653878B2 |
Circuit, optical module, methods and optical communication system for dual rate power point compensation
A dual-rate power point compensating circuit, comprising a microprocessor and a transmitter optical subsystem assembly (TOSA), wherein the TOSA includes a laser connected to a laser driver, a monitor photodiode (MPD) connected to the laser driver, and a current divider connected to the microprocessor and the MPD. When a feedback current from the MPD exceeds the adjustable and/or operating range of the laser driver, the feedback current is reduced so that it is kept in the adjustable and/or operating range of the laser driver. The laser driver determines the optical output power of the laser from the value of the reduced feedback current. The circuit and method extend the adjustable and/or operating range of a laser driver and enable it to regulate a target optical output power of the laser with a broad testing range and high accuracy when the feedback current is relatively high. |
| US09653877B1 |
Nested frequency combs
Apparatus, systems, and methods of generating multi combs can be used in a variety of applications. In various embodiments, a passive resonator can be disposed in the laser cavity of a mode-locked laser to generate a nested frequency comb. The passive resonator can be a sample under investigation, where a characteristic of the sample is determined using the generated nested frequency comb. Additional apparatus, systems, and methods are disclosed. |
| US09653876B2 |
Gas laser apparatus for determining composition ratio of laser gas
A gas laser apparatus includes an actual laser output acquiring unit that acquires a first actual laser output at a predetermined laser output command after passage of a predetermined time from issuing of a first laser gas pressure command and acquires a second actual laser output at the predetermined laser output command after passage of the predetermined time from issuing of a second laser gas pressure command smaller than the first laser gas pressure command and a determining unit that determines whether the composition ratio of a laser gas in a gas container is normal or not by comparing the first actual laser output with a first reference output and comparing the second actual laser output with a second reference output smaller than the first reference output. |
| US09653863B2 |
Process for providing a charge dissipation path
When a hobby enthusiast has recharged the battery for a remote controlled vehicle, such as a scale facsimile automobile, boat, helicopter or airplane, the battery must be connected again to the vehicle drive system, to provide power. This operation is typically performed by connecting each lead of an electronic speed controller to each corresponding lead of the battery, through a removable barrel receptacle lead and a mating barrel plug lead respectively, attached to each corresponding lead. An improved connector lead is described herein that protects components that may be attached to either lead in a connection. The charge dissipates in a resistive member that is physically coupled to a conductive member to form at least in part a first lead. When an improved lead is connected to a mating lead, the connection initially provides a charge dissipation path through the resistive member, but subsequently provides a bypass, current carrying conductive path around the resistive member from one component to another. By making use of an improved connector, electrical components are protected, not only from hot-swap current, but also from electrostatic discharge in general. |
| US09653860B2 |
Ultrabox receptacle box
A modular electrical receptacle box configured to allow outlets and switches to be easily installed using wire segments extending between terminals in the box bottom surface and the outlet and switch. The box has a housing having a first recess, at least one electrical outlet or switch secured to the housing and disposed in the first recess, a plurality of electrical terminals disposed in the bottom wall, a plurality of electrical conductor segments extending between the outlet or switch and the electrical terminals, and a first connector coupled to the electrical terminals via a plurality of electrical busses. |
| US09653851B1 |
Electrical connector
An electrical connector includes an insulating housing, a plurality of conductive terminals, a shielding plate and a ground element. The insulating housing has a base portion, and a tongue portion protruded frontward from a front surface of the base portion. The conductive terminals are received in the insulating housing, and front ends of the conductive terminals are exposed to the tongue portion. The shielding plate is received in the insulating housing. The ground element is for being connected between the shielding plate and ground. The ground element is received in the insulating housing. The ground element has a touch portion contacting the shielding plate. |
| US09653848B2 |
Connector
A connector includes a housing and a plurality of signal contacts and a plurality of ground contacts. Each contact includes a contact portion that contacts an object, a connection portion mounted on a substrate, and a fixing portion located between the contact portion and the connection portion in the vicinity of the connection portion. The signal contact and the ground contact are aligned and held in the housing, and the fixing portion is fixed to the housing. When the plurality of signal contacts are arranged between the ground contacts, at least two of the ground contacts are coupled and connected integrally or by a separate component, the coupling and connection being made in a section of each ground contact between one end (leading end) of the contact portion and the fixing portion, so that high-frequency transmission characteristics are improved. |
| US09653845B2 |
Connector assembly with integrated lever locking system
An electrical connector assembly comprising a connector housing; and a mate assist mechanism comprising a lever pivotably arranged on the connector housing. The lever is movable from a preliminary mating position to a fully mated position, and is configured to be releasably held in the preliminary mating position by a holding means. The holding means comprises a locking protrusion and a corresponding locking reception receiving said locking protrusion when the lever is in the preliminary mating position. |
| US09653835B2 |
Contact system for plug-in connections on electronics housings
A contact system for plug-in connections on electronics housings (1) for making contact with mechatronic components of motor vehicles, includes at least one contact element (13) formed of a punched part, with which contact is made on a printed circuit board (5) and which is routed out of a housing (2). For the purpose of making releasable contact with the mechatronic components, flexibly compensating for relative movements of the contacts, and allowing cost-effective production and processing without the use of special technical apparatuses, the at least one contact element (13) is designed to be fastened to a base plate (2) of the electronics housing (1) by insertion and latching, make contact with a plug-in contact (23) of a mechatronic component by way of a first contact lug (14), and make contact with the printed circuit board (5) by way of a second contact lug (20). |
| US09653828B1 |
Electrical connector
An electrical connector mounted to a circuit board, includes an insulating housing, a plurality of terminals integrally molded to the insulating housing, a shell surrounding the insulating housing, and an upper cover covered on the circuit board. The shell has at least one lower fastening piece. At least one tongue board of the circuit board is fastened on the at least one lower fastening piece. Circuit lines equipped on a bottom surface of the at least one tongue board are embedded in lower embedding slots of the at least one lower fastening piece. The upper cover has at least one upper fastening piece. The at least one upper fastening piece is fastened on the at least one tongue board. Circuit lines equipped on a top surface of the at least one tongue board are embedded in upper embedding slots of the at least one upper fastening piece. |
| US09653825B2 |
Modified registered jack-style plug for direct attachment to a circuit board
A physical network plug, configured to attach to a registered jack (RJ)-style jack and also configured to be directly mountable to a circuit board, is provided. The plug includes a plurality of pin contacts extending from a front end thereof and configured to extend through and be electrically connected to a circuit board. Each of the pin contacts is electrically connected to a spade disposed within the plug. The plug further includes a pair of tabs, extending from the front end of the plug, and configured to extend through the circuit board from a rear side to a front side of the circuit board, and to clasp the front side of the circuit board. |
| US09653824B2 |
Reduced temperature energy storage device
An energy storage system is disclosed. The energy storage system includes a first energy storage cell, a second energy storage cell, and a first interconnect connecting the first and second cells. The interconnect includes a support member and a plurality of protrusions extending away from the support member. At least two protrusions are spaced relative to each other along a longitudinal axis of the interconnect. |
| US09653823B2 |
Connector having installation-responsive compression
A connector includes an conductor engager, coupler-driver and a compressor-body. A coupler is disposed over and engages a grounding end of the conductor engager while a torque drive member rotationally drives the coupler to threadably engage an interface port. Threaded engagement of the coupler causes the conductor engager to move forwardly toward the interface port and the torque drive member to move rearwardly relative to the conductor engager. Rearward movement of the torque drive member causes a compressor to slide axially over plurality of radially compliant fingers of the compressor-body. The compliant fingers are displaced radially inward to compress a prepared end of the coaxial cable, i.e., an outer conductor and a radially compliant outer jacket, against a tubular-shaped retention end of the conductor engager. Compression of the prepared end connects the coaxial cable to the connector. |
| US09653822B2 |
Cable connector assembly and method of manufacturing the cable connector assembly
A cable connector assembly includes a cable (6), a contact module connected with the cable, a shell (3) enclosing on the contact module, an inner insulator (7) enclosing on the shell and front end of the cable, an outer insulator (5) enclosing on the inner insulator, and a cover (4) assembled on the outer insulator. The shell has a mating section on a front end thereof, and the mating section is extending forwards beyond the outer insulator. The outer insulator has a pair of cutouts (51) on opposite walls thereof. The inner insulator defines a pair of projections exposed in the corresponding cutouts of the outer insulator, and the cover is assembled to the inner insulator and the outer insulator by combination with the projections. |
| US09653821B1 |
Dual band antenna with a first order mode and a second order mode
An antenna structure with a radio frequency (RF) circuit, an antenna carrier, and conductive material disposed on the antenna carrier and coupled to the RF circuit slot is described. The conductive material can radiate or receive first electromagnetic energy as a loop antenna in a first frequency band in a second order mode. The conductive material can include a first slot between portions of the conductive material and a second slot between other portions of the conductive material. The first slot or the second slot can radiate or receive second electromagnetic energy as a slot antenna at a second frequency band in a first order mode. The second frequency band can be higher than the first frequency band. |
| US09653819B1 |
Waveguide antenna fabrication
An example method of fabricating a waveguide antenna may involve providing a first metal layer with waveguide channels formed therein. The method may also involve selecting at least one coupling surface on the first metal layer that is proximate to at least edges of the waveguide channels. The method may also involve removing respective oxidation layers from second and third metal layers. The method may also involve providing, to the selected at least one coupling surface, a fusible metal material and a reactive metal foil between surfaces of the first and second metal layers and between surfaces of the first and third metal layers. The method may also involve coupling the layers together by igniting the reactive metal foil so as to locally provide heat to the surfaces of the layers and melt the fusible metal material, and then cooling the melted fusible metal material. |
| US09653816B2 |
Antenna system
An antenna system can include a first panel of radiators that extend from a vertex in a first substantially linear direction. The antenna system can also include a second panel of radiators extending from the vertex in a second substantially linear direction. The first panel of radiators and the second panel of radiators form an angle between about 1 degree and about 45 degrees to enhance gain. |
| US09653812B2 |
Subsurface antenna for radio frequency heating
A subsurface antenna is designed for use below the surface of the Earth. In some configurations the antenna is a dipole antenna, which can be used for radio frequency heating of an oil-bearing formation. |
| US09653811B2 |
Dipole antenna with micro strip line stub feed
Various embodiments are described that relate to a line feed and a dipole element. The line feed can be supplied directly with a current without a balun. Being supplied with this current can cause the line feed to emit an electromagnetic field. This electromagnetic field can excite a dipole element with two sides. Through this excitement, the dipole element can have current flowing in a uniform direction on both sides. |
| US09653810B2 |
Waveguide fed and wideband complementary antenna
A complementary antenna (e.g., wideband complementary antenna) is presented herein. A complementary antenna can include a first dipole portion, a second dipole portion, a first electrically conductive surface, and a second electrically conductive surface. The first dipole portion can include a first patch antenna portion and a second patch antenna portion. The second dipole portion can include a third patch antenna portion and a fourth patch antenna portion electrically coupled to the second patch antenna portion via a strip antenna portion. The first electrically conductive surface can be coupled to the first dipole portion and the second dipole portion via a first set of electrically conductive pins. The second electrically conductive surface can be coupled to the first electrically conductive surface via a second set of electrically conductive pins. |
| US09653809B2 |
Antenna module and antenna thereof
The present invention provides an antenna module and an antenna thereof. The antenna includes a first radiation element, a second radiation element, a third radiation element, and a short-circuit portion. The second radiation element has one end connected with the first radiation element. The third radiation element connected with the other end of the second radiation element, and includes a first connection section, a second connection section, and a third connection section. The first connection section is perpendicular to the second radiation element. The second connection section connected with the first connection section. The third connection section is connected with the second connection section and located at an internal side of the second connection section. The short-circuit portion connected with the second connection section and located at an external side of the second connection portion. |
| US09653806B2 |
Multi-band wireless terminals with metal backplates and coupling feed elements, and related multi-band antenna systems
An antenna system for use in a portable electronic device may include first and second metal elements. One of the first and second metal elements may be provided by a metal backplate of a housing of the portable electronic device. The antenna system may additionally include a coupling feed element between the first and second metal elements of the portable electronic device. |
| US09653805B2 |
Chip packages including through-silicon via dice with vertically inegrated phased-array antennas and low-frequency and power delivery substrates
An apparatus includes a die with through-silicon vias and radio frequency integrated circuit capabilities and it is vertically integrated with a phased-array antenna substrate. The through-silicon via and a radio frequency integrated circuit is coupled to a plurality of antenna elements disposed on the phased-array antenna substrate where each of the plurality of antenna elements is coupled to the through-silicon vias and radio frequency integrated circuit through a plurality of through-silicon vias. A process of assembling the through-silicon vias and radio frequency integrated circuit to the phased-array antenna substrate includes testing the apparatus. |
| US09653804B2 |
Multi-aperture electronically scanned arrays and methods of use
An electronically scanned array (ESA) system comprises a first ESA assembly including a first antenna system coupled to a first plurality of transmit/receive modules and a second ESA assembly including a second antenna system coupled to a second plurality of transmit/receive modules. The ESA system also includes a manifold system coupled to the first and second ESA assemblies. The manifold system including an RF signal processing system for processing signals received from the first and second ESA assemblies. |
| US09653803B2 |
Radio frequency signal processing method and wireless communication device
A radio frequency signal processing method for a wireless communication device, which includes an omni-directional antenna and a plurality of directional antennas, includes receiving a request signal from a first sending node with the omni-directional antenna, sending a confirming signal to the first sending node with the omni-directional antenna, receiving a data signal from the first sending node with a first directional antenna of the plurality of directional antennas according to the request signal and a result of a training packet process, transmitting an acknowledge signal to the first sending node with the first directional antenna, and receiving follow-up signals with the omni-directional antenna. The request signal is utilized to ask the wireless communication device to receive the data signal. |
| US09653792B2 |
Window antenna loaded with a coupled transmission line filter
A window antenna wherein a silver ceramic trace is printed on an interior ply, and a connector is attached to the trace and a signal input. A length of the embedded antenna wire is oriented parallel to a coextensive length of the trace to form a coupled pass band filter. The coupled pass band filter provides a convenient feed to the antenna wire and eliminates a connection that extends from the edge of the laminate. |
| US09653783B2 |
Multiband antennas formed from bezel bands with gaps
Electronic devices are provided that contain wireless communications circuitry. The wireless communications circuitry may include radio-frequency transceiver circuitry and antenna structures. An inverted-F antenna may have first and second short circuit legs and a feed leg. The first and second short circuit legs and the feed leg may be connected to a folded antenna resonating element arm. The antenna resonating element arm and the first short circuit leg may be formed from portions of a conductive electronic device bezel. The folded antenna resonating element arm may have a bend. The bezel may have a gap that is located at the bend. Part of the folded resonating element arm may be formed from a conductive trace on a dielectric member. A spring may be used in connecting the conductive trace to the electronic device bezel portion of the antenna resonating element arm. |
| US09653781B2 |
Electronic device
An electronic device is provided. The electronic device includes a casing, a display module, and a communication module. The casing includes a first surface and a second surface. The display module is disposed on the first surface and has a display region. The communication module includes a first antenna module and a second antenna module. The first antenna module is disposed close to the display module and is corresponding perpendicularly to at least one part of the display region. The second antenna module is disposed close to the second surface. The communication module selectively receives and transmits a wireless signal along an outward direction extending from the first surface via the first antenna module or along an outward direction extending from the second surface via the second antenna module. |
| US09653779B2 |
Dual-band LTE MIMO antenna
A multiple-input-multiple output antenna for use with wireless communication comprises a first element a first radiation element operable to resonate at a first frequency and a second radiation element operable to resonate at a second frequency, wherein the second frequency is not an integer multiple of the first frequency. The first and second antenna radiation elements are each proximate to a ground plane and the respective resonance frequencies of the first radiation element and the second radiation element is achieved by controlling the electrical coupling between the first radiation element, the second radiation element and the ground plane and the resonance frequencies of the first and second radiation elements is controlled independently. |
| US09653773B2 |
Slow wave RF propagation line including a network of nanowires
The instant disclosure describes a radiofrequency propagation line including a conducting strip connected to a conducting plane parallel to the plane of the conducting strip, wherein the conducting plane includes a network of nanowires made of an electrically conductive, non-magnetic material extending orthogonally to the plane of the conducting strip, in the direction of said conducting strip. |
| US09653772B2 |
Semiconductor resonators with reduced substrate losses
A resonator includes a laminate, an inductive element on the laminate, and a semiconductor die attached to the inductive element and the laminate. The semiconductor die includes a substrate and a device layout area. The device layout area is separated into a number of device layout sub-areas, each of which has an area between about 1.0 μm2 and 100.0 μm2. By limiting the area of each one of the device layout sub-areas with the charge carrier trap trenches, the total area of the semiconductor die prone to inducement of eddy currents (i.e., the layer of accumulated charge at the interface of the substrate and the device layout area) is reduced, which in turn reduces interference with the magnetic field of the inductive element and thus improves the performance of the resonator. |
| US09653769B2 |
Connection structure between antenna apparatus and radio communication apparatus
Antenna 2 and radio communication apparatus 1 include mount portions 9 and 15, flat proximity opposing surfaces 13 and 20, and waveguide portions 12 and 19 penetrating through proximity opposing surfaces 13 and 20, respectively. For example, in proximity opposing surface 13 of radio communication apparatus 1, choke groove 14 is formed outside waveguide portion 12. With mount portions 9 and 15 of antenna 2 and radio communication apparatus 1 abutted against and fixed to each other, proximity opposing surfaces 13 and 20 are set parallel to, and directly opposite to each other with a clearance interposed therebetween so that waveguide portions 12 and 19, opposite to each other and with a clearance, form a waveguide. |
| US09653757B2 |
Nonaqueous electrolyte solution for secondary battery, and lithium secondary battery
A nonaqueous electrolyte solution for a secondary battery includes: a nonaqueous solvent including a cyclic carbonate having at least one fluoro group on a side chain thereof, a chain carbonate, and trimethylacetonitrile; and a lithium salt dissolved in the nonaqueous solvent. |
| US09653756B2 |
Magnesium compound, electrolyte solution for magnesium battery, and magnesium battery including the electrolyte solution
A magnesium compound represented by Formula 1 wherein the magnesium compound is dissolvable in an ether solvent, an electrolyte solution for magnesium batteries that includes the magnesium compound and a magnesium battery including the electrolyte solution are provided: wherein, in Formula 1, X1 is a halogen atom; and at least one of X2 and X3 each independently is an electron withdrawing group, wherein, when X2 or X3 is not an electron withdrawing group, X2 or X3 is a hydrogen atom, a C1-C20 alkyl group, or a C6-C20 aryl group. |
| US09653750B2 |
Electrode protection using a composite comprising an electrolyte-inhibiting ion conductor
Composite structures including an ion-conducting material and a polymeric material (e.g., a separator) to protect electrodes are generally described. The ion-conducting material may be in the form of a layer that is bonded to a polymeric separator. The ion-conducting material may comprise a lithium oxysulfide having a lithium-ion conductivity of at least at least 10−6 S/cm. |
| US09653747B2 |
Fuel cell with seal cut-outs on the separator in the gas passage
A fuel cell is formed by stacking a plurality of unit cells. Each of the unit cells includes a membrane electrode assembly, and an anode side metal separator and a cathode side metal separator sandwiching the membrane electrode assembly therebetween. In a surface of the cathode side metal separator, metal portions are exposed in at least part of a second flat portion in an area surrounded by seal lines SL of the anode side metal separator. Cutouts are formed on a surface of the cathode side metal separator by cutting at least part of the second flat portion up to the metal portions thereby to expose the metal portions through the cutouts. |
| US09653737B2 |
Co-deposition of conductive material at the diffusion media/plate interface
A method of depositing a conductive material is described. The method includes: providing a plate selected from anode plates, cathode plates, bipolar plates, or combinations thereof, wherein the plate includes gas flow channels; providing a diffusion media in contact with the gas flow channel side of the plate to form an assembly; introducing a gaseous precursor of the conductive material into the assembly using a chemical vapor infiltration process; infiltrating the gaseous precursor into the diffusion media and gas flow channels of the plates; and depositing a coating of the conductive material on the diffusion media, the gas flow channels of the plate, or both. An assembly having a CVI conductive coating and a fuel cell incorporating the diffusion media having the CVI conductive coating are also described. |
| US09653732B2 |
Metal phosphates and process for the preparation thereof
A process for producing a phosphate by: introducing oxidic metal(II)-, metal(III)- metal(IV) or compounds with mixed oxide stages selected from hydroxides, oxides, oxide-hydroxides, oxide-hydrates, carbonates and hydroxide carbonates, of at least one of the metals Mn, Fe, Co and Ni with the elemental forms or alloys of at least one of the metals Mn, Fe, Co and/or Ni into an aqueous medium containing phosphoric acid, and reacting the oxidic metal compounds with elemental forms or alloys of the metals to obtain divalent metal ions, removing solid substances, producing an alkali metal phosphate receiver solution with a pH-value of 5 to 8 and metering the aqueous solution into the receiver solution and at the same time metering a basic aqueous alkali hydroxide solution that the pH-value of the resulting reaction mixture is kept in the region of 5 to 8 to precipitate the desired phosphate. |
| US09653731B2 |
Layered oxide materials for batteries
Materials are presented of the formula: AxMyMiziO2−d, where A is sodium or a mixed alkali metal including sodium as a major constituent; x>0.5; M is a transition metal; y>0; Mi, for i=1, 2, 3 . . . n, is a metal or germanium; z1>0 zi≧0 for each i=2, 3 . . . n; 0 |
| US09653726B2 |
Rechargeable lithium battery comprising positive electrode comprising sacrificial positive active material
A rechargeable lithium battery including a negative electrode including a silicon-based negative active material; a positive electrode including a positive active material including a sacrificial positive active material selected from lithium nickel oxides, lithium molybdenum oxides, and combinations thereof; and a non-aqueous electrolyte, is disclosed. |
| US09653724B2 |
Secondary battery, and secondary battery module and secondary battery pack comprising the same
A secondary battery according to the present disclosure includes a cell assembly including a unit cell having at least one non-coated passage formed across an electrode plate, a temperature sensor including a temperature sensing unit located within the non-coated passage and a sensor lead extending from the temperature sensing unit, and a battery case to receive the cell assembly and which is sealed in a state that the sensor lead is drawn outside.According to the present disclosure, a temperature change of the secondary battery may be measured quickly and correctly, and thus, the secondary battery may be controlled more minutely in response to a temperature change, and gas generated in the battery case during charging and discharging of the secondary battery may be easily discharged to a surrounding area of the cell assembly, thereby preventing a battery efficiency reduction phenomenon. |
| US09653723B2 |
Battery terminal, fuse unit, and method for manufacturing fuse unit
A battery terminal includes a terminal main body provided in opposed plates thereof as a pair, formed by folding approximately in a U shape a strip plate made of a conductive metal, respectively with electrode insertion holes in which a rod-like electrode projecting from a terminal attaching surface in a battery is sequentially inserted, and formed to extend toward an outer edge of the terminal attaching surface at time of being connected to the rod-like electrode, and a joint joining the pair of the opposed plates in a state in which the opposed plates surface-contact and overlap each other on an opposite side of a folded part as seen from the electrode insertion hole. |
| US09653720B2 |
Traction battery assembly
A traction battery assembly includes adjacent battery cells supported by a tray and a busbar electrically connecting the adjacent battery cells. The busbar includes a longitudinal midpoint and a pair of bowed sections joined at the midpoint. Each of the bowed sections has an actuate portion in contact with a terminal on one of the cells. The bowed sections provide increased contact with the cells when the cells have different elevations with respect to the tray. A busbar module is also disclosed. The busbar module comprises a housing and a busbar supported within the housing. |
| US09653716B2 |
Manufacturing method for battery case lid including explosion-proof valve
A battery case lid is formed by working a metal plate, and includes a substrate section and an explosion-proof valve formed in the substrate section. The explosion-proof valve has a reduced thickness section that is thinner than the substrate section, and the reduced thickness section is formed by extending the metal plate by applying pressure while the metal plate is kept unrestrained. |
| US09653714B2 |
Electric storage device and electric storage apparatus
An electric storage device is provided with an electrode assembly including a positive electrode plate and a negative electrode plate; a case for housing the electrode assembly; a positive-electrode external terminal arranged on an outer surface of the case and electrically connected to the positive electrode plate; a negative-electrode external terminal arranged on an outer surface of the case and electrically connected to the negative electrode plate; and a gas exhaust valve formed in a region of the case on the opposite side of a region where the positive-electrode external terminal and the negative-electrode external terminal are arranged. |
| US09653712B2 |
Battery module having assembly coupling structure
Disclosed herein is a battery module including a battery cell array including two or more stacked battery cells, each of which is configured to have a structure in which an electrode assembly, including a cathode, an anode, and a separator disposed between the cathode and the anode, is received in a battery case together with an electrolyte in a sealed state, and fixing members, each of which is integrally coupled to a portion or the entirety of an outer edge of a corresponding one of the battery cells, each of the fixing members being provided with an assembly type coupling structure, by which the fixing members are coupled to each other such that the battery cell array forms a stable stack structure. |
| US09653711B2 |
Flat battery
There is provided a flat battery including a positive electrode can, a negative electrode can, a positive electrode material, a negative electrode material, and a positive electrode ring provided on an inner surface of a bottom of the positive electrode can to hold one of the positive electrode material and the negative electrode material. The positive electrode ring has a side wall and a flange that extends outward to overlap an open end of a circumferential wall of the negative electrode can. The flange is placed between the open end of the circumferential wall of the negative electrode can and the inner surface of the bottom of the positive electrode can. |
| US09653707B2 |
Organic light emitting diode display
An organic light emitting diode display includes: a first electrode positioned over the substrate; an organic emission layer positioned over the first electrode; a second electrode positioned over the organic emission layer; a refractive layer positioned over the second electrode; and a light transflective metal layer positioned over the refractive layer. |
| US09653706B2 |
Organic electroluminescent element, lighting device, lighting system, and method for manufacturing organic electroluminescent element
According to one embodiment, an organic electroluminescent element includes a first electrode, an organic layer, and a second electrode. The first electrode is light-transmissive. The organic layer is provided on the first electrode. The second electrode is provided on the organic layer. The second electrode is light-reflective and includes a first conductive portion and a second conductive portion. The first conductive portion extends in a first direction. The second conductive portion extends in a second direction intersecting the first direction. The second conductive portion intersects the first conductive portion. A length in the first direction of the first conductive portion is longer than 1 mm and not more than 47 mm. A length in the second direction of the second conductive portion is longer than 1 mm and not more than 47 mm. |
| US09653705B2 |
Light-emitting element
An electrode layer having high reflectance and a light-emitting element having high emission efficiency are provided. The light-emitting element includes a first electrode layer, a second electrode layer, and an EL layer between the first electrode layer and the second electrode layer. The first electrode layer includes a conductive layer and an oxide layer in contact with the conductive layer. The conductive layer has a function of reflecting light. The oxide layer includes In and M (M represents Al, Si, Ti, Ga, Y, Zr, Sn, La, Ce, Nd, or Hf). A content of the M in the oxide layer is higher than or equal to a content of the In. |
| US09653702B2 |
Electroluminescent device
In an organic EL display device (electroluminescent device) including an organic EL element (electroluminescent element), a sealing film is provided to seal the organic EL element, and a projection (preventing portion) is configured to prevent the sealing film from peeling off and to have an inclined plane forming an obtuse angle with a light emitting surface of the organic EL element. The projection is provided only in a non-light emitting region of the organic EL element. |
| US09653700B2 |
Methods for making optical components, optical components, and products including same
Methods for making multiple hermetically sealed optical components are disclosed. Methods for making an individual hermetically sealed optical component are disclosed. An individual hermetically sealed optical component and products including same are also disclosed. |
| US09653696B2 |
Tin perovskite/silicon thin-film tandem solar cell
A method of making a non-toxic perovskite/inorganic thin-film tandem solar cell including the steps of depositing a textured oxide buffer layer on an inexpensive substrate, depositing a metal-inorganic film from a eutectic alloy on the buffer layer; and depositing perovskite elements on the metal-inorganic film, thus forming a perovskite layer based on a metal from the metal-inorganic film, incorporating the metal into the perovskite layer. |
| US09653694B2 |
Precursor dielectric composition with thiosulfate-containing polymers
A precursor dielectric composition comprises: (1) a photocurable or thermally curable thiosulfate-containing polymer that has a Tg of at least 50° C. and comprises: an organic polymer backbone comprising (a) recurring units comprising pendant thiosulfate groups; and organic charge balancing cations, (2) optionally, an electron-accepting photosensitizer component, and (3) one or more organic solvents in which the photocurable or thermally curable thiosulfate-containing polymer is dissolved or dispersed. These precursor dielectric compositions can be applied to various substrates and eventually cured to form dielectric compositions or layers for various types of electronic devices. |
| US09653691B2 |
Phosphorescence-sensitizing fluorescence material system
Novel molecules are provided that include a sensitizer group, an acceptor group, and an electron-transfer barrier that suppresses triplet-triplet energy transfer between the sensitizer group and the acceptor group. Organic light emitting devices (OLEDs) that include a layer including these novel molecules are also provided. These devices may be used to provide highly efficient OLEDs with longer operational lifetime. |
| US09653689B2 |
Condensed-cyclic compound and organic light-emitting diode including the same
A condensed-cyclic compound represented by Formula 1 below, and an organic light-emitting diode including the condensed-cyclic compound. wherein R1 through R6, Ar5 and Ar6, and X1 through X10 are defined as in the specification. |
| US09653687B2 |
Materials for organic electroluminescent devices
The present invention relates to a mixture comprising a) a polymer which contains at least one L=X structural unit, b) a triplet emitter compound and c) a carbazole compound or a soluble neutral molecule. The invention furthermore relates to organic electroluminescent devices which contain the mixture according to the invention. |
| US09653686B2 |
Organic film transistor, organic semiconductor film, organic semiconductor material and application of these
An organic film transistor containing a compound, which is composed of n repeating units represented by Formula (1-1), (1-2), or (101), in a semiconductor active layer is an organic film transistor using a compound that results in high carrier mobility when being used in the semiconductor active layer of the organic film transistor and exhibits high solubility in an organic solvent; (Each of R1 R2 represents a hydrogen atom or a substituent; each of Ar1 and Ar2 independently represents a heteroarylene group or an arylene group; V1 represents a divalent linking group; m represents an integer of 0 to 6; cy represents a naphthalene ring or an anthracene ring; each of R3 and R4 represents a hydrogen atom or a substituent; each of Ar3 and Ar4 represents a heterocyclic aromatic ring or an aromatic ring; V2 represents a divalent linking group; p represents an integer of 0 to 6; n represents an integer of equal to or greater than 2; A is a divalent linking group represented by Formula (101′); each of RA1 to RA6 represents a hydrogen atom, a substituent, or a direct bond with Ar101 or Ar102 in Formula (101); and among the groups represented by RA1 to RA6, two different groups are direct bonds with Ar101 and Ar102 in Formula (101) respectively.) |
| US09653684B2 |
Semiconductor memory device
A semiconductor memory device according to an embodiment comprises a memory cell array configured from a plurality of row lines and column lines that intersect one another, and from a plurality of memory cells disposed at each of intersections of the row lines and column lines and each including a variable resistance element. Where a number of the row lines is assumed to be N, a number of the column lines is assumed to be M, and a ratio of a cell current flowing in the one of the memory cells when a voltage that is half of the select voltage is applied to the one of the memory cells to a cell current flowing in the one of the memory cells when the select voltage is applied to the one of the memory cells is assumed to be k, a relationship M2<2×N×k is satisfied. |
| US09653683B2 |
Phase change memory cell with improved phase change material
A phase change memory cell. The phase change memory cell includes a substrate and a phase change material. The phase change material is deposited on the substrate for performing a phase change function in the phase change memory cell. The phase change material is an alloy having a mass density change of less than three percent during a transition between an amorphous phase and a crystalline phase. |
| US09653682B1 |
Resistive random access memory structure
The present disclosure provides a semiconductor structure, including an Nth metal layer, a planar bottom barrier layer over and in contact with the Nth metal layer, a data storage layer over the planar bottom barrier layer, an electrode over the data storage layer, and an (N+1)th metal layer over the electrode. N is a positive integer. A manufacturing method for the semiconductor structure is also provided. |
| US09653679B1 |
Magnetoresistive structures with stressed layer
A method of making a magnetoresistive structure is disclosed. The method includes forming a pillar structure including a magnetic tunnel junction on a substrate that includes a first electrode, depositing a stressed layer onto a pillar structure sidewall, and depositing a second electrode above the magnetic tunnel junction. |
| US09653676B2 |
Method for manufacturing piezoelectric device
A method for manufacturing a piezoelectric device including a piezoelectric thin film, a support member, a first electrode, and a cavity formed at a support member side of the first electrode between the piezoelectric thin film and the support member includes forming a sacrificial layer in an area to define the cavity, forming an etching adjustment layer which adjusts progress of etching in a region where the first electrode is exposed to a side of the piezoelectric thin film, simultaneously forming a through hole through which a portion of the sacrificial layer is exposed to the side of the piezoelectric thin film and an opening which the first electrode is exposed to the side of the piezoelectric thin film by etching the piezoelectric thin film and the etching adjustment layer, and removing the sacrificial layer through the through hole. |
| US09653674B2 |
Contact electrification effect-based back gate field-effect transistor
The present invention provides a contact electrification effect-based back gate field-effect transistor. The back gate field-effect transistor includes: a conductive substrate; an insulating layer formed on a front face of the conductive substrate; a field-effect transistor assembly including: a channel layer, a drain and a source, and a gate; and a triboelectric nanogenerator assembly including: a static friction layer formed at a lower surface of the gate, a movable friction layer disposed opposite to the static friction layer and separated by a preset distance, and a second electro-conductive layer formed at an outside of the movable friction layer and being electrically connected to the source; wherein, the static friction layer and the movable friction layer are made of materials in different ratings in triboelectric series, and the static friction layer and the movable friction layer are switchable between a separated state and a contact state under the action of an external force. |
| US09653672B2 |
Thermoelectric materials, thermoelectric module including thermoelectric materials, and thermoelectric apparatus including thermoelectric modules
A thermoelectric material containing a dichalcogenide compound represented by Formula 1 and having low thermoelectric conductivity and high Seebeck coefficient: RaTbX2-nYn (1) wherein R is a rare earth element, T includes at least one element selected from the group consisting of Group 1 elements, Group 2 elements, and a transition metal, X includes at least one element selected from the group consisting of S, Se, and Te, Y is different from X and includes at least one element selected from the group consisting of S, Se, Te, P, As, Sb, Bi, C, Si, Ge, Sn, B, Al, Ga and In, a is greater than 0 and less than or equal to 1, b is greater than or equal to 0 and less than 1, and n is greater than or equal to 0 and less than 2. |
| US09653671B2 |
Light emitting device and method for operating a plurality of light emitting arrangements
According to various examples, systems, methods, and devices for a light emitting device are described herein. As one example, a light emitting device includes a light emitting element and a capacitor. The capacitor is configured as a voltage buffer for the light emitting element and is further configured to dissipate heat from the light emitting element. According to another example, a carrier for a light emitting arrangement is described herein. According to this example, the carrier includes a capacitor configured to buffer a voltage of the light emitting arrangement. The carrier further includes a contacting structure configured for electrically contacting the light emitting arrangement and the capacitor. The capacitor and the contacting structure are arranged such that the capacitor is configured to dissipate heat from the light emitting arrangement. |
| US09653668B2 |
LED filament and filament-type LED bulb
A LED filament and a LED filament bulb using the same are disclosed. The LED filament includes a carrier, a LED chip disposed on the carrier and a conductive lead connected to the carrier. The conductive lead is electrically connected to the LED chip and includes a lead head portion, a lead tail portion and a lead neck portion connecting the lead head portion with the lead tail portion. A solid body width of the lead neck portion is less than a maximum solid body width of the lead head portion. Because the lead neck portion with reduced solid body width can function as a vulnerable position of the conductive lead, when a stress is applied onto the conductive lead, the lead neck portion would first take action and therefore the bonding location between the lead head portion and the carrier or the carrier itself can be protected. |
| US09653667B2 |
Light emitting device having a connection part electrically coupled a first electrode and a conductive support member
A light emitting device includes a light emitting structure including a first conductive semiconductor layer, an active layer under the first conductive semiconductor layer, and a second conductive semiconductor layer adjacent the active layer. A first electrode is electrically coupled to the first conductive semiconductor layer, and a second electrode is electrically coupled to the second conductive semiconductor layer. A channel layer is provided at a peripheral portion of a lower portion of the light emitting structure, and a conductive support member is provided adjacent to the second electrode. A first connection part is electrically coupled to the first electrode and the conductive support member, and a second connection part is electrically coupled to the second electrode. |
| US09653666B2 |
Light-emitting device and the manufacturing method thereof
A method of manufacturing a light-emitting device comprises the steps of: providing a substrate; forming a mask block contacting the substrate and exposing a portion of the substrate; implanting an ion into the portion of the substrate to form an ion implantation region; and forming a semiconductor stack on the substrate such that multiple cavities are formed between the semiconductor stack and the ion implantation region; wherein the mask block comprises a material made of metal or oxide. |
| US09653665B2 |
LED dome with inner high index pillar
Affixed over a transparent growth substrate (34) of an LED die (30) is a transparent rectangular pillar (40), having a footprint approximately the same size as the LED die. The pillar height is greater than a length of the LED die, and the pillar has an index (n) approximately equal to that of the substrate (e.g., 1.8), so there is virtually no TIR at the interface due to the matched indices. Surrounding the pillar and the LED die is a lens portion (42) having a diameter between 1.5-3 times the length of the LED die. The index of the lens portion is about 0.8 times the index of the substrate. The lens portion may have a dome shape (46). A large portion of the light exiting the substrate is internally reflected off the lateral pillar/cylinder interface and exits the top surface of the pillar. Thus, the emission is narrowed and light extraction efficiency is increased. |
| US09653655B2 |
Light emitting diodes with zinc oxide current spreading and light extraction layers deposited from low temperature aqueous solution
A method for fabricating a Light Emitting Diode (LED) with increased light extraction efficiency, comprising providing a III-Nitride based LED structure comprising a light emitting active layer between a p-type layer and an n-type layer; growing a Zinc Oxide (ZnO) layer epitaxially on the p-type layer by submerging a surface of the p-type layer in a low temperature aqueous solution, wherein the ZnO layer is a transparent current spreading layer; and depositing a p-type contact on the ZnO layer. The increase in efficiency may be more than 93% with very little or no increase in cost. |
| US09653653B2 |
Light emitting diode device
A light emitting diode device is provided. The light emitting diode device has a substrate, a plurality of metal pads, a plurality of LEDs and a first metal conductive wire. A plurality of first metal pads of the metal pads are disposed on a first surface of the substrate, and the LEDs are disposed on a part of the first metal pads. Each of the LEDs has at least one first electrode contact. The first electrode contact of each of the LEDs electrically connected to the first metal conductive wire has the same electrode contact polarity. Moreover, another light emitting diode device is also provided. |
| US09653650B2 |
Method and system for epitaxy processes on miscut bulk substrates
A method for providing (Al,Ga,In)N thin films on Ga-face c-plane (Al,Ga,In)N substrates using c-plane surfaces with a miscut greater than at least 0.35 degrees toward the m-direction. Light emitting devices are formed on the smooth (Al,Ga,In)N thin films. Devices fabricated on the smooth surfaces exhibit improved performance. |
| US09653646B2 |
Semiconductor layer sequence and method of producing the same
A semiconductor layer sequence includes an n-conducting n-type side, a p-conducting p-type side, and an active zone between the sides, the active zone simultaneously generating a first radiation having a first wavelength and a second radiation having a second wavelength, the active zone including at least one radiation-active layer having a first material composition that generates the first radiation, the at least one radiation-active layer is oriented perpendicular to a growth direction of the semiconductor layer sequence, the active zone includes a multiplicity of radiation-active tubes having a second material composition and/or having a crystal structure that generates the second radiation, which crystal structure deviates from the at least one radiation-active layer, and the radiation-active tubes are oriented parallel to the growth direction, the radiation-active tubes having an average diameter of 5 nm to 100 nm and an average surface density of the radiation-active tubes of 108 1/cm2 to 1011 1/cm2. |
| US09653643B2 |
Wafer level packaging of light emitting diodes (LEDs)
An LED wafer includes LED dies on an LED substrate. The LED wafer and a carrier wafer are joined. The LED wafer that is joined to the carrier wafer is shaped. Wavelength conversion material is applied to the LED wafer that is shaped. Singulation is performed to provide LED dies that are joined to a carrier die. The singulated devices may be mounted in an LED fixture to provide high light output per unit area. |
| US09653641B2 |
Light emitting device and projector
In a light emitting device, a light waveguide is provided with a first region including a central position, a second region including a first light emission surface, and a third region including a second light emission surface. A second cladding layer includes a plurality of noncontact regions. The plurality of noncontact regions intersect the light waveguide. A ratio of an area in which the plurality of noncontact regions overlap the first region to an area of the first region is greater than a ratio of an area in which the plurality of noncontact regions overlap the second region to an area of the second region, and is greater than a ratio of an area in which the plurality of noncontact regions overlap the third region to an area of the third region. |
| US09653639B2 |
Laser using locally strained germanium on silicon for opto-electronic applications
The subject matter disclosed herein relates to formation of silicon germanium devices with tensile strain. Tensile strain applied to a silicon germanium device in fabrication may improve performance of a silicon germanium laser or light detector. |
| US09653638B2 |
Contacts for solar cells formed by directing a laser beam with a particular shape on a metal foil over a dielectric region
A method of fabricating a solar cell is disclosed. The method can include forming a dielectric region on a surface of a solar cell structure and forming a metal layer on the dielectric layer. The method can also include configuring a laser beam with a particular shape and directing the laser beam with the particular shape on the metal layer, where the particular shape allows a contact to be formed between the metal layer and the solar cell structure. |
| US09653635B2 |
Flexible high-voltage adaptable current photovoltaic modules and associated methods
A flexible photovoltaic module for converting light into an electric current includes a plurality of electrically interconnected flexible photovoltaic submodules monolithically integrated onto a common flexible substrate. Each photovoltaic submodule includes a plurality of electrically interconnected flexible thin-film photovoltaic cells monolithically integrated onto the flexible substrate. A flexible photovoltaic module for converting light into an electric current includes a backplane layer for supporting the photovoltaic module. A first pottant layer is disposed on the backplane layer, and a photovoltaic submodule assembly is disposed on the first pottant layer. The photovoltaic submodule assembly has at least one photovoltaic submodule, where each photovoltaic submodule includes a plurality of thin-film photovoltaic cells. A second pottant layer is disposed on the photovoltaic submodule assembly, and a upper laminate layer disposed on the second pottant layer. |
| US09653634B2 |
Interlocking edges having electrical connectors for building integrable photovoltaic modules
Provided are novel building integrable photovoltaic (BIP) modules that are mechanically and electrically interconnectable. According to various embodiments, the modules include channels and protrusion members. A channel of one module snugly fits over a protrusion member of an adjacent module to provide a moisture seal and, in certain embodiments, to collect water in between two modules and direct it downward. In certain embodiments, a channel is configured to interlock with a protrusion member in one or more directions. The channel is positioned along one edge of the module, while the protrusion member is positioned along the opposite edge, so that BIP modules can form a continuous interconnected row. The channel and protrusion member include electrical connectors having conductive elements. Inserting a protrusion member into a channel and, in certain embodiments, sliding one with respect to another also electrically interconnects the conductive elements. |
| US09653633B2 |
Solar cell, electronic device, and manufacturing method of solar cell
A power generating film is disposed on a substrate, a transparent conductive film is disposed on the power generating film in an overlapping manner, a first insulating film having a thickness of greater than or equal to 1 μm is disposed on the transparent conductive film, and the substrate is formed into a predetermined shape by irradiating the substrate with laser light which is condensed thereto and by spraying gas onto the substrate. |
| US09653624B2 |
Optical sensor device
The following configuration is adopted in order to provide a highly reliable optival sensor device which enhances the reliability of devices without making the devices unsuitable for size and thickness reductions. The light sensor comprises an element-mounting portion (3) having a cavity and a lid member closely attached thereinto, the lid member being composed of: a window (2) constituted of a phosphate-based glass to which properties approximate to a spectral luminous efficacy properties have been imparted by compositional control; and a frame (1) constituted of a phosphate-based glass having light-shielding properties. The lid member is aLaminated glass member obtained by cutting the phosphate-based glass having the spectral luminous efficacy properties into individual pieces, fitting the glass piece into the opening of the phosphate-based glass (1) having light-shielding properties, the opening having been formed so as to have a size approximately equal to the cavity size, and melting and integrating the glasses member. |
| US09653616B2 |
Display panel and display device using the same
A display panel comprising a TFT substrate, a display medium and an opposite substrate is provided. The display medium is disposed between the TFT substrate and the opposite substrate. The TFT substrate comprises a substrate, a first electrode layer, a pixel electrode layer, a first insulating layer, a second electrode layer, a second insulating layer, a channel layer and an over coating layer. The first electrode layer and the pixel electrode layer are disposed on the substrate. The first insulating layer is disposed on the first electrode layer and the pixel electrode layer. The second electrode layer is disposed on the first insulating layer. The second insulating layer is disposed on the second electrode layer. The channel layer is interposed into a first contact hole and a second contact hole to electrically connect the first electrode layer. The over coating layer is disposed on the channel layer. |
| US09653615B2 |
Hybrid ETSOI structure to minimize noise coupling from TSV
In one aspect, a method for forming an electronic device includes the following steps. An ETSOI layer of an ETSOI wafer is patterned into one or more ETSOI segments each of the ETSOI segments having a width of from about 3 nm to about 20 nm. A gate electrode is formed over a portion of the one or more ETSOI segments which serves as a channel region of a transistor, wherein portions of the one or more ETSOI segments extending out from under the gate electrode serve as source and drain regions of the transistor. At least one TSV is formed in the ETSOI wafer adjacent to the transistor. An electronic device is also provided. |
| US09653611B2 |
Semiconductor device
[Problem] To provide a semiconductor device suitable for miniaturization. To provide a highly reliable semiconductor device. To provide a semiconductor device with improved operating speed.[Solving Means] A semiconductor device including a memory cell including first to cth (c is a natural number of 2 or more) sub memory cells, wherein: the jth sub memory cell includes a first transistor, a second transistor, and a capacitor; a first semiconductor layer included in the first transistor and a second semiconductor layer included in the second transistor include an oxide semiconductor; one of terminals of the capacitor is electrically connected to a gate electrode included in the second transistor; the gate electrode included in the second transistor is electrically connected to one of a source electrode and a drain electrode which are included in the first transistor; and when j≧2, the jth sub memory cell is arranged over the j−1th sub memory cell. |
| US09653607B2 |
Thin film transistor and manufacturing method thereof
A thin film transistor (TFT) includes a semiconductive layer, a first inter-layer drain (ILD) layer, a second ILD layer, and at least one contact hole passing through the first ILD layer and the second ILD layer. The semiconductive layer includes a channel region, a first lightly doped drain (LDD) region, a second LDD region, a first heavily doped drain (HDD) region, and a second HDD region. The at least one contact hole includes a first portion passing through the second ILD layer and a second portion passing through the first ILD layer. The second portion gradually narrows along a direction from a top to a bottom of the first ILD layer. |
| US09653606B2 |
Fabrication process for mitigating external resistance of a multigate device
A method for fabricating a multigate device includes forming a fin on a substrate of the multigate device, the fin being formed of a semiconductor material, growing a first conformal epitaxial layer directly on the fin and substrate, wherein the first conformal epitaxial layer is highly doped, growing a second conformal epitaxial layer directly on the first conformal epitaxial layer, wherein the second conformal epitaxial layer is highly doped, selectively removing a portion of second epitaxial layer to expose a portion of the first conformal epitaxial layer, selectively removing a portion of the first conformal epitaxial layer to expose a portion of the fin and thereby form a trench, and forming a gate within the trench. |
| US09653605B2 |
Fin field effect transistor (FinFET) device and method for forming the same
A fin field effect transistor (FinFET) device structure and method for forming FinFET device structure are provided. The FinFET structure includes a substrate and a fin structure extending above the substrate. The FinFET structure includes an epitaxial structure formed on the fin structure, and the epitaxial structure has a first height. The FinFET structure also includes fin sidewall spacers formed adjacent to the epitaxial structure. The sidewall spacers have a second height and the first height is greater than the second height, and the fin sidewall spacers are configured to control a volume and the first height of the epitaxial structure. |
| US09653604B1 |
Semiconductor device and manufacturing method thereof
A semiconductor device includes a fin structure disposed over a substrate, a gate structure and a source. The fin structure includes an upper layer being exposed from an isolation insulating layer. The gate structure disposed over part of the upper layer of the fin structure. The source includes the upper layer of the fin structure not covered by the gate structure. The upper layer of the fin structure of the source is covered by a crystal semiconductor layer. The crystal semiconductor layer is covered by a silicide layer formed by Si and a first metal element. The silicide layer is covered by a first metal layer. A second metal layer made of the first metal element is disposed between the first metal layer and the isolation insulating layer. |
| US09653603B1 |
Semiconductor device and method for fabricating the same
A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a recess in the substrate; forming a buffer layer in the recess; forming an epitaxial layer on the buffer layer; and removing part of the epitaxial layer, part of the buffer layer, and part of the substrate to form fin-shaped structures. |
| US09653601B2 |
Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink-harmonic wrinkle reduction
A method and apparatus for use in improving linearity sensitivity of MOSFET devices having an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to address degradation in second- and third-order intermodulation harmonic distortion at a desired range of operating voltage in devices employing an accumulated charge sink. |
| US09653598B2 |
Transistor component
A transistor component includes a semiconductor body, a first main electrode, a gate contact electrode, a plurality of transistor cells, and a plurality of gate electrodes. The semiconductor body has a drain region and a drift region of a first conduction type, and a body region of a second conduction type. The first main electrode is on a top side of the semiconductor body. The plurality of gate electrodes is electrically connected to the gate contact electrode and arranged successively in a first lateral direction. In the plurality, a first gate electrode is next to a second gate electrode. The first main electrode includes a first trench contact finger, between the first gate electrode and the second gate electrode, and a second trench contact finger, between the first gate electrode and the second gate electrode, electrically connecting the first main electrode to the body region. |
| US09653597B2 |
Method for fabricating a shallow and narrow trench FET and related structures
Disclosed is a method for fabricating a shallow and narrow trench field-effect transistor (trench FET). The method includes forming a trench within a semiconductor substrate of a first conductivity type, the trench including sidewalls and a bottom portion. The method further includes forming a substantially uniform gate dielectric in the trench, and forming a gate electrode within said trench and over said gate dielectric. The method also includes doping the semiconductor substrate to form a channel region of a second conductivity type after forming the trench. In one embodiment, the doping step is performed after forming the gate dielectric and after forming the gate electrode. In another embodiment, the doping step is performed after forming the gate dielectric, but prior to forming the gate electrode. Structures formed by the invention's method are also disclosed. |
| US09653594B2 |
Semiconductor device and method for forming the same
A system and method for forming and using a liner is provided. An embodiment comprises forming an opening in an inter-layer dielectric over a substrate and forming the liner along the sidewalls of the opening. A portion of the liner is removed from a bottom of the opening, and a cleaning process may be performed through the liner. By using the liner, damage to the sidewalls of the opening from the cleaning process may be reduced or eliminated. Additionally, the liner may be used to help implantation of ions within the substrate. |
| US09653593B2 |
Method of fabricating FinFET device and structure thereof
The present disclosure provides a FinFET device and method of fabricating a FinFET device. The method includes providing a substrate, forming a fin structure on the substrate, forming a gate structure including a gate dielectric and gate electrode, the gate structure overlying a portion of the fin structure, forming a protection layer over another portion of the fin structure, and thereafter performing an implantation process to form source and drain regions. |
| US09653592B2 |
Method for fabricating semiconductor device and semiconductor device
A method for fabricating a semiconductor device includes: forming a metal pattern including nickel on a semiconductor layer, the metal pattern having upper and side surfaces; forming a mask pattern having an opening in which upper and side surfaces of the metal pattern therein being exposed; forming a barrier layer on the metal pattern exposed in the opening by a plating method; and forming a conducting layer on the barrier layer exposed in the opening. |
| US09653590B2 |
Compound semiconductor device and method of manufacturing the same
A compound semiconductor device includes: a semiconductor substrate; a channel layer over the semiconductor substrate; a carrier supply layer over the channel layer; and a gate electrode, a source electrode and a drain electrode above the carrier supply layer. The semiconductor substrate includes an impurity-containing region containing an impurity, the impurity forms a level lower than a lower edge of a conduction band of silicon by 0.25 eV or more, the impurity forms the level higher than an upper edge of a valence band of silicon. |
| US09653589B2 |
Semiconductor multi-layer substrate, semiconductor device, and method for manufacturing the same
A semiconductor multi-layer substrate includes a substrate made of Si and a multi-layer semiconductor layer. The multi-layer semiconductor layer includes an active layer made of a nitride semiconductor, a first warp control layer being formed between the substrate and the active layer and giving a predetermined warp to the substrate, and a second warp control layer made of a nitride semiconductor of which amount of an increase in a warp per a unit thickness is smaller than an amount of increase in the warp per a unit thickness of the first warp control layer. A total thickness of the multi-layer semiconductor layer is equal to or larger than 4 μm. |
| US09653587B2 |
IE type trench gate IGBT
In a method of further enhancing the performance of a narrow active cell IE type trench gate IGBT having the width of active cells narrower than that of inactive cells, it is effective to shrink the cells so that the IE effects are enhanced. However, when the cells are shrunk simply, the switching speed is reduced due to increased gate capacitance. A cell formation area of the IE type trench gate IGBT is basically composed of first linear unit cell areas having linear active cell areas, second linear unit cell areas having linear hole collector areas and linear inactive cell areas disposed therebetween. |
| US09653583B1 |
Methods of forming diffusion breaks on integrated circuit products comprised of finFET devices
One illustrative method disclosed herein includes, among other things, forming a first gate structure above a fin, forming epi semiconductor material on the fin, performing at least one first etching process through a patterned sacrificial layer of material to remove at least a gate cap layer and sacrificial gate materials of the first gate structure so as to define a first isolation cavity that exposes the fin while leaving the second gate structure intact, performing at least one second etching process through the first isolation cavity to remove at least a portion of a vertical height of the fin and thereby form a first isolation trench, removing the patterned sacrificial layer of material, and forming a layer of insulating material above the epi semiconductor material and in the first isolation trench and in the first isolation cavity. |
| US09653581B2 |
Semiconductor device and method of making
A semiconductor device is provided. The semiconductor device includes a channel region disposed between a source region and a drain region, a gate structure over the channel region, an interlayer dielectric (ILD) layer proximate the gate structure, an ILD stress layer proximate the top portion of gate structure and over the ILD layer. The gate structure includes a first sidewall, a second sidewall and a top portion. A first stress memorization region is also provided. The first stress memorization region is proximate the top portion of the gate structure. A method of making a semiconductor device is also provided. |
| US09653579B2 |
Method for making semiconductor device with filled gate line end recesses
A method for making a semiconductor device may include forming first and second spaced apart semiconductor active regions with an insulating region therebetween, forming at least one sacrificial gate line extending between the first and second spaced apart semiconductor active regions and over the insulating region, and forming sidewall spacers on opposing sides of the at least one sacrificial gate line. The method may further include removing portions of the at least one sacrificial gate line within the sidewall spacers and above the insulating region defining at least one gate line end recess, filling the at least one gate line end recess with a dielectric material, and forming respective replacement gates in place of portions of the at least one sacrificial gate line above the first and second spaced apart semiconductor active regions. |
| US09653574B2 |
Selective etching in the formation of epitaxy regions in MOS devices
A method for forming a semiconductor structure includes forming a gate stack over a semiconductor substrate; forming a recess in the semiconductor substrate and adjacent the gate stack; and performing a selective epitaxial growth to grow a semiconductor material in the recess to form an epitaxy region. After the step of performing the selective epitaxial growth, a selective etch-back is performed to the epitaxy region. The selective etch-back is performed using process gases comprising a first gas for growing the semiconductor material, and a second gas for etching the epitaxy region. |
| US09653571B2 |
Freestanding spacer having sub-lithographic lateral dimension and method of forming same
An aspect of the invention includes a freestanding spacer having a sub-lithographic dimension for a sidewall image transfer process. The freestanding spacer comprises: a first spacer layer having a first portion disposed on the semiconductor layer; and a second spacer layer having a first surface disposed on the first portion of the first spacer layer, wherein the first spacer layer has a first dielectric constant and the second spacer layer has a second dielectric constant, the first dielectric constant being greater than the second dielectric constant, and wherein a dimension of each of the first and second spacer layers collectively determine the sub-lithographic lateral dimension of the freestanding spacer. |
| US09653567B2 |
Lateral bipolar transistor
A bipolar junction transistor comprises a semiconductor layer disposed on an insulating material, at least a portion of the semiconductor layer forming a base region. The bipolar junction transistor further comprises a transistor emitter laterally disposed on a first side of the base region, where in the transistor emitter is a first doping type and has a first width, and wherein the first width is a lithographic feature size. The bipolar junction transistor further comprises a transistor collector laterally disposed on a second side of the base region, wherein the transistor collector is the first doping type and the first width. The bipolar junction transistor further comprises a central base contact laterally disposed on the base region between the transistor emitter and the transistor collector, wherein the central base contact is a second doping type and has a second width, and wherein the second width is a sub-lithographic feature size. |
| US09653566B2 |
Bipolar junction transistors with an air gap in the shallow trench isolation
Device structures, fabrication methods, and design structures for a bipolar junction transistor. A trench isolation region is formed in a substrate. The trench isolation region is coextensive with a collector in the substrate. A base layer is formed on the collector and on a first portion of the trench isolation region. A dielectric layer is formed on the base layer and on a second portion of the trench isolation region peripheral to the base layer. After the dielectric layer is formed, the trench isolation region is at least partially removed to define an air gap beneath the dielectric layer and the base layer. |
| US09653565B2 |
Semiconductor devices and methods of fabricating the same
A three dimensional semiconductor memory device includes a vertical channel structure extending in a vertical direction on a substrate; interlayer insulating layers surrounding the vertical channel structure and being stacked in the vertical direction on the substrate, gate electrodes surrounding the vertical channel structure and being disposed between the interlayer insulating layers, corners of the gate electrodes adjacent to the vertical channel structure being rounded, and auxiliary gate insulating patterns disposed between the gate electrodes and the vertical channel structure, wherein a side surface of the auxiliary gate insulating pattern is substantially coplanar with a side surface of the interlayer insulating layer in the vertical direction on the substrate. |
| US09653559B2 |
Methods to enhance doping concentration in near-surface layers of semiconductors and methods of making same
A die includes a semiconductive prominence and a surface-doped structure on the prominence. The surface-doped structure makes contact with contact metallization. The prominence may be a source- or drain contact for a transistor. Processes of making the surface-doped structure include wet-vapor- and implantation techniques, and include annealing techniques to drive in the surface doping to only near-surface depths in the semiconductive prominence. |
| US09653558B2 |
Semiconductor structure having a dummy contact and manufacturing method thereof
A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a substrate, a source region, a drain region, a gate, and a dummy contact. The source region and the drain region are formed in the substrate. The gate is formed on the substrate and between the source region and the drain region. The dummy contact includes a plurality of dummy plugs formed on the substrate, wherein the dummy plugs have depths decreasing towards the drain region. |
| US09653556B1 |
Field plate for high-voltage field effect transistors
A high voltage semiconductor structure with a field plate comprising a depletable material that increases the breakdown voltage of the semiconductor structure. A depletion region forms within the depletable field plate which redistributes the electric field and preventing electric charges from concentrating at the corners of the field plate. The thickness, doping concentration, doping uniformity, and geometric shape of the field plates may be adjusted to optimize the effect of the charge redistribution. |
| US09653555B2 |
Depression filling method and processing apparatus
A method of filling a depression of a workpiece is provided. The depression passes through an insulating film and extends up to an inside of a semiconductor substrate. The method includes forming a first thin film made of a semiconductor material along a wall surface which defines the depression, performing gas phase doping on the first thin film, by annealing the workpiece within a vessel, forming an epitaxial region from the semiconductor material of the first thin film along a surface of the semiconductor substrate which defines the depression, without moving the first thin film with the gas phase doping performed, forming a second thin film made of a semiconductor material along the wall surface which defines the depression; and by annealing the workpiece within the vessel, further forming an epitaxial region from the semiconductor material of the second thin film moved toward a bottom of the depression. |
| US09653550B2 |
MOSFET structure and manufacturing method thereof
A MOSFET structure and a method for manufacturing the same are disclosed. The method comprises: a. providing a substrate (100); b. forming a silicon germanium channel layer (101), a dummy gate structure (200) and a sacrificial spacer (102); c. removing the silicon germanium channel layer and portions of the substrate which are not covered by the dummy gate structure (200) and located under both sides of the dummy gate structure 200, so as to form vacancies (201); d. selectively epitaxially growing a first semiconductor layer (300) on the semiconductor structure to fill bottom and sidewalls of the vacancies (201); and e. removing the sacrificial spacer (102) and filling a second semiconductor layer (400) in the vacancies which are not filled by the first semiconductor layer (300). In the semiconductor structure of the present disclosure, carrier mobility in the channel can be increased, negative effects induced by the short channel effects can be suppressed, and device performance can be enhanced. |
| US09653548B2 |
Non-planar semiconductor device having group III-V material active region with multi-dielectric gate stack
Non-planar semiconductor devices having group III-V material active regions with multi-dielectric gate stacks are described. For example, a semiconductor device includes a hetero-structure disposed above a substrate. The hetero-structure includes a three dimensional group III-V material body with a channel region. A source and drain material region is disposed above the three-dimensional group III-V material body. A trench is disposed in the source and drain material region separating a source region from a drain region, and exposing at least a portion of the channel region. A gate stack is disposed in the trench and on the exposed portion of the channel region. The gate stack includes first and second dielectric layers and a gate electrode. |
| US09653542B2 |
FinFET having isolation structure and method of forming the same
A transistor includes a substrate having an upper surface, a fin structure protruding from the upper surface of the substrate, a first isolation structure over the upper surface of the substrate, and a second isolation structure. The fin structure extends along a first direction and comprising a lower portion and an upper portion. The first isolation structure surrounds the lower portion of the fin structure. The second isolation structure is at least partially embedded in the upper portion of the fin structure. |
| US09653537B1 |
Controlling threshold voltage in nanosheet transistors
Embodiments are directed to a method of forming a semiconductor device and resulting structures for controlling a threshold voltage on a nanosheet-based transistor. A nanosheet stack is formed over a substrate. The nanosheet stack includes a first nanosheet vertically stacked over a second nanosheet. A tri-layer gate metal stack is formed on each nanosheet. The tri-layer gate metal stack includes an inner nitride layer formed on a surface of each nanosheet, a doped transition metal layer formed on each inner nitride layer, and an outer nitride layer formed on each doped transition metal layer. |
| US09653536B2 |
Method for fabricating a structure
A method for fabricating a structure comprising, in succession, a support substrate, a dielectric layer, an active layer, a separator layer of polycrystalline silicon, comprising the steps of: a) providing a donor substrate, b) forming an embrittlement area in the donor substrate, c) providing the support structure, d) forming the separator layer on the support substrate, e) forming the dielectric layer, f) assembling the donor substrate and the support substrate, g) fracturing the donor substrate along the embrittlement area, h) subjecting the structure to a strengthening annealing of at least 10 minutes, the fabrication method being noteworthy in that step d) is executed in such a way that the polycrystalline silicon of the separator layer exhibits an entirely random grain orientation, and in that the strengthening annealing is executed at a temperature strictly greater than 950° C. and less than 1200° C. |
| US09653535B2 |
DT capacitor with silicide outer electrode and/or compressive stress layer, and related methods
Method of forming a deep trench capacitor are provided. The method may include forming a deep trench in a substrate; forming a metal-insulator-metal (MIM) stack within a portion of the deep trench, the MIM stack forming including forming an outer electrode by co-depositing a refractory metal and silicon into the deep trench; and filling a remaining portion of the deep trench with a semiconductor. |
| US09653529B2 |
Display module
An organic display device includes a pixel driving circuit having a thin film transistor connected to a current supply line and a capacitor. A first insulation layer, with a first electrode thereon, covers a source electrode of the transistor. The first electrode is connected to the transistor through a contact hole in the insulation layer. A second insulation layer including an aperture is formed on the first insulation layer and electrode layers. An organic light emitting layer, with a second electrode thereon is formed in the aperture and connected to the first electrode. The second insulation layer includes an inner wall at the aperture, said inner wall having a surface of a convex plane on an edge of the recessed part of the first electrode. The convex plane is located between the organic light emitting layer and the edge of the first electrode, and the second electrode is formed over plurality of pixels. |
| US09653528B2 |
Display apparatus and electronic apparatus
Disclosed herein is a display apparatus, including: a plurality of subpixels disposed adjacent each other and forming one pixel which forms a unit for formation of a color image; the plurality of subpixels including a first subpixel which emits light of the shortest wavelength and a second subpixel disposed adjacent the first subpixel; the second subpixel having a light blocking member disposed between the second subpixel and the first subpixel and having a width greater than a channel length or a channel width of a transistor which forms the second subpixel. |
| US09653527B2 |
Display apparatus having pixels areas with different thicknesses
A display apparatus comprising: a base comprising; a substrate, a plurality of pixel electrodes formed over the substrate, and a pixel definition layer formed over the plurality of pixel electrodes; and an intermediate layer formed over each of the plurality of pixel electrodes of the base. In one implementation, the base is divided into a plurality of areas which comprises a first area and a second area, wherein the intermediate layer formed over the first area of the base has a first thickness, and the intermediate layer formed over the second area of the base has a second thickness substantially different from the first thickness wherein the intermediate layer comprises a common layer and a functional layer, and wherein the common layer of the intermediate layer formed over the first area of the base has a thickness substantially different from that of the common layer of the intermediate layer formed over the second area of the base. |
| US09653526B2 |
Pixel defining layer and manufacturing method thereof, display panel and display device
The present invention discloses a pixel defining layer and a manufacturing method thereof, a display panel and a display device. The pixel defining layer comprises a first pixel defining layer and a second pixel defining layer stacked on the first pixel defining layer, wherein the first pixel defining layer has a plurality of first openings corresponding to light-emitting regions of respective sub-pixels in one-to-one correspondence, the second pixel defining layer has a plurality of second openings corresponding to the first openings in one-to-one correspondence, a cross section of the first opening is in a regular trapezoidal shape which is narrow at top and wide at bottom, and a cross section of the second opening is in an inverted trapezoidal shape which is wide at top and narrow at bottom. The present invention can effectively avoid the short between the anode and the cathode and the open of the cathode. |
| US09653525B2 |
Light emitting display device
A light emitting display device includes a substrate, a first electrode, a pixel defining layer, a light emitting layer, a second electrode, and a reflective pattern. The substrate includes a plurality of pixels, each including a top emission pixel in a first area and a bottom emission pixel in a second area. The first electrode is in the first area and the second area. The pixel defining layer includes pixel openings to expose the first electrode and reflective pattern openings between adjacent pixels. The light emitting layer is on the first electrode, and the second electrode is on the light emitting layer. The reflective pattern is in the reflective pattern opening and spaced from the second electrode in the first area. |
| US09653523B2 |
Input and output device having touch sensor element as input device and display device
A flexible input and output device in which defects due to a crack is reduced. The input and output device includes a first flexible substrate, a second flexible substrate, a first buffer layer, a first crack inhibiting layer, an input device, and a light-emitting element. A first surface of the first flexible substrate faces a second surface of the second flexible substrate. The first buffer layer, the first crack inhibiting layer, and the input device are provided on the first surface side of the first flexible substrate. The first buffer layer includes a region overlapping with the first crack inhibiting layer. The first buffer layer is between the first crack inhibiting layer and the first surface. The input device includes a transistor and a sensor element. The light-emitting element is provided on the second surface side of the second flexible substrate. |
| US09653521B2 |
Organic light emitting display device with substantially polygonal sub-pixels
An organic light emitting display device includes a plurality of sub-pixels arranged in a substantially hexagonally-shaped structure, each of the sub-pixels including a corresponding one of a plurality of organic light emitting devices, wherein the plurality of sub-pixels includes a plurality of first sub-pixels for emitting light of a first color, a plurality of second sub-pixels for emitting light of a second color, and a plurality of third sub-pixels for emitting light of a third color, and wherein centers of adjacent ones of the first, second, and third sub-pixels form a triangle having one of three sides that is shorter than the other two of the sides. |
| US09653514B2 |
Solid-state imaging device and method for driving the same
A solid-state imaging device includes: multiple pixels. Each pixel is arranged at a surface layer portion of a semiconductor substrate, and includes: a photoelectric conversion portion that converts light incident into an electric charge; a charge holding portion that stores the electric charge, and is arranged in the semiconductor substrate; a multiplication gate electrode that is capacitively coupled with the charge holding portion, and is arranged on the semiconductor substrate via an insulation film; and a charge barrier portion that is arranged between the charge holding portion and the insulation film, and has a higher impurity concentration than the semiconductor substrate. |
| US09653512B2 |
Solid-state image pickup device and electronic apparatus using the same
An embodiment of the invention provides a solid-state image pickup device, including a pixel portion in which a plurality of light receiving areas corresponding to different wavelengths, respectively, are disposed, and transistors used commonly to the plurality of adjacent light receiving areas in the pixel portion, and disposed so as to be brought near to a side of the light receiving area, corresponding to the shorter wavelength, of the plurality of adjacent light receiving areas. |
| US09653510B2 |
Solid-state imaging device
A solid-state imaging device includes: pixels arranged in a matrix; a vertical signal line provided for each column, conveying a pixel signal; a power line provided for each column, proving a power supply voltage; and a feedback signal line provided for each column, conveying a signal from a peripheral circuit to a pixel, in which each of the pixels includes: an N-type diffusion layer; a photoelectric conversion element above the N-type diffusion layer; and a charge accumulation node between the N-type diffusion layer and the photoelectric conversion element, accumulating signal charge generated in the photoelectric conversion element, the feedback signal line, a metal line which is a part of the charge accumulation node, the vertical signal line, and the power line are disposed in a second interconnect layer, and the vertical signal line and the power line are disposed between the feedback signal line and the metal line. |
| US09653507B2 |
Deep trench isolation shrinkage method for enhanced device performance
Some embodiments of the present disclosure relate to a deep trench isolation (DTI) structure configured to enhance efficiency and performance of a photovoltaic device. The photovoltaic device comprises a functional layer disposed over an upper surface of a semiconductor substrate, and a pair of pixels formed within the semiconductor substrate, which are separated by the DTI structure. The DTI structure is arranged within a deep trench. Sidewalls of the deep trench are partially covered with a protective sleeve formed along the functional layer prior to etching the deep trench. The protective sleeve prevents etching of the functional layer while etching the deep trench, which prevents contaminants from penetrating the pair of pixels. The protective sleeve also narrows the width of the DTI structure, which increases pixel area and subsequently the efficiency and performance of the photovoltaic device. |
| US09653504B1 |
Chip-scale packaged image sensor packages with black masking and associated packaging methods
A chip-scale image sensor packaging method with black masking includes (a) cutting a composite wafer having a plurality of image sensors bonded to a common glass substrate to form slots in the common glass substrate, wherein the slots define a cover glass for each of the image sensors, respectively, (b) forming black mask in the slots such that the black mask, for each of the image sensors, spans perimeter of the cover glass as viewed cross-sectionally along optical axis of the image sensors, and (c) dicing through the black mask in the slots to singulate a plurality of chip-scale packaged image sensors each including one of the image sensors and the cover glass bonded thereto, with sides of the cover glass facing away from the optical axis being at least partly covered by the black mask. |
| US09653503B2 |
Image sensor and image processing system including the same
An image sensor capable of boosting a voltage of a floating diffusion node is provided. The image sensor includes a floating diffusion node and a storage element which are in a semiconductor substrate. The image sensor includes a first light-shielding material formed over the floating diffusion node, and a second light-shielding material formed over the storage diode. The second light-shielding material is separated from the first light-shielding material. The image sensor also includes a first voltage supply line configured to apply a first voltage to the first light-shielding material and a second voltage supply line configured to apply a second voltage lower than the first voltage to the second light-shielding material. |
| US09653499B2 |
Solid-state imaging device, method of manufacturing solid-state imaging device, and electronic apparatus
A solid-state imaging device including an imaging area where a plurality of unit pixels are disposed to capture a color image, wherein each of the unit pixels includes: a plurality of photoelectric conversion portions; a plurality of transfer gates, each of which is disposed in each of the photoelectric conversion portions to transfer signal charges from the photoelectric conversion portion; and a floating diffusion to which the signal charges are transferred from the plurality of the photoelectric conversion portions by the plurality of the transfer gates, wherein the plurality of the photoelectric conversion portions receive light of the same color to generate the signal charges, and wherein the signal charges transferred from the plurality of the photoelectric conversion portions to the floating diffusion are added to be output as an electrical signal. |
| US09653493B2 |
Bottom-gate and top-gate VTFTs on common structure
An electronic device includes a vertical-support-element with first and second edges having first and second reentrant profiles, respectively. The first reentrant profile includes first conformal semiconductor and dielectric layers, and a conformal conductive top-gate. A first electrode contacts a first portion of the first conformal semiconductor layer over the top of the vertical-support-element. A second electrode, adjacent to the first edge, contacts a second portion of the first conformal semiconductor layer not over the vertical-support-element. The second reentrant profile includes a conformal conductive bottom-gate, and second conformal dielectric and semiconductor layers. A third electrode, adjacent to the second edge, contacts the second semiconductor layer not over the vertical-support-element. A fourth electrode, over the vertical-support-element, contacts the second semiconductor layer. The first and second electrodes define a first semiconductor channel of a top-gate transistor, the third and fourth electrodes define a second semiconductor channel of a bottom-gate transistor. |
| US09653492B2 |
Array substrate, manufacturing method of array substrate and display device
Embodiments of the disclosure provide an array substrate, a manufacturing method of the array substrate and a display device. The array substrate includes a thin film transistor region and a display region. The thin film transistor region includes a thin film transistor and a black matrix, and the display region includes a common electrode. |
| US09653490B2 |
Semiconductor device and electronic device
To provide a novel shift register. Transistors 101 to 104 are provided. A first terminal of the transistor 101 is connected to a wiring 111 and a second terminal of the transistor 101 is connected to a wiring 112. A first terminal of the transistor 102 is connected to a wiring 113 and a second terminal of the transistor 102 is connected to the wiring 112. A first terminal of the transistor 103 is connected to the wiring 113 and a gate of the transistor 103 is connected to the wiring 111 or a wiring 119. A first terminal of the transistor 104 is connected to a second terminal of the transistor 103, a second terminal of the transistor 104 is connected to a gate of the transistor 101, and a gate of the transistor 104 is connected to a gate of the transistor 102. |
| US09653489B2 |
Light emitting device and electronic apparatus
There is provided a light emitting device including: a semiconductor substrate; a plurality of pixel circuits that is disposed in a display region of the semiconductor substrate; a first wiring that is formed of a conductive material so as to be supplied with a predetermined electric potential; and a plurality of first contact portions that is formed of a conductive material so as to connect the semiconductor substrate and the first wiring. The plurality of first contact portions and the first wiring are provided in the display region. |
| US09653488B2 |
Semiconductor device and manufacturing method thereof
A manufacturing method of a semiconductor device comprises the steps of: providing a transparent substrate; forming a gate electrode on the transparent substrate; forming a gate insulation layer covering the gate electrode; forming an oxide semiconductor layer on the gate insulation layer and at least partially over the gate electrode; forming an etching stop layer over the gate electrode and at least covering a part of the oxide semiconductor layer, wherein the etching stop layer includes an opening; forming an electrode layer at the opening and on a part of the etching stop layer; and applying a low-resistance treatment to a part of the oxide semiconductor layer uncovered by the etching stop layer and the electrode layer to form a pixel electrode. |
| US09653486B2 |
Analog/digital circuit including back gate transistor structure
To provide a semiconductor device with low power consumption. In transistors electrically connected to function as a comparator circuit, back gates are provided in the transistors functioning as current sources, and the transistors functioning as the current sources can be switched between conduction and non-conduction in accordance with a control signal supplied to the back gates. The control signal makes the transistor conductive in a period during which the comparator circuit operates and non-conductive in the other period. A semiconductor layer to be a channel formation region of the transistor included in the semiconductor device includes an oxide semiconductor. |
| US09653484B2 |
Array substrate and manufacturing method thereof, display device, thin-film transistor (TFT) and manufacturing method thereof
An array substrate and a manufacturing method thereof, a display device, a thin-film transistor (TFT) and a manufacturing method thereof. The array substrate comprises a base substrate and a pixel electrode and a TFT formed on the base substrate. The TFT includes an active layer and a source/drain pattern. The source/drain pattern is connected with the active layer. The pixel electrode is connected with the active layer. The array substrate can improve the aperture ratio of pixels and the chargeability of the TFT. |
| US09653481B2 |
Flexible display having damage impeding layer and method for manufacturing the same
A flexible display includes a flexible base substrate, a thin film transistors layer formed on the flexible base substrate, and a light emitting elements layer formed on the thin film transistors layer, where the flexible base substrate includes a first support layer formed below the thin film transistors layer, a second support layer disposed below the first support layer, and a heat-energy blocking/reflecting layer provided between the first support layer and the second support layer. The heat-energy blocking/reflecting layer is configured to block or reflect a sufficient portion of radiated heat-energy that is generated when the flexible base substrate is separated from a supporting carrier substrate so as to prevent the damage from the radiated heat-energy to the light emitting elements layer. |
| US09653478B2 |
Semiconductor device, method for manufacturing same, and nonvolatile semiconductor memory device
Provided is a semiconductor element having, while maintaining the same integratability as a conventional MOSFET, excellent switch characteristics compared with the MOSFET, that is, having the S-value less than 60 mV/order at room temperature. Combining the MOSFET and a tunnel bipolar transistor having a tunnel junction configures a semiconductor element that shows an abrupt change in the drain current with respect to a change in the gate voltage (an S-value of less than 60 mV/order) even at a low voltage. |
| US09653477B2 |
Single-chip field effect transistor (FET) switch with silicon germanium (SiGe) power amplifier and methods of forming
Various embodiments include field effect transistors (FETs) and methods of forming such FETs. One method includes: forming a first set of openings in a precursor structure having: a silicon substrate having a crystal direction, the silicon substrate substantially abutted by a first oxide; a silicon germanium (SiGe) layer overlying the silicon substrate; a silicon layer overlying the SiGe layer; a second oxide overlying the silicon layer; and a sacrificial layer overlying the second oxide, wherein the first set of openings each expose the silicon substrate; undercut etching the silicon substrate in a direction perpendicular to the crystal direction of the silicon substrate to form a trench corresponding with each of the first set of openings; passivating exposed surfaces of at least one of the SiGe layer or the silicon layer in the first set of openings; and at least partially filling each trench with a dielectric. |
| US09653475B1 |
Semiconductor device and method of manufacturing the same
According to one embodiment, a method of manufacturing a semiconductor device includes: forming a first film including a conductive material above a semiconductor substrate; forming a second film on the first film; forming a third film including a conductive material on the second film; exposing a part of the second film; and wet etching the second film. In the wet etching, a first and second insulation films are deposited on side surfaces of the first and third films, and part of a space between the first and third films is blocked by the first and second insulation films to form an air gap between the first and third films. |
| US09653474B2 |
Electronic device and method for fabricating the same
A method for fabricating an electronic device including a semiconductor memory may include: forming a stack structure in which an interlayer dielectric layer and a material layer are alternately stacked on a substrate; forming a plurality of holes arranged to have a substantially constant interval while exposing the substrate by passing through the stack structure; forming a channel layer in a first hole of the plurality of holes; forming a dummy layer in a second hole of the plurality of holes; forming a mask pattern on a resultant structure including the dummy layer and the channel layer to expose an area extending in a first direction while overlapping the dummy layer arranged in the first direction; and forming a slit by etching the stack structure using the mask pattern as an etching barrier and removing the dummy layer. |
| US09653469B2 |
Memory array and non-volatile memory device of the same
A non-volatile memory device is provided. The non-volatile memory device includes a substrate area, two storage units, a spacer structure and two control units. The storage units include two anti-fuse gates each having a gate dielectric layer between the anti-fuse gate and the substrate area and two diffusion areas. The spacer structure is formed on the substrate area and between the two anti-fuse gates and contacts thereto. Each of the diffusion areas is a first doping area doped with a first type dopant contacting one of the two anti-fuse gates. Each of the control units includes a select gate formed on the substrate area and a second doping area. A first side of the select gate contacts one of the diffusion areas of the storage unit. The second doping area is doped with the first type dopant and contacts a second side of the select gate. |
| US09653468B2 |
Memory cells having a folded digit line architecture
Memory arrays having folded architectures and methods of making the same. Specifically, memory arrays having a portion of the transistors in a row that are reciprocated and shifted with respect to other transistors in the same row. Trenches formed between the rows may form a weave pattern throughout the array, in a direction of the row. Trenches formed between legs of the transistors may also form a weave pattern throughout the array in a direction of the row. |
| US09653465B1 |
Vertical transistors having different gate lengths
A method of forming a semiconductor device and resulting structures having vertical transistors with different gate lengths are provided. A sacrificial gate is formed over a channel region of a semiconductor fin. The sacrificial gate includes a first material. The first material in a first portion of the sacrificial gate adjacent to the semiconductor fin is converted to a second material, the first portion having a first depth. The first portion of the sacrificial gate is then removed. |
| US09653464B1 |
Asymmetric band gap junctions in narrow band gap MOSFET
A method for forming a semiconductor device, including forming one or more fin structures on a semiconductor substrate, where the fin structure defines source and drain regions. The method includes forming a gate stack, depositing a first contact insulator layer, and applying an etching process to portions of the first insulator layer to form a trench that extends to the source region. The method also includes depositing an epitaxial lower band gap source material into the trench and extending to the source region, depositing a second insulator layer, applying a second etching process to portions of the second insulator layer to form a trench that extends to the source and drain regions, and depositing a metalizing material over the substrate. |
| US09653463B1 |
Semiconductor device with different fin pitches
A method for forming a semiconductor device includes forming a first fin and a second fin on a substrate, the first fin arranged in parallel with the second fin, the first fin arranged a first distance from the second fin, the first fin and the second fin extending from a first source/drain region through a channel region and into a second source/drain region on the substrate. The method further includes forming a third fin on the substrate, the third fin arranged in parallel with the first fin and between the first fin and the second fin, the third fin arranged a second distance from the first fin, the second distance is less than the first distance, the third fin having two distal ends arranged in the first source/drain region. A gate stack is formed over the first fin and the second fin. |
| US09653462B2 |
Semiconductor device and method for fabricating the same
A semiconductor device includes a fin type active pattern extended in a first direction and disposed on a substrate. A first gate electrode and a second gate electrode are disposed on the fin type active pattern. The first gate electrode and the second gate electrode are extended in a second direction crossing the first direction. A trench region is disposed in the fin type active pattern and between the first gate electrode and the second gate electrode. A source/drain region is disposed on a surface of the trench region. A source/drain contact is disposed on the source/drain region. The source/drain contact includes a first insulating layer disposed on the source/drain region and a metal oxide layer disposed on the first insulating layer. |
| US09653460B1 |
Semiconductor device and method of fabricating the same
A semiconductor device and a method of fabricating the same, the semiconductor device includes a substrate, a first gate and a second gate. The first gate is disposed on the substrate and includes a first gate insulating layer, a polysilicon layer, a silicide layer and a protective layer stacked with each other on the substrate and a first spacer surrounds the first gate insulating layer, the polysilicon layer, the silicide layer and the protective layer. The second gate is disposed on the substrate and includes a second gate insulating layer, a work function metal layer and a conductive layer stacked with each other on the substrate, and a second spacer surrounds the second gate insulating layer, the work function metal layer and the conductive layer. |
| US09653457B2 |
Stacked device and associated layout structure
Stacked devices and circuits formed by stacked devices are described. In accordance with some embodiments, a semiconductor post extends vertically from a substrate. A first source/drain region is in the semiconductor post. A first gate electrode layer laterally surrounds the semiconductor post and is vertically above the first source/drain region. A first gate dielectric layer is interposed between the first gate electrode layer and the semiconductor post. A second source/drain region is in the semiconductor post and is vertically above the first gate electrode layer. The second source/drain region is connected to a power supply node. A second gate electrode layer laterally surrounds the semiconductor post and is vertically above the second source/drain region. A second gate dielectric layer is interposed between the second gate electrode layer and the semiconductor post. A third source/drain region is in the semiconductor post and is vertically above the second gate electrode layer. |
| US09653447B2 |
Local interconnect layer enhanced ESD in a bipolar-CMOS-DMOS
Disclosed is a PNP ESD integrated circuit, including a substrate, an active region formed within the substrate, the active region including at least one base region of a second conductivity type, a plurality of collector regions of a first conductivity type formed within the active region, a plurality of emitter regions of the first conductivity type formed within the active region, and a local interconnect layer (LIL) contacting the plurality of emitter regions and the plurality of collector regions, the LIL including cooling fin contacts formed on the collector regions to enhance the current handling capacity of the collector regions. |
| US09653445B2 |
Semiconductor device and method of fabricating 3D package with short cycle time and high yield
A method of making a semiconductor device comprises the steps of providing a first manufacturing line, providing a second manufacturing line, and forming a first redistribution interconnect structure using the first manufacturing line while simultaneously forming a second redistribution interconnect structure using the second manufacturing line. The method further includes the steps of testing a first unit of the first redistribution interconnect structure to determine a first known good unit (KGU), disposing a known good semiconductor die (KGD) over the first KGU of the first redistribution interconnect structure, testing a unit of the second redistribution interconnect structure to determine a second known good unit (KGU, and disposing the second KGU of the second redistribution interconnect structure over the first KGU of the first redistribution interconnect structure and the KGD. A resolution of the second manufacturing line is greater than a resolution of the first manufacturing line. |
| US09653439B2 |
Three dimensional structures within mold compound
A method including forming at least one passive structure on a substrate by a build-up process; introducing one or more integrated circuit chips on the substrate; and introducing a molding compound on the at least one passive structure and the one or more integrated circuit chips. A method including forming at least one passive structure on a substrate by a three-dimensional printing process; introducing one or more integrated circuit chips on the substrate; and embedding the at least one passive structure and the one or more integrated circuit chips in a molding compound. An apparatus including a package substrate including at least one three-dimensional printed passive structure and one or more integrated circuit chips embedded in a molding material. |
| US09653437B2 |
Packaging a substrate with an LED into an interconnect structure only through top side landing pads on the substrate
Standardized photon building blocks are packaged in molded interconnect structures to form a variety of LED array products. No electrical conductors pass between the top and bottom surfaces of the substrate upon which LED dies are mounted. Microdots of highly reflective material are jetted onto the top surface. Landing pads on the top surface of the substrate are attached to contact pads disposed on the underside of a lip of the interconnect structure. In a solder reflow process, the photon building blocks self-align within the interconnect structure. Conductors in the interconnect structure are electrically coupled to the LED dies in the photon building blocks through the contact pads and landing pads. Compression molding is used to form lenses over the LED dies and leaves a flash layer of silicone covering the landing pads. The flash layer laterally above the landing pads is removed by blasting particles at the flash layer. |
| US09653436B2 |
LED module with LED chips
Various embodiments may relate to an LED module, including a number of first inherently unpackaged LED chips, which are in each case designed to emit light of a first color at a respective light emission area, and a number of second inherently unpackaged LED chips, which are in each case designed to emit light of a second color, different than the first color, at a respective light emission area. The LED chips are provided jointly in a housing, and the respective light emission area of a second LED chip is at least 25% smaller than the respective light emission area of a first LED chip. The sum of the light emission areas of the first LED chips is at least 50% greater than the sum of the light emission areas of the second LED chips. |
| US09653435B2 |
Light emitting diode (LED) package having short circuit (VLED) die, lens support dam and same side electrodes and method of fabrication
A light emitting diode (LED) package includes a main vertical LED (VLED) die; a short circuit VLED die; a lens support dam; a transparent lens attached to the lens support dam; a first electrode in electrical communication with a first semiconductor layer of the main VLED die and a second electrode in electrical communication with a second semiconductor layer of the main VLED die. |
| US09653434B2 |
LED module
The invention relates to a light-emitting diode arrangement having the following: a preferably heat-conductive substrate (2); a printed circuit board (5) which is arranged on the substrate (2), a recess (9) being provided in the printed circuit board (5); and at least one light-emitting diode chip (3) which is arranged on the substrate (2) and in the recess (9), said recess (9) being at least partly filled with at least one matrix material which preferably has a color-converting material (8). |
| US09653432B2 |
Metal to metal bonding for stacked (3D) integrated circuits
The present invention provides a stabilized fine textured metal microstructure that constitutes a durable activated surface usable for bonding a 3D stacked chip. A fine-grain layer that resists self anneal enables metal to metal bonding at moderate time and temperature and wider process flexibility. |
| US09653421B2 |
Semiconductor device
A semiconductor device is provided with: a semiconductor chip die-bonding mounted face up on a support; an intermediate substrate connecting the semiconductor chip to a plurality of external connection portions; and a plurality of connection bumps connecting the semiconductor chip and the intermediate substrate. The plurality of connection bumps includes a plurality of power supply bumps connected to a plurality of electrode pads on the semiconductor chip for supplying power to the semiconductor chip. The intermediate substrate includes: a plurality of power supply pads connected to the plurality of electrode pads through the plurality of power supply bumps; a bump surface facing the semiconductor chip and having a plurality of power supply pads formed thereon; an external connection surface having a plurality of external connection pads formed thereon connected to the external connection portions; and a capacitor connected to the plurality of power supply bumps. |
| US09653420B2 |
Microelectronic devices and methods for filling vias in microelectronic devices
Microelectronic devices and methods for filling vias and forming conductive interconnects in microfeature workpieces and dies are disclosed herein. In one embodiment, a method includes providing a microfeature workpiece having a plurality of dies and at least one passage extending through the microfeature workpiece from a first side of the microfeature workpiece to an opposite second side of the microfeature workpiece. The method can further include forming a conductive plug in the passage adjacent to the first side of the microelectronic workpiece, and depositing conductive material in the passage to at least generally fill the passage from the conductive plug to the second side of the microelectronic workpiece. |
| US09653417B2 |
Method for singulating packaged integrated circuits and resulting structures
A method of packaging an integrated circuit includes forming a first integrated circuit and a second integrated circuit on a wafer, the first and second integrated circuit separated by a singulation region. The method includes covering the first and second integrated circuits with a molding compound, and sawing through the molding compound and a top portion of the wafer using a beveled saw blade, while leaving a bottom portion of the wafer remaining. The method further includes sawing through the bottom portion of the wafer using a second saw blade, the second saw blade having a thickness that is less than a thickness of the beveled saw blade. The resulting structure is within the scope of the present disclosure. |
| US09653416B2 |
Semiconductor substrate and manufacturing method thereof
A method of manufacturing a semiconductor substrate includes a device-forming process of forming a plurality of device areas in a substrate section, a first wiring process of forming circuit wirings connected to the plurality of device areas, an electrode pad-forming process of forming a plurality of electrode pads, a second wiring process of forming a potential adjustment wiring electrically connecting at least a part of the electrode pads, an electrode-forming process of forming electrode bodies on the electrode pads by electroless plating after the second wiring process, and a potential adjustment-releasing process of releasing a connection by the potential adjustment wiring after the electrode-forming process. |
| US09653415B2 |
Semiconductor device packages and method of making the same
The present disclosure relates to a semiconductor device package. The semiconductor device package includes a substrate, a semiconductor device, a plurality of electronic components, a first package body, a patterned conductive layer and a feeding element. The semiconductor device and the plurality of electronic components are disposed on the substrate. The first package body covers the semiconductor device but exposes the plurality of electronic components. The patterned conductive layer is formed on the first package body. The feeding element electrically connects the patterned conductive layer to the plurality of electronic components. |
| US09653408B2 |
High-frequency package
A high-frequency package comprises a die; a plurality of leads; and a die pad; wherein a surface of the die pad is lower than top surfaces of the plurality of leads, the die is disposed on the die pad with the lower surface, such that a top surface of the die is substantially aligned with the top surfaces of the plurality of leads. |
| US09653407B2 |
Semiconductor device packages
The present disclosure relates to a semiconductor device package and a method for manufacturing the semiconductor device package. The semiconductor device package includes a substrate, a grounding element, a component, a package body and a conductive layer. The grounding element is disposed in the substrate and includes a connection surface exposed at a second portion of a lateral surface of the substrate. The component is disposed on a top surface of the substrate. The package body covers the component and the top surface of the substrate. A lateral surface of the package body is aligned with the lateral surface of the substrate. The conductive layer covers a top surface and the lateral surface of the package body, and further covers the second portion of the lateral surface of the substrate. A first portion of the lateral surface of the substrate is exposed from the conductive layer. |
| US09653404B1 |
Overlay target for optically measuring overlay alignment of layers formed on semiconductor wafer
The present invention provides an overlay target. The overlay target includes a plurality of first pattern blocks and a plurality of second pattern blocks. The first pattern blocks and the second patterns blocks are arranged in array by being separated by at least one first gaps stretching along a first direction and at least one second gaps stretching along a second direction. Each first pattern block is composed of a plurality of first stripe patterns stretching along a third direction, and each second pattern block is composed of a plurality of second stripe patterns stretching along a fourth direction. The first direction is orthogonal to the second direction, the third direction and the fourth direction are 45 degrees relative to the first direction. |
| US09653401B2 |
Method for forming buried conductive line and structure of buried conductive line
A method for forming a buried conductive line is described. A substrate having a trench therein and a contact area thereon is provided, wherein the trench has an end portion in the contact area and a conductive layer is filled in the trench. A mask layer is formed covering the conductive layer in the contact area. The conductive layer is etched back using the mask layer as a mask. |
| US09653398B1 |
Non-oxide based dielectrics for superconductor devices
A method of forming a superconductor device is provided. The method includes depositing a non-oxide based dielectric layer over a substrate, depositing a photoresist material layer over the non-oxide based dielectric layer, irradiating and developing the photoresist material layer to form a via pattern in the photoresist material layer, and etching the non-oxide based dielectric layer to form openings in the non-oxide based dielectric layer based on the via pattern. The method further comprises stripping the photoresist material layer, and filling the openings in the non-oxide based dielectric with a superconducting material to form a set of superconducting contacts. |
| US09653395B2 |
Hybrid subtractive etch/metal fill process for fabricating interconnects
In one example, a method for fabricating an integrated circuit includes patterning a layer of a first conductive metal, via a subtractive etch process, to form a plurality of lines for connecting semiconductor devices on the integrated circuit. A large feature area is formed outside of the plurality of conductive lines via a metal fill process using a second conductive metal. |
| US09653393B2 |
Method and layout of an integrated circuit
An integrated circuit layout includes a first metal line, a second metal line, at least one first conductive via and a first conductive segment. The first metal line is formed along a first direction. The at least one first conductive via is disposed over the first metal line. The second metal line is disposed over at least one first conductive via and is in parallel with the first metal line. The first conductive segment is formed on one end of the second metal line. |
| US09653386B2 |
Compact multi-die power semiconductor package
One disclosed implementation is a power semiconductor package including a sync transistor having a drain on its top surface and a source and a gate on its bottom surface. The source of the sync transistor is configured for attachment to a first partially etched leadframe segment and the gate of the sync transistor is configured for attachment to a second partially etched leadframe segment. A control transistor has a source and a gate on its top surface and a drain on its bottom surface. The drain of the control transistor is configured for attachment to a third partially etched leadframe segment. A first conductive clip extends to the substrate and is situated over the drain of the sync transistor and the source of the control transistor, the first conductive clip coupling the drain of the sync transistor and the source of the control transistor to the substrate without using a leadframe. |
| US09653382B2 |
Semiconductor laser structure
A semiconductor laser structure is provided. The semiconductor laser comprises a central thermal shunt, a ring shaped silicon waveguide, a contiguous thermal shunt, an adhesive layer and a laser element. The central thermal shunt is located on a SOI substrate which has a buried oxide layer surrounding the central thermal shunt. The ring shaped silicon waveguide is located on the buried oxide layer and surrounds the central thermal shunt. The ring shaped silicon waveguide includes a P-N junction of a p-type material portion, an n-type material portion and a depletion region there between. The contiguous thermal shunt covers a portion of the buried oxide layer and surrounds the ring shaped silicon waveguide. The adhesive layer covers the ring shaped silicon waveguide and the buried oxide layer. The laser element covers the central thermal shunt, the adhesive layer and the contiguous thermal shunt. |
| US09653370B2 |
Systems and methods for embedding devices in printed circuit board structures
Embodiments relate to active devices embedded within printed circuit boards (PCBs). In embodiments, the active devices can comprise at least one die, such as a semiconductor die, and coupling elements for mechanically and electrically coupling the active device with one or more layers of the PCB in which the device is embedded. Embodiments thereby provide easy embedding of active devices in PCBs and inexpensive integration with existing PCB technologies and processes. |
| US09653361B2 |
Semiconductor device having gate-all-around transistor and method of manufacturing the same
A semiconductor device includes a fin structure disposed on a substrate, a sacrificial layer pattern disposed on the fin structure, an active layer pattern disposed on the sacrificial layer pattern, and a gate dielectric layer and a gate electrode layer extending through the sacrificial layer pattern and surrounding a portion of the active layer pattern. |
| US09653359B2 |
Bulk fin STI formation
Techniques for STI in fin device structures formed on bulk substrates are provided. In one aspect, a method of forming a fin device in a bulk substrate includes the steps of: forming fins and trenches in between the fins in the bulk substrate; and annealing the bulk substrate in an oxygen ambient under conditions sufficient to form a thermal oxide on sidewalls of the fins and which completely fills the trenches, wherein the thermal oxide forms a STI region between each of the fins. A method of forming a fin device in a bulk substrate is also provided where a deposited STI oxide is used in combination with a thermal oxide. A fin device is also provided. |
| US09653358B2 |
Semiconductor device structure and method for manufacturing the same
The present invention presents a method for manufacturing a semiconductor device structure as well as the semiconductor device structure. Said method comprises: providing a semiconductor substrate; forming a first insulating layer on the semiconductor substrate; forming a shallow trench isolation embedded in the first insulating layer and the semiconductor substrate; forming a channel region embedded in the semiconductor substrate; and forming a gate stack stripe on the channel region. Said method further comprises, before forming the channel region, performing a source/drain implantation on the semiconductor substrate. By means of forming the source/drain regions in a self-aligned manner before forming the channel region and the gate stack, said method achieves the advantageous effects of the replacement gate process without using a dummy gate, thereby simplifying the process and reducing the cost. |
| US09653357B2 |
Plasma etching apparatus
A plasma etching apparatus includes: a housing defining a plasma processing chamber; a workpiece retaining unit disposed within the plasma processing chamber of the housing and retaining a workpiece on an upper surface of the workpiece retaining unit; a processing gas injecting unit injecting a processing gas for plasma generation onto the workpiece retained by the workpiece retaining unit, the processing gas injecting unit including a processing gas jetting portion; a processing gas supply unit supplying the processing gas to the processing gas injecting unit; and a pressure reducing unit reducing a pressure within the plasma processing chamber. The processing gas jetting portion of the processing gas injecting unit includes a central injecting portion and a peripheral injecting portion surrounding the central injecting portion. |
| US09653345B1 |
Method of fabricating semiconductor structure with improved critical dimension control
A method of fabricating a semiconductor structure for improving critical dimension control is provided in the present invention. The method includes the following steps. An inter metal dielectric (IMD) layer is formed on a semiconductor substrate, a patterned hard mask layer is formed on the IMD layer, and a first aperture is formed in the IMD layer. A first barrier layer is formed on the patterned hard mask layer and a surface of the first aperture, a first patterned resist is formed on the first barrier layer, and an etching process is performed to form a second aperture in the IMD layer by using the first patterned resist as a mask. The first patterned resist is kept from being poisoned because of the first barrier layer, and the critical dimension control of the semiconductor structure may be improved accordingly. |
| US09653343B1 |
Method of manufacturing semiconductor device with shallow trench isolation (STI) having edge profile
A method for fabricating semiconductor device is disclosed. First, a substrate having a first region and a second region is provided, a shallow trench isolation (STI) is formed in the substrate to separate the first region and the second region, and a patterned hard mask is formed on the first region and part of the STI, in which the patterned hard mask exposes includes an opening to expose part of the STI. Next, a gas is driven-in through the exposed STI to alter an edge of the substrate on the first region. |
| US09653340B2 |
Heated wafer carrier profiling
An apparatus includes a carrier rotatable about an axis of rotation where the carrier has a top surface adapted to hold at least one semiconductor wafer and a surface characterization tool which is operative to move over a plurality of positions relative to the top surface of the carrier and/or the wafer transverse to the axis of rotation. The surface characterization tool is operative to move over a plurality of positions relative to the top surface of the carrier and/or the wafer transverse to the axis of rotation and is further adapted to produce characterization signals over the plurality of positions on at least a portion of the carrier and/or on at least a portion of said major surface of the wafer as the carrier rotates. |
| US09653339B2 |
Integrated shielding for wafer plating
A semiconductor substrate carrier for use during wet chemical processing may comprise a conductive flange to couple the carrier with processing equipment, a frame coupled with the conductive flange, where the frame is configured to hold a semiconductor substrate, and an integrated shield coupled with the frame. The integrated shield is configured to alter an electric field near at least a portion of a surface of the semiconductor substrate during the wet chemical processing. |
| US09653335B2 |
Wafer processing laminate, wafer processing member, temporary bonding arrangement, and thin wafer manufacturing method
A laminate comprising a support, a temporary adhesive layer, and a wafer having a circuit-forming front surface and a back surface to be processed allows for processing the wafer. The temporary adhesive layer consists of a first temporary bond layer (A) of thermoplastic organosiloxane polymer which is releasably bonded to the front surface of the wafer and a second temporary bond layer (B) of thermosetting modified siloxane polymer which is laid contiguous to the first temporary bond layer and releasably bonded to the support. |
| US09653328B2 |
Method and apparatus for surface treatment using inorganic acid and ozone
An apparatus for treating a surface of an article includes a chamber for receiving an article to be treated. A dispenser dispenses a treatment liquid including inorganic acid onto the article. A tank stores the treatment liquid. An ozone generator communicates with a supply line entering or exiting the tank to mix ozone with the treatment liquid. A cooler cools the treatment liquid to a subambient temperature in a range of 3° C. to less than 20° C. A heater heats a surface of an article to be treated to a temperature at least 30° C. greater than a temperature of the treatment liquid when applied to the article. |
| US09653327B2 |
Methods of removing a material layer from a substrate using water vapor treatment
Embodiments of the invention generally relate to methods of removing and/or cleaning a substrate surface having different material layers disposed thereon using water vapor plasma treatment. In one embodiment, a method for cleaning a surface of a substrate includes positioning a substrate into a processing chamber, the substrate having a dielectric layer disposed thereon forming openings on the substrate, exposing the dielectric layer disposed on the substrate to water vapor supplied into the chamber to form a plasma in the water vapor, maintaining a process pressure in the chamber at between about 1 Torr and about 120 Torr, and cleaning the contact structure formed on the substrate. |
| US09653325B2 |
Underfill process and processing machine thereof
A processing machine of an underfill process comprises a carrier, an automated device, a scanning mechanism, an identifying device and a host. The carrier is suitable for carrying a package substrate provided with chips bonded thereon. The automated device has a dispenser for filling an underfill between each chip and the package substrate. The scanning mechanism is configured on the carrier, and the identifying device is driven by the scanning mechanism to move along a predetermined path over the package substrate and identify positions of the chips before the dispenser fills the underfill between each chip and the package substrate. The identifying device is suitable for outputting an identifying result of chip position, and a movement of the identifying device is independent from a movement of the dispenser. The host receives the identifying result and locates the dispenser of the automated device according to the identifying result. |
| US09653324B2 |
Integrated circuit package configurations to reduce stiffness
Embodiments of the present disclosure are directed towards an integrated circuit (IC) package including a die having a first side and a second side disposed opposite to the first side. The IC package may further include an encapsulation material encapsulating at least a portion of the die and having a first surface that is adjacent to the first side of the die and a second surface disposed opposite to the first surface. In embodiments, the second surface may be shaped such that one or more cross-section areas of the IC package are thinner than one or more other cross-section areas of the IC package. Other embodiments may be described and/or claimed. |
| US09653323B2 |
Manufacturing method of substrate structure having embedded interconnection layers
A manufacturing method of a substrate structure is provided. The method includes the following steps. Firstly, a conductive carrier is provided. Then, a first metal layer is formed on the conductive carrier. Then, a second metal layer is formed on the first metal layer. Then, a third metal layer is formed on the second metal layer, wherein each of the second metal layer and the third metal layer has a first surface and a second surface opposite to the first surface, the first surface of the third metal layer is connected to the second surface of the second metal layer, the surface area of the first surface of the third metal layer is larger than the surface area of the second surface of the second metal layer, and the first metal layer, the second metal layer and the third metal layer form a conductive structure. |
| US09653322B2 |
Method for fabricating a semiconductor package
Representative implementations of devices and techniques provide a semiconductor package comprising a laminate substrate. The laminate substrate includes at least one conductive layer laminated to a surface of an insulating core. The laminate substrate also includes one or more die openings, in which one or more semiconductor die are located. |
| US09653321B2 |
Plasma processing method
A plasma processing method for processing a silicon containing film formed on a substrate including a step of removing a reaction product with a first plasma formed from a first gas containing halogen, hydrogen, and carbon in a case where the reaction product is formed when performing an etching process on the silicon containing film by using an etching mask having an etching pattern. |
| US09653319B2 |
Method for using post-processing methods for accelerating EUV lithography
Methods for using high-speed EUV resists including resists having additives that may be detrimental to etch chambers. Methods include using reversal materials and/or reversal techniques, as well as diffusion-limited etch-back and slimming for pattern creation and transfer. A substrate with high-speed EUV resist is lithographically patterned and developed into a patterned resist mask. An image reversal material is then over-coated on the patterned resist mask such that the image reversal material fills and covers the patterned resist mask. An upper portion of the image reversal material is removed such that top surfaces of the patterned resist mask are exposed. The patterned resist mask is removed such that the image reversal material remains resulting in a patterned image reversal material mask. Residual resist material is removed via a slimming process using an acid diffusion and subsequent development. |
| US09653317B2 |
Plasma processing method and plasma processing apparatus
A metal-containing deposit can be efficiently removed. A plasma processing method includes removing a deposit, which adheres to a member within a processing vessel and contains at least one of a transition metal and a base metal, by plasma of a processing gas containing a CxFy gas, in which x is an integer equal to or less than 2 and y is an integer equal to or less than 6, and without containing a chlorine-based gas and a nitrogen-based gas. |
| US09653308B2 |
Epitaxial lift-off process with guided etching
A method for performing epitaxial lift-off allowing reuse of a III-V substrate to grow III-V devices is presented. A sample is received comprising a growth substrate with a top surface, a sacrificial layer on the top surface, and a device layer on the sacrificial layer. This substrate is supported inside a container and the container is filled with a wet etchant such that the wet etchant progressively etches away the sacrificial layer and the device layer lifts away from the growth substrate. While filling the container with the wet etchant, the sample is supported in the container such that the top surface of the growth substrate is non-parallel with an uppermost surface of the wet etchant. Performed in this manner, the lift-off process requires little individual setup of the sample, and is capable of batch processing and high throughput. |
| US09653307B1 |
Surface modification compositions, methods of modifying silicon-based materials, and methods of forming high aspect ratio structures
A surface modification composition comprising a silylation agent comprising a silyl acetamide, a silylation catalyst comprising a perfluoro acid anhydride, an amine-based complexing agent, and an organic solvent. Methods of modifying a silicon-based material and methods of forming high aspect ratio structures on a substrate are also disclosed. |
| US09653306B2 |
Method for forming crystalline cobalt silicide film
The present invention is directed to a method for forming a crystalline cobalt silicide film, comprising the steps of: applying to a surface made of silicon a composition obtained by mixing a compound represented by the following formula (1A) or (1B): SinX2n+2 (1A) SimX2m (1B) wherein each X in the formulas (1A) and (1B) is a hydrogen atom or a halogen atom, n is an integer of 1 to 10, and m is an integer of 3 to 10, or a polymer thereof with a zero-valent cobalt complex to form a coating film; heating the coated film at 550 to 900° C. so as to form a two-layer film which is composed of a first layer made of a crystalline cobalt silicide on the surface made of silicon and a second layer containing silicon atoms, oxygen atoms, carbon atoms and cobalt atoms on the first layer; and removing the second layer of the two-layer film. |
| US09653301B2 |
Semiconductor device having electrode made of high work function material, method and apparatus for manufacturing the same
Provided is a semiconductor device including a metal film which can be formed with lower costs but still manage to have a necessary work function and oxidation resistance. The semiconductor device includes an insulating film disposed on a substrate; and a metal film disposed on the insulating film. The metal film includes a stacked structure of: a first metal film disposed on the insulating film to directly contact the insulating film; a second metal film disposed on the first metal film to directly contact the first metal film; and the first metal film disposed on the second metal film to directly contact the second metal film, the second metal film having a work function greater than 4.8 eV and being different from the first metal film in material, wherein an oxidation resistance of the first metal film is greater than that of the second metal film. |
| US09653300B2 |
Structure of metal gate structure and manufacturing method of the same
A manufacturing method of a metal gate structure is provided. First, a substrate covered by an interlayer dielectric is provided. A gate trench is formed in the interlayer dielectric, wherein a gate dielectric layer is formed in the gate trench. A silicon-containing work function layer is formed on the gate dielectric layer in the gate trench. Finally, the gate trench is filled up with a conductive metal layer. |
| US09653298B2 |
Thermal processing by transmission of mid infra-red laser light through semiconductor substrate
Thermal processing is performed by transmission of mid infra-red laser light through a substrate such as a semiconductor substrate with a limited mid infra-red transmission range. The laser light is generated by a rare-earth-doped fiber laser and is directed through the substrate such that the transmitted power is capable of altering a target material at a back side region of the substrate, for example, on or spaced from the substrate. The substrate may be sufficiently transparent to allow the transmitted mid infra-red laser light to alter the target material without altering the material of the substrate. In one example, the rare-earth-doped fiber laser is a high average power thulium fiber laser operating in a continuous wave (CW) mode and in a 2 μm spectral region. |
| US09653294B2 |
Methods of forming fine patterns and methods of manufacturing integrated circuit devices using the methods
The present inventive concept provides a method of forming a fine pattern including forming a plurality of pillar-shaped guides that are regularly arranged on a feature layer. |
| US09653290B2 |
Method for manufacturing nanowire transistor device
A method for manufacturing a nanowire transistor device includes the following steps: A substrate is provided, and the substrate includes a plurality of nanowires suspended thereon. Each of the nanowires includes a first semiconductor core. Next, a first selective epitaxial growth process is performed to form second semiconductor cores respectively surrounding the first semiconductor cores. The second semiconductor cores are spaced apart from the substrate. After forming the second semiconductor core, a gate is formed on the substrate. |
| US09653283B2 |
Method of manufacturing a semiconductor device
A method of manufacturing a semiconductor device is provided. The method includes providing a semiconductor substrate including a transistor and a dummy gate disposed on the transistor, removing the dummy gate on the transistor, performing treatment using hydrogen (H2) on a surface of the semiconductor substrate, so as to remove residue materials left behind from the removal of the dummy gate, and forming a metal gate on the transistor. |
| US09653280B2 |
Electrode for use in a lamp
The invention describes an electrode (1) for use in a lamp (3) comprising a quartz glass envelope (30) enclosing a chamber (31), which electrode (1) comprises a tip for extending into the chamber (31) and base for embedding in a sealed portion (33) of the quartz glass envelope (30), characterized in that the base comprises a plurality of essentially smooth concave channels (2) arranged around the body of the electrode (2) and wherein the depth (dch) of a channel (2) is preferably at most 8 percent, more preferably at most 5 percent, most preferably at most 3 percent of a diameter (De) of the electrode (2). The invention further describes a method of manufacturing an electrode (1) for use in a lamp (3) comprising a chamber (11) in a quartz glass envelope (30), which method comprises the step of removing material from the body of the electrode (1) to form a plurality of channels (2) around the body of the electrode such that a channel (2) comprises channel side walls (62) and an essentially concave channel floor (60), and such that depth (dch) of a channel (2) is preferably at most 8 percent, more preferably at most 5 percent, most preferably at most 3 percent of a diameter (De) of the electrode (2). The invention also describes a lamp (3) comprising such electrodes (1), and a method of manufacturing such a lamp (3). |
| US09653278B2 |
Dynamic multipole Kingdon ion trap
An ion trap is disclosed comprising a plurality of elongate electrodes aligned with one another and with a central longitudinal axis along respective longitudinal axes and that are spaced apart from one another and disposed about a central longitudinal axis to form a quadrupole. The ion trap further comprises an elongate electrode that is aligned with and disposed along the central longitudinal axis, and circuitry coupled to the outer electrodes is suitable for driving the central and outer electrodes to selectively trap of ions within a region defined between the central electrode and the outer. |
| US09653277B2 |
Mass spectrometer
A basic ion optical system having a guaranteed capability for the temporal focusing of ions, including sector-shaped electrodes, an injection slit and an ejection slit, is arranged on the same plane. Four or more sets of the basic ion optical systems are arrayed at predetermined intervals in a direction substantially orthogonal to the aforementioned plane. The injection slit on a topmost basic ion optical system plane and the ejection slit on a basic ion optical system plane located immediate below, as well as the injection slit on a bottommost basic ion optical system plane and the ejection slit on a basic ion optical system plane located immediate above, are respectively connected by another type of basic ion optical system having a guaranteed capability for the temporal focusing of ions. The other injection slits and ejection slits are respectively connected by another type of basic ion optical system having a guaranteed capability for the temporal focusing of ions. Thus, a loop orbit having a three-dimensionally deformed figure “8”-shape is formed, whereby the flight distance is elongated while ensuring the temporal focusing of the ions for the entire system, simultaneously with utilizing the three-dimensional space to compactify the ion optical system. |
| US09653270B2 |
Method for connecting magnetic substance target to backing plate, and magnetic substance target
A method for connecting a magnetic substance target to a backing plate with less variation in plate thickness, characterized in having the steps of connecting the magnetic substance target to an aluminum plate beforehand while maintaining the flatness, connecting the magnetic substance target connected to the aluminum plate to the backing plate while maintaining the flatness, and grinding out the aluminum plate, whereby the flatness of the magnetic substance target can be maintained until the magnetic substance target is connected to the backing plate by a relatively simple operation. |
| US09653269B2 |
Detecting arcing using processing chamber data
A method and apparatus for detecting substrate arcing and breakage within a processing chamber is provided. A controller monitors chamber data, e.g., parameters such as RF signals, voltages, and other electrical parameters, during operation of the processing chamber, and analyzes the chamber data for abnormal spikes and trends. Using such data mining and analysis, the controller can detect broken substrates without relying on glass presence sensors on robots, but rather based on the chamber data. |
| US09653267B2 |
Temperature controlled chamber liner
A liner for a semiconductor processing chamber and a semiconductor processing chamber are provided. In one embodiment, a liner for a semiconductor processing chamber includes a body having an outwardly extending flange. A plurality of protrusions extend from a bottom surface of the flange. The protrusions have a bottom surface defining a contact area that is asymmetrically distributed around the bottom surface of the flange. |
| US09653265B2 |
Methods and systems for plasma deposition and treatment
This application is directed to an apparatus for creating microwave radiation patterns for an object detection system. The apparatus includes a waveguide conduit having first slots at one side of the conduit and corresponding second slots at an opposite side of the conduit. The waveguide conduit is coupled to a microwave source for transmitting microwaves from the microwave source through the plurality of first slots. A plunger is moveably positioned in the waveguide conduit from one end thereof. The plunger allows the waveguide conduit to be tuned to generally optimize the power of the microwaves exiting the first slots. Secondary plungers are each fitted in one of the second slots to independently tune or detune microwave emittance through a corresponding first slot. |
| US09653263B2 |
Multi-beam writing of pattern areas of relaxed critical dimension
To irradiate a target with a beam of energetic electrically charged particles, the beam is formed and imaged onto a target, where it generates a pattern image composed of pixels. For a pattern which comprises a primary pattern region to be written with a predetermined primary feature size and a secondary pattern region which is composed of structure features capable of being written with a secondary feature size, larger than the primary feature size. The structure features of the primary pattern region are written by exposing a plurality of exposure spots on grid positions of a first exposure grid; the structure features in the secondary pattern region are written by exposing a plurality of exposure spots on grid positions of a second exposure grid according to a second arrangement which is coarser that the regular arrangement of the first exposure grid. |
| US09653261B2 |
Charged particle lithography system and beam generator
The invention relates to a charged particle lithography system for exposing a target. The system includes a charged particle beam generator for generating a charged particle beam; an aperture array (6) for forming a plurality of beamlets from the charged particle beam; and a beamlet projector (12) for projecting the beamlets onto a surface of the target. The charged particle beam generator includes a charged particle source (3) for generating a diverging charged particle beam; a collimator system (5a,5b,5c,5d; 72;300) for refracting the diverging charged particle beam; and a cooling arrangement (203) for removing heat from the collimator system, the cooling arrangement comprising a body surrounding at least a portion of the collimator system. |
| US09653259B2 |
Method for determining a beamlet position and method for determining a distance between two beamlets in a multi-beamlet exposure apparatus
The invention relates to a method for determining a beamlet position in a charged particle multi-beamlet exposure apparatus. The apparatus is provided with a sensor comprising a conversion element for converting charged particle energy into light and a light sensitive detector. The conversion element is provided with a sensor surface area provided with a 2D-pattern of beamlet blocking and non-blocking regions. The method comprises taking a plurality of measurements and determining the position of the beamlet with respect to the 2D-pattern on the basis of a 2D-image created by means of the measurements. Each measurement comprises exposing a feature onto a portion of the 2D-pattern with a beamlet, wherein the feature position differs for each measurement, receiving light transmitted through the non-blocking regions, converting the received light into a light intensity value, and assigning the light intensity value to the position at which the measurement was taken. |
| US09653258B2 |
Near-field optical transmission electron emission microscope
The Near-field Optical Transmission Electron Emission Microscope involves the combination, in one instrument, of optical imaging in the near-field regime or close to it (in respect to the transmission electromagnetic radiation when the wavelength exceeds the desired lateral resolution) and the secondary electron imaging of EEM microscope (“Cathode lens objective” based Emission Electron Microscopy). These two microscopic techniques are combined by the application of the photon-electron converter, which converts the optical, transmission image of the object (illuminated by the penetrating electromagnetic radiation) to the correlated photoelectron image, by means of a matrix of one-way closed channels (capillaries). The closed, smooth front face of the converter (comprising channel-bottoms) remains in contact with the object of imaging, whereas its opposite, opened face (consisting of an array (matrix) of channel openings) is exposed to vacuum and emits the secondary electrons. |
| US09653257B2 |
Method and system for reducing charging artifacts in scanning electron microscopy images
A scanning electron microscopy system for mitigating charging artifacts includes a scanning electron microscopy sub-system for acquiring multiple images from a sample. The images include one or more sets of complementary images. The one or more sets of complementary images include a first image acquired along a first scan direction and a second image acquired along a second scan direction opposite to the first scan direction. The system includes a controller communicatively coupled to the scanning electron microscopy sub-system. The controller is configured to receive images of the sample from the scanning electron microscopy sub-system. The controller is further configured to generate a composite image by combining the one or more sets of complementary images. |
| US09653256B2 |
Charged particle-beam device
Provided is a charged-particle-beam device capable of simultaneously cancelling out a plurality of aberrations caused by non-uniform distribution of the opening angle and energy of a charged particle beam. The charged-particle-beam device is provided with an aberration generation lens for generating an aberration due to the charged particle beam passing off-axis, and a corrective lens for causing the trajectory of the charged particle beam to converge on the main surface of an objective lens irrespective of the energy of the charged particle beam. The main surface of the corrective lens is disposed at a crossover position at which a plurality of charged particle beams having differing opening angles converge after passing through the aberration generation lens. |
| US09653253B2 |
Plasma-based material modification using a plasma source with magnetic confinement
A plasma-based material modification system for material modification of a work piece may include a plasma source chamber coupled to a process chamber. A support structure, configured to support the work piece, may be disposed within the process chamber. The plasma source chamber may include a first plurality of magnets, a second plurality of magnets, and a third plurality of magnets that surround a plasma generation region within the plasma source chamber. The plasma source chamber may be configured to generate a plasma having ions within the plasma generation region. The third plurality of magnets may be configured to confine a majority of electrons of the plasma having energy greater than 10 eV within the plasma generation region while allowing ions from the plasma to pass through the third plurality of magnets into the process chamber for material modification of the work piece. |
| US09653246B2 |
Magnetron
To provide a magnetron improved in high efficiency and load stability while suppressing costs. By shortening the height of vane Vh so that the ratio of the height of vane Vh to a gap between end hats EHg (EHg/Vh) satisfies a condition 1.12≦EHg/Vh≦1.26, an input side pole piece-vane gap IPpvg becomes larger than an output side pole piece-vane gap OPpvg, and an input side end hat-vane gap IPevg becomes larger than an output side end hat-vane gap OPevg, load stability at high efficiency can be improved while shortening the height of vane Vh. Therefore, it is possible to provide a magnetron improved in high efficiency and load stability while suppressing costs. |
| US09653245B2 |
Temperature switch and method for adjusting a temperature switch
The invention relates to a temperature switch comprising a housing (2), a switching system (3) consisting of a first support (3.1) with a fixed contact (3.2) and a second support (3.3), on which a switch spring (3.4) with a switch contact (3.5) is arranged and a switching arrangement (4), which effects a positional change of the switch contact (3.5) as a function of the temperature. |
| US09653242B2 |
Actuator of a safety switch and safety switch having such an actuator
The invention relates to an actuator (1) of a safety switch (10) for detecting and locking a specifiable state of an apparatus (2), in particular for detecting and locking the closed state of a safety device of a machine (4) or the like, wherein the actuator (1) has an inductor (36) for a contact-free signal exchange with a reading inductor (38) of a switch element (16) of the safety switch (10), and wherein the actuator (1) has a locking flank (50) on which a lock element (24) of the switch element (16) can be brought into locking contact and the actuator (1) can therefore be locked on the switch element (16), characterized in that the inductor (36) has at least one winding extending around the locking flank (50) or around a recess or hole in the actuator (1) forming the locking flank (50) so that the at least one winding extends around the lock element (24) or around an extension of the lock element (24) in the state in which the actuator (1) is locked to the switch element (16), as well as a safety switch having such an actuator. |
| US09653241B2 |
Magnetic actuating device for a current switching device
A magnetic actuating device (1) for a current switching device (2) comprises: —a ferromagnetic stator (3) and a ferromagnetic armature (4) which is movable between a first end position (5), which is close to the ferromagnetic stator (3), and a second end position (6) which is spaced apart from the ferromagnetic stator (3), —a compression spring (7)configured for urging the ferromagnetic armature (4) to the second end position (6), —an electrical coil (8) energizable for electromagnetically attracting the ferromagnetic armature (4) to the first end position (5), and —a mechanical locking assembly (10) configured for releasably blocking the ferromagnetic armature (4) in the first end position (5). |
| US09653238B2 |
Embedded pole part with an isolating housing
An exemplary embedded pole part with an isolating housing, which accommodates a vacuum interrupter as well as electric terminals by an injected embedding material, wherein the injected embedding material is filled with silica based on silicon dioxide as filler material, and the silica is silica fume, which includes amorphous, non-porous spheres of silicon dioxide and agglomerates thereof. |
| US09653235B2 |
Switch device
A switch device includes an operation unit having a pushbutton for performing a pushing operation; a switch unit separably joined to the operation unit, the switch unit including an opening-closing contact mechanism opened or closed in conjunction with the pushing operation of the pushbutton of the operation unit, and a rotary drive plate rotating between a standby position and a usage position; and an engagement portion engaging the operation unit to the rotary drive plate to rotary-drive the rotary drive plate from the standby position to the usage position when the operation unit is attached to the switch unit. The operation unit is detached from or attached to the switch unit to set the opening-closing contact mechanism in respectively predetermined opening-closing states. |
| US09653233B2 |
Rotary battery switch
A battery switch including a selector supported by a housing and rotatably mounted to the housing. The selector having four positions, including, a first position in which a first and second bank terminals are disconnected from a first and second load terminals, a second position in which the first bank terminal is connected to the first load terminal and the second bank terminal is disconnected from the second load terminal, a third position in which the first bank terminal is connected to the first load terminal, the second bank terminal is connected to the second load terminal, and the first bank terminal is disconnected from the second bank terminal, and a fourth position in which the first bank terminal is connected to the first load terminal and the second bank terminal and the second bank terminal is connected to the second load terminal. |
| US09653230B1 |
Push plate, mounting assembly, circuit board, and method of assembling thereof for ball grid array packages
A push plate that includes springs in the form of cantilever flexures and an inspection window is disclosed. The push plate provides a known, uniform, down force and minimal torque to a package to be tested. The cantilevers have a known, calculable down force producing stiffness. The window provides for viewing of the package during testing. |
| US09653227B2 |
Mechanically lockable hand switch
A switch for controlling a control circuit or an operating current of electric-motors in linear gear drives includes: a switch casing, having at least an upper part including keys, and a lower part for forming a receiving space; a circuit board incorporated in the receiving space with microswitches including a switch casing and a spring-biased push-rod therein; wherein, when the keys are actuated by a user, the push rod actuates the micro-switch to control a control circuit or operating current, and wherein the switch contains at least one locking element, transferable between a locking position, which locks the keys, and a release position, which releases the keys. To prevent damage to a switch from pressure forces during actuation, the locking device is formed such that the pressure applied to the key is transferred onto the switch casing and/or the circuit board plate over as wide an area as possible. |
| US09653225B2 |
Electrical switching device
Electronic switching device having a housing in which at least one printed circuit board with circuit parts is arranged, the housing being designed with at least one housing cover, which closes a housing opening, and with a cable bushing for a connection cable and being provided with a filling made of a plastic material which surrounds the printed circuit board with circuit parts, wherein the printed circuit board (2) is encapsulated in the housing (1) in a supported manner on a grid-like carrier body (6), to which end the grid-like carrier body (6) has individual supports (7) which span an adjustment plane (X) depending on heights (Y) of the supports (7) and on which the printed circuit board (2) can be fixed at a distance from the housing walls (8, 9, 10) for a localized arrangement of the encapsulated circuit parts in the housing (1). |
| US09653221B2 |
Method of making a carbon composition for an anode
An anode in a lithium ion capacitor, including: a carbon composition comprising: a coconut shell sourced carbon in from 85 to 95 wt %; a conductive carbon in from 1 to 10 wt %; and a binder in from 3 to 8 wt %; and an electrically conductive substrate, wherein the coconut shell sourced carbon has a disorder (D) peak to graphitic (G) peak intensity ratio by Raman analysis of from 1.40 to 1.85; and by elemental analysis a hydrogen content of from 0.01 to 0.25 wt %; a nitrogen content of from 0.01 to 0.55 wt %; and an oxygen content of from 0.01 to 2 wt %. Also disclosed are methods of making and using the carbon composition. |
| US09653220B2 |
Capacitor
To provide a capacitor capable of having a larger capacity than a case where only a solid electrolyte is simply used as a dielectric material of the capacitor. The capacitor (1) includes a solid electrolytic body (3) and a plurality of electrodes (5, 7) which is formed on the solid electrolytic body (3) and disposed opposite to each other with the solid electrolytic body (3) interposed therebetween, and the solid electrolytic body (3) includes an oxide-based lithium ion conductive solid electrolyte as a base material and contains oxide particles formed of a part of elements configuring the base material. |
| US09653219B2 |
Mesoporous nanocrystalline film architecture for capacitive storage devices
A mesoporous, nanocrystalline, metal oxide construct particularly suited for capacitive energy storage that has an architecture with short diffusion path lengths and large surface areas and a method for production are provided. Energy density is substantially increased without compromising the capacitive charge storage kinetics and electrode demonstrates long term cycling stability. Charge storage devices with electrodes using the construct can use three different charge storage mechanisms immersed in an electrolyte: (1) cations can be stored in a thin double layer at the electrode/electrolyte interface (non-faradaic mechanism); (2) cations can interact with the bulk of an electroactive material which then undergoes a redox reaction or phase change, as in conventional batteries (faradaic mechanism); or (3) cations can electrochemically adsorb onto the surface of a material through charge transfer processes (faradaic mechanism). |
| US09653215B2 |
Solid electrolyte capacitor including multiple silane coupling layers provided on a dielectric layer and method for manufacturing the same
A solid electrolytic capacitor comprises a positive electrode, a dielectric layer, a silane coupling layer, a conductive polymer layer, and a negative electrode layer. The dielectric layer is provided on the positive electrode. The silane coupling layer is provided on the dielectric layer. The conductive polymer layer is provided on the silane coupling layer. The negative electrode layer is provided on the conductive polymer layer. The silane coupling layer comprises a first silane coupling layer and a second silane coupling layer. The first silane coupling layer covers a part of a surface of the dielectric layer facing the conductive polymer layer. The second silane coupling layer covers at least a part of a portion exposed from the first silane coupling layer on the surface of the dielectric layer facing the conductive polymer layer. |
| US09653214B2 |
Laminated capacitor and laminated capacitor series and laminated capacitor mounted body including capacitor
In a laminated capacitor, a distance between an inner internal electrode at a first principal surface side, from a pair of internal electrodes that sandwich an effective dielectric layer located closest to a second principal surface side in a first sub-electrostatic capacitance portion, and a second principal surface is smaller than or equal to a distance between an internal electrode located closest to the second principal surface side in a main electrostatic capacitance portion and the inner internal electrode. |
| US09653213B2 |
Multilayer ceramic capacitor and board having the same
A multilayer ceramic capacitor may include a ceramic body having first to third dielectric layers, first and third internal electrodes disposed to be partially exposed to an upper surface of the ceramic body, second and fourth internal electrodes disposed to be partially exposed to a lower surface of the ceramic body, internal resistance electrodes disposed on the third dielectric layers and partially exposed to the upper surface of the ceramic body, first and third external electrodes disposed on the ceramic body to be connected to the first and third internal electrodes, second and fourth external electrodes disposed to be connected to the second and fourth internal electrodes. The first and third external electrodes are electrically connected to each other by the internal resistance electrodes. |
| US09653212B2 |
Multilayer ceramic capacitor and board for mounting thereof
A multilayer ceramic capacitor may include three external electrodes disposed on a mounting surface of a ceramic body so as to be spaced apart from each other. When a height of at least one portion of the external electrode formed on one side surface of the ceramic body in a width direction is defined as d, and a thickness of the ceramic body is defined as T, a ratio of d/T satisfies 0.10≦d/T. |
| US09653210B2 |
Multilayer ceramic capacitor
A multilayer ceramic capacitor may include: a ceramic body; a plurality of first internal electrodes disposed in the ceramic body; a plurality of second internal electrodes stacked alternately with the first internal electrodes in the ceramic body; first and second external electrodes connected to the first internal electrodes, respectively; a third external electrode extended from one side surface of the ceramic body to a portion of a surface opposing a mounting surface of the ceramic body and connected to the second internal electrodes; a fourth external electrode extended from the other side surface of the ceramic body to a portion of the surface opposing the mounting surface of the ceramic body; and an intermitting part disposed on the surface opposing the mounting surface of the ceramic body and connecting the third and fourth external electrodes to each other. |
| US09653209B2 |
Method for producing electronic component
A method for producing an electronic component including a laminate, a circuit element provided therein, and external conductors electrically connected thereto. The method including steps of obtaining a mother laminate that has a plurality of the laminates arranged in a matrix-like state in a first direction and a second direction perpendicular thereto. The mother laminate is cut into the laminates. In the step of obtaining, the mother laminate is obtained such that the external conductors of two laminates adjacent in the first direction are joined, and circuit elements provided in the two laminates have a point-symmetrical relationship with each other. In the step of cutting, the mother laminate is cut along first cutoff lines extending in the second direction after the mother laminate is cut along second cutoff lines extending in the first direction. The external conductors are located on corresponding first cutoff lines. |
| US09653203B2 |
Multilayer inductor
A multilayer inductor providing improved DC superposition characteristics by a permanent magnet that emits a bias magnetic flux, and having a low-loss material as a magnetic body to improve converter conversion efficiency. The multilayer inductor has a plurality of laminated electrically insulating magnetic layers; and laminated conductive patterns, each of the conductive patterns being connected in sequence in the lamination direction forming a spiral coil inside the magnetic layer. An magnetized annular permanent magnet layer emits a magnetic flux whose direction is opposite that of a magnetic flux excited by the coil is between an outer peripheral edge of the inductor and an outer peripheral edge of the coil so as not to overlap an inner peripheral part of the magnet layer with the conductive patterns and so as to block a space between the conductive patterns and the magnet layer, in axial view of the coil. |
| US09653201B2 |
Contactless feed system and shield case for the same
There is provided a shield case allowing efficient power delivery while ensuring environmental resistant such as strength and waterproof and provided a contactless feed system using the shield case.A contactless feed system includes: a feed-side device installed in a fixed body; a receive-side device installed in a mobile body and fed electric power from the feed-side device in a contactless manner, and a shield case used in the feed-side device of the contactless feed system includes: a case open toward the receive-side device; a coil housed in an interior of the case; and a cover covering an opening of the case, wherein a load support member extending from a bottom surface of the case to an inner surface of the cover is provided inside the case. |
| US09653192B2 |
PTC composition and over-current protection device containing the same
A PTC composition comprises crystalline polymer and conductive filler. The conductive filler comprises tungsten carbide powder dispersed in the crystalline polymer, and the tungsten carbide powder comprises impurity of less than 7% by weight. The impurity comprises the materials other than tungsten monocarbide. |
| US09653190B2 |
Removal device for radioactive cesium
To provide a device for removing radioactive cesium from waste material containing radioactive cesium, doing so at low energy and in a dependable manner. The removal device 1 for radioactive cesium is provided with: a rotary kiln 41 which is provided with a burner 41b supplying from the kiln outlet an organic matter O3 contaminated with radioactive cesium, and an inorganic matter charging port 41a supplying from the kiln inlet inorganic matter S4 contaminated with radioactive cesium, and which is employed to burn the organic matter O3 together with the inorganic matter S4; and a recovery device cooling tower 51, a cyclone 52, a bag filter 53 for recovering cesium that has volatilized in the rotary kiln. A drying/crushing device (dryer 21, crusher 22) for drying and crushing the organic matter O1 prior to charging the radioactive cesium-contaminated organic matter to the rotary kiln can be provided. Additionally, a reforming/drying/crushing device (reformer 31, dryer 32, crusher 23) for reforming, drying, and crushing the inorganic matter S1 can be provided. During burning of the organic matter O3 together with the inorganic matter S4, a calcium source can be added as a reaction accelerant A to the rotary kiln. |
| US09653184B2 |
Non-volatile memory module with physical-to-physical address remapping
The various embodiments described herein include systems, methods and/or devices used to enable physical-to-physical address remapping in a storage module. In one aspect, the method includes, for each of a sequence of two or more units of non-volatile memory, determining a validity state of a respective unit of memory. In accordance with a determination that the validity state of the respective unit of memory is an invalid state, the method includes storing, in a table, a second address assigned to the respective unit of memory. At least a portion of the second address is a physical address portion corresponding to a physical location of a second unit of memory. In accordance with a determination that the validity state of the respective unit of memory is a valid state, the method includes forgoing assignment of the second address corresponding to the unit of memory. |
| US09653183B1 |
Shared built-in self-analysis of memory systems employing a memory array tile architecture
Shared built-in self-analysis of memory systems employing a memory array tile architecture is provided. To selectively control which memory tile among a plurality of memory tiles is accessed for a built-in self-analysis (BISA) operation, a shared BISA address issued from a shared BISA circuit includes a memory tile address. Each memory tile includes a unique fixed memory tile address that is compared to the received memory tile address of a received BISA address. If the memory tile address in the received BISA address matches the fixed memory tile address of a memory tile, the memory tile is activated to use the memory address in the BISA address to access addressed memory bit cells for analysis. Thus, if the memory system is redesigned to include additional memory tiles for increased capacity, the memory tile address size in the BISA address can be updated for addressing added memory tiles. |
| US09653182B1 |
Testing method, manufacturing method, and testing device of memory device
According to one embodiment, a testing method of a memory device includes annealing the memory device, the memory device including a memory element; performing, after the annealing, to the memory element a process which sets a first magnetization orientation of a first ferromagnetic layer to be antiparallel to a second magnetization orientation of the second ferromagnetic layer; reading, after the performing of the process, data from the memory element; and determining the memory element as defective due to the second magnetization orientation being parallel to a third magnetization orientation of a third ferromagnetic layer, when data represented by the first magnetization orientation being antiparallel to the second magnetization orientation differs from the read data. |
| US09653177B1 |
One time programmable non-volatile memory and read sensing method thereof
A read sensing method for an OTP non-volatile memory is provided. The memory array is connected with plural bit line pairs. Firstly, the plural bit line pairs are precharged to a precharge voltage. Then, a selected memory cell connected with a specific bit line pair is determined. Then, two bit lines of the specific bit line pair are respectively connected with the data line and the reference line and are discharged to a reset voltage. After a first cell current and a second cell current from the specific bit line pair are received, a first voltage level of the data line and a second voltage level of the reference line are gradually changed from the reset voltage. According to a result of comparing the first voltage level and the second voltage level, an output signal is generated. |
| US09653176B2 |
Read disturb reclaim policy
Memory systems may include a memory including a plurality of memory blocks and a controller. The controller calculates an effective read disturb based on both a direct neighbor read disturb count and a non-direct neighbor read disturb count. The controller selects a wordline with the largest effective read disturb for test read and deciding whether to reclaim the data of the block based on the errors on the wordline. |
| US09653173B1 |
Memory cell with different program and read paths for achieving high endurance
A memory cell includes a coupling device, a read transistor, a first read selection transistor, a second read selection transistor, an erase device, a program transistor, and a program selection transistor. The coupling device is formed on a first doped region. The erase device is formed on a second doped region. The read transistor, the first read selection transistor, the second read selection transistor, the program transistor, and the program selection transistor are formed on a third doped region. A gate terminal of the coupling device is coupled to a common floating gate. A gate terminal of the erase device is coupled to the floating gate. During a program operation, electrical charges are moved from the common floating gate. During an erase operation, electrical charges are ejected from the common floating gate to the erase device. |
| US09653172B2 |
Storage device and operating method thereof
There are provided a storage device and an operating method thereof. A storage device includes a main block including a plurality of sub-blocks, a peripheral circuit for generating operation voltages used in a read operation of a selected sub-block among the sub-blocks and performing the read operation of the selected sub-block by using the operation voltages, and a control logic for, when an erased sub-block among the sub-blocks is included in the read operation, controlling the peripheral circuit to perform the read operation by lowering levels of some of the operation voltages. |
| US09653167B2 |
Semiconductor memory device using grounded dummy bit lines
A semiconductor memory device according to an embodiment comprises a memory cell array including first and second wiring line layers disposed sequentially above memory cells, the first wiring line layer including a first wiring line and a first dummy wiring line, and the second wiring line layer including a second wiring line and a second dummy wiring line, the second wiring line being disposed at the same position in the first direction as the first dummy wiring line, the second dummy wiring line being disposed at the same position in the first direction as the first wiring line, and during an access operation by a control circuit, the first and second wiring lines being electrically connected to at least one of the memory cells, and the first and second dummy wiring lines being fixed at a certain first potential. |
| US09653165B2 |
Multiplexer-based ternary content addressable memory
In one example, a ternary content addressable memory (TCAM) includes an input port coupled to receive a W-bit key as input, and an output port coupled to provide a match vector as output, the match vector including at least one bit. The TCAM further includes a memory having memory cells operable to store N*W pairs of bits for N W-bit TCAM words. The memory includes a plurality of memory outputs. The TCAM further includes at least one compare circuit. The at least one compare circuit includes at least one multiplexer each coupled to receive as input a true version and a complement version of a bit of the W-bit key. Each of the at least one multiplexer is controlled by a respective pair of memory outputs of the plurality of memory outputs. The at least one compare circuit further includes combinatorial logic coupled to perform at least one logical AND operation based on output of the at least one multiplexer. |
| US09653163B2 |
Memory cell with non-volatile data storage
The invention concerns a memory cell comprising first and second resistive elements (202, 204) coupled respectively between first and second storage nodes and first and second intermediate nodes, at least one of them being programmable to take up one of at least two resistive states (Rmin′ Rmax); a third transistor (220) coupled between the first and second intermediate nodes; a fourth transistor (502) coupled between the first storage node (206, 210) and a data input node (506); and a control circuit arranged, during a write phase, to activate the third and fourth transistors and to couple the data input node to a second supply voltage (VDD, GND) via a first circuit block (508) in order to generate a current in a first direction through the first and second resistive elements in order to program the resistive state of at least one of the elements. |
| US09653162B2 |
System and a method for designing a hybrid memory cell with memristor and complementary metal-oxide semiconductor
The embodiments herein relates to a hybrid non-volatile memory cell system and architecture for designing integrated circuits. The system comprises CMOS access transistor connected to a memristor which stores a data based on a resistance. The system has a word line for accessing the hybrid memory and two bit lines carrying data of mutually opposite values for transferring a data from the memory. The two terminals of the transistor are connected respectively to a first terminal of the memristor and to a first bit line. The gate terminals of the transistors are coupled together to form a word line. The access transistors control the two bit lines during a read and write operation. A control logic performs a read and write operation with the hybrid memory cells. The memory architecture prevents a power leakage during data storage and controls a drift in a state during a read process. |
| US09653160B2 |
Memory device reducing test time and computing system including the same
A memory device includes memory cell array and an address decoder. The memory cell array includes a normal memory region and a redundant memory region. The normal memory region operates in response to data signal and plurality of normal memory region signals. The redundant memory region operates in response to data signal and plurality of redundant memory region signals. The address decoder includes normal memory region signal generator and redundant memory region signal generator. The normal memory region signal generator activates first normal memory region signals and redundant memory region signal generator activates first redundant memory region signal simultaneously when address decoder operates in test mode. First normal memory region signals correspond to an address signal and are included in plurality of normal memory region signals. A first redundant memory region signal corresponds to an address signal and is included in the plurality of redundant memory region signals. |
| US09653159B2 |
Memory device based on conductance switching in polymer/electrolyte junctions
A non-volatile memory device including at least a first electrode and a second electrode provided on a substrate, the first and second electrodes being separated from each other; an organic semiconductive polymer electrically connecting the first and second electrodes; an electrolyte in contact with the organic semiconductive polymer; and a third electrode that is not in contact with the first electrode, the second electrode, and the organic semiconductive polymer; wherein the organic semiconductive polymer has a first redox state in which it exhibits a first conductivity, and a second redox state in which it exhibits a second conductivity. |
| US09653155B1 |
Nonvolatile memory device having connection unit for allowing precharging of bit lines in single step
A nonvolatile memory device may include a cell string comprising a plurality of memory cells coupled in series; a bit line coupled to the cell string; a page buffer suitable for driving a sensing node to a ground voltage, a middle voltage, and a core voltage during a normal program operation, a slow program operation and a program inhibition operation, respectively; and a connection unit suitable for coupling the bit line to the sensing node in response to a control signal of a first voltage during the slow program operation, and in response to the control signal of a second voltage higher than the first voltage during the normal program operation and the program inhibition operation. |
| US09653153B2 |
Phase hysteretic magnetic josephson junction memory cell
One embodiment describes a memory cell. The memory cell includes a phase hysteretic magnetic Josephson junction (PHMJJ) that is configured to store one of a first binary logic state corresponding to a binary logic-1 state and a second binary logic state corresponding to a binary logic-0 state in response to a write current that is provided to the memory cell and to generate a superconducting phase based on the stored digital state. The memory cell also includes a superconducting read-select device that is configured to implement a read operation in response to a read current that is provided to the memory cell. The memory cell further includes at least one Josephson junction configured to provide an output based on the superconducting phase of the PHMJJ during the read operation, the output corresponding to the stored digital state. |
| US09653151B1 |
Memory array having segmented row addressed page registers
The access speeds of new memory technologies may not be compatible with product specifications of existing memory technologies such as DRAM, SRAM, and FLASH technologies. Their electrical parameters and behaviors are different such that they cannot meet existing memory core specifications without new architectures and designs to overcome their limitations. New memories such as STT-MRAM, Resistive-RAM, Phase-Change RAM, and a new class of memory called Vertical Layer Thyristor (VLT) RAM requires new read sensing and write circuits incorporating new voltage or current levels and timing controls to make these memory technologies work in today's systems. Systems and methods are provided for rendering the memory cores of these technologies transparent to existing peripheral logic so that they can be easily integrated. |
| US09653150B1 |
Static random access memory (SRAM) bitcell and memory architecture without a write bitline
A bit cell and memory architecture wherein a write bitline is not required is presented. The bitcell and the memory architecture bring a huge improvement in the performance, dynamic power, leakage power, area, and the yield of the memory. |
| US09653143B2 |
Apparatuses including memory section control circuits with global drivers
Apparatuses, memory section control circuits, and methods of refreshing memory are disclosed. An example apparatus includes a plurality of memory sections and a plurality of memory section control circuits. Each memory section control circuit is coupled to a respective one of the plurality of memory sections and includes a plurality of access line drivers, each of which includes a plurality of transistors having common coupled gates. During an operation of the apparatus a first voltage is provided to the commonly coupled gates of the transistors of at least some of the access line drivers of the memory section control circuit coupled to an active memory section and a second voltage is provided to the commonly coupled gates of the transistors of the access line drivers of the memory section control circuit coupled to an inactive memory section control circuit, wherein the first voltage is greater than the second voltage. |
| US09653136B2 |
Memory device, comprising at least one element and associated method spintronics
A storage device, comprising at least one spintronic element suitable for representing a state among at least n states associated with the spintronic element, n>1, characterized in that each of the n states is associated with at least one characteristic of a group of magnetic skyrmions in the spintronic element, and in that said characteristic associated with a state n oi is different from said characteristic associated with a state n oj when the states n oi and n oj are two different states among the n states. |
| US09653133B2 |
Semiconductor device and semiconductor system
A semiconductor system may include a command processor configured to decode a command to generate an active pulse and a delayed active pulse, and a bank active signal generation circuit configured to generate a bank active signal for performing an active operation for a bank accessed by an address. The bank active signal may be disabled in synchronization with the active pulse and is enabled in synchronization with the delayed active pulse. |
| US09653130B1 |
Latency control device and semiconductor device including the same
A latency control device and a semiconductor device including the same may be provided. The latency control device may include a first delay controller configured to delay a command signal based on a first internal clock having a first phase and a control signal. The latency control device may include a second delay controller configured to delay the command signal based on a second internal clock having a second phase different from the first phase and a test control signal. The latency control device may include a selection circuit configured to select any one of an output signal of the first delay controller and an output signal of the second delay controller based on a selection signal, and output a latency signal. The latency control device may include a test controller configured to generate the test control signal based on the control signal and a test signal. |
| US09653125B2 |
Storage device, memory device and semiconductor device for improving data transfer speeds
According to one embodiment, a storage device includes a memory device including a memory cell configured to hold data, an output buffer configured to output the data, and a circuit configured to generate a reference voltage; and a controller device including an input buffer. The data from the output buffer is input into one input terminal of the input buffer and the reference voltage from the circuit is input into the other input terminal of the input buffer. |
| US09653124B2 |
Dual-sided rackmount storage assembly
Systems, methods, apparatuses, and assemblies for data storage systems are provided herein. In one example, a data storage assembly is presented. The data storage assembly includes a midplane assembly configured to electrically couple on a first side to storage modules and compute modules, electrically couple on a second side to communication modules and one or more power supply modules. The data storage assembly includes a chassis configured to mechanically house and structurally support each of the storage modules, the compute modules, the communication modules, and the one or more power supply modules when coupled to the midplane assembly to form the data storage assembly and allow installation of the data storage assembly into a rackmount environment. |
| US09653120B2 |
Movie advertising playback systems and methods
An ad in a movie can be a static ad having a position in the movie that cannot be moved, or a dynamic ad having a position in the movie that can be changed. When a viewer of the movie wishes to skip a portion of the movie containing the ad, the playback system determines whether the ad is static or dynamic. If the ad is static, then only the portion of the movie preceding the static ad can be skipped, that is, the ad is unskippable; this technique is referred to as “bounceback” since the end of the skip bounces back to the start of the static ad. If the ad is dynamic, then the ad is moved to after the end of the skip; this technique is referred to as “slipad” since the ad slips to later in the movie. When a movie has multiple ads, some can be static and some can be dynamic. |
| US09653119B2 |
Method and apparatus for generating 3D audio positioning using dynamically optimized audio 3D space perception cues
An apparatus generating audio cues for content indicative of the position of audio objects within the content comprising: an audio processor receiving raw audio tracks for said content and information indicative of the positions of at least some of said audio tracks within frames of said content, said audio processor generating corresponding audio parameters; an authoring tool receiving said audio parameters and generating encoding coefficients, said audio parameters including audio cue of the position of audio objects corresponding to said tracks in at least one spatial dimension; and a first audio/video encoder receiving an input and encoding said input into an audio visual content having visual objects and audio objects, said audio objects being disposed at location corresponding to said one spatial position, said encoder using said encoding coefficients for said encoding. |
| US09653110B2 |
Speed control of data storage device using service controller
Embodiments generally relate to data storage in a computing system. The present technology discloses techniques that that can enable an optimized mechanism to change spinning speed of data storage disk drives. The present technology can use a service controller, e.g. a Baseboard Management Device (BMC), to communicate with a disk controller to change the spinning speed of disk drives. The present technology can improve energy efficiency by efficiently controlling the spinning speed of disk drives. It can also reduce data access latency by promptly spinning up a disk from a spun-down state. |
| US09653109B2 |
Low friction tape head
A drive-implemented method according to one embodiment includes guiding a magnetic medium over a magnetic head at an angle at which the magnetic medium flies over a leading outer portion of the head, engages a leading edge of a tape bearing surface of a central portion of the head, and engages an inner edge of a tape bearing surface of a trailing outer portion of the head. The inner edge of the tape bearing surface of the trailing outer portions skives air from the magnetic medium when the magnetic medium travels in a direction from the central portion towards the trailing outer portion. |
| US09653107B2 |
Hologram recording and playback device and hologram playback method
A hologram recording and playback device is provided with: a medium rotation unit which rotates a hologram recording medium around a predetermined rotational axis; a movement unit which is capable of moving the position of the medium rotation unit within a plane that is perpendicular to the rotational axis; an orthogonal incident angle modification unit which is capable of modifying an orthogonal incident angle; a medium rotation control unit which controls the medium rotation unit so as to rotate the hologram recording medium; an eccentricity compensation unit which performs positioning control of the movement unit; an orthogonal incident angle control unit which controls the orthogonal incident angle modification unit; and an orthogonal incident angle calculation unit which calculates the orthogonal incident angle. |