专利汇可以提供STACKED PACKAGE-ON-PACKAGE MEMORY DEVICES专利检索,专利查询,专利分析的服务。并且3D Stacked memory devices with copper pillars electrically connecting the package units are disclosed. A stacked package-on-package memory device includes a base chip package unit having a logic processing chip disposed on a base substrate; and a memory chip stack overlying the base chip unit. The memory chip stack includes a stack of packaged memory units. Each packaged memory unit including a memory chip on an IC substrate. Copper pillars are disposed on the back side of the IC substrate and electrically connected to the base substrate.,下面是STACKED PACKAGE-ON-PACKAGE MEMORY DEVICES专利的具体信息内容。
What is claimed is:
This application is a continuation-in-part application of U.S. application Ser. No. 14/445,574 filed Jul. 29, 2014 the disclosure of which is incorporated by reference herein in its entirety.
1. Technical Field
The present disclosure relates to three dimensional (3D) stacked memory devices, and more particularly, to 3D stacked package-on-package memory devices with copper pillars electrically interconnecting the package units thereof.
2. Description of Related Art
Three dimensional package-on-package (PoP) technologies for logic device plus memory stacks include an integrated circuit packaging to vertically combine a logic device or a memory controller and a memory package stack which contain high capacity or combination memory devices. The memory package stack includes two or more packages which are installed atop each other with direct vertical chip connection using through silicon via (TSV) to route signals therebetween. This allows higher performance and component density in handheld devices, such as mobile phones, personal digital assistants (PDA), and digital cameras.
In general, cost for 3D DRAM packages increases by using expensive TSV staking. TSV technologies utilizing vertical vias in the silicon wafers are used to interconnect each of the chips. Using through silicon vias substantially results in shortened interconnect length, improved electrical performance, and reduced power consumption by the memory device.
Alternatively, 3D memory stack with copper pillar interconnections uses solder bumps with plating a lead-free solder cap on top of the copper pillar. Requirements for developing 3D stack with copper pillar interconnections lead to new package technologies, particularly replacing wire bonding in many higher end devices that require high I/O density, low production cost and small area packaging.
To achieve one or more objectives, 3D stacked memory devices with copper pillars electrically connecting the PoP memory units are provided. By using copper pillar via, high performance, high I/O density, low fabrication cost, and small area packaging can be achieved.
According to an aspect, a stacked package-on-package memory device comprises a base chip package unit having a logic processing chip disposed on a base substrate and at least one stacked memory package unit overlying the base chip package unit. The at least one stacked memory package unit includes a memory chip on an IC substrate. Copper pillars are disposed on the back side of the IC substrate and electrically connected to the base substrate.
In some embodiments, the memory chip includes a DRAM chip, a mobile DRAM chip, a low power DDR (LPDDR) chip, a high bandwidth memory (HBM) chip, a hybrid memory cube (HMC) chip, and a Wide I/O2 chip, etc. Besides on top of the dielectrics, copper traces or pads are fully or partially embedded into a dielectric layer on the base substrate. The copper traces or pads have surfaces finished for protection during structure assembly.
According to another aspect, a stacked package-on-package memory device comprises a base chip package unit having a logic processing chip disposed on a base substrate and a memory chip stack overlying the base chip unit. The memory chip stack includes a stack of packaged memory units, each packaged memory unit comprising a memory chip on an IC substrate. Copper pillars are disposed on the back side of the IC substrate and electrically connected to the base substrate.
According to another aspect, a stacked package-on-package memory device comprises a main circuit board with through via and interconnections therein, a logic processing chip disposed on the main circuit board, and a memory chip stack disposed side-by-side with the logic processing chip on the main circuit board, wherein the memory chip stack includes a stack of packaged memory units, each packaged memory unit comprising a memory chip on an IC substrate, and wherein copper pillars are disposed on the back side of the IC substrate and electrically connected to the base substrate.
The foregoing aspects and many of the attendant advantages will become more readily appreciated as the same becomes better understood by reference to the following detailed description, when taken in conjunction with the accompanying pictures, wherein:
Reference will now be made in detail to the present preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts. In the drawings, the shape and thickness of an embodiment may be exaggerated for clarity and convenience. This description will be directed in particular to elements forming part of, or cooperating more directly with, apparatus in accordance with embodiments of the present invention. It should be noted that the features illustrated in the drawings are not necessarily drawn to scale, and like reference numerals represent the same or similar elements. The devices, elements, and methods in the following description are configured to illustrate embodiments of the present invention, and should not be construed in a limiting sense.
3D stacked memory packages comprising very low profile packages combine independent logic devices and memory package units stacked one on top of the other. Switching from a single PoP memory device to 3D memory stack using copper pillar interconnections will enable high I/O density, low production cost, and reduction of both package size and power consumption. Embodiments of the present invention disclose 3D stacked package-on-package memory devices with copper pillars electrically interconnecting the package-on-package device units.
While the exemplary embodiment is described in conjunction with a low power mobile DRAM chip, the features of the memory chip 140 may also be applied to other memory chips, such as a DDR chip, a high bandwidth memory (HBM) chip, a hybrid memory cube (HMC) chip and a wide 110 memory chip. In some embodiments, the IC substrate or IC package is not limited to memory chips, and is applicable to other types of ICs or chips.
Electrical interconnection components 145 including copper bumps of the memory chip 140 jointing copper traces or pads on the IC substrate 120 are interposed between the memory chip 140 and the IC substrate 120. The copper traces or pads are fully or partially embedded into a dielectric layer on the base substrate. The copper traces or pads have surfaces finished for protection during structure assembly. Alternatively, the copper trace or the copper pad protrudes out of the IC substrate.
To further reduce the height of the memory chip package unit 100, the memory chip can be further thinned down by grinding or polishing. A mold encapsulation 150 can be implemented on the memory chip 140 such that a thin die and mold cap are formed. In one embodiment, through mold vias (not shown) filled with copper can be alternatively formed as electrical connections.
The base chip package unit 200 comprises an array of solder balls 215, or other interconnecting arrangement such as C4 (controlled collapse chip connection) balls or the interconnecting arrangements described with respect to
According to embodiments of the present invention, there at least two varieties of copper interconnections. One of the copper interconnections is memory chip to IC substrate interconnections. Electrical interconnection components 145 including copper bumps of the memory chip 140 jointing copper traces or pads on the IC substrate 120 are interposed between the memory chip 140 and the IC substrate 120. The copper traces or pads are fully or partially embedded into a dielectric layer on the base substrate 220. The copper traces or pads have surfaces finished for protection during structure assembly. Alternatively, the copper trace or the copper pad protrudes out of the IC substrate. The other copper interconnection is package to package interconnections. Copper pillars 125 are disposed on the back side of the IC substrate 120 and electrically connected to the IC substrate or base substrate of other package units.
The I/O pad locations are considerations for stacked memory packaging. For example, arrangement of I/O pads for low power mobile DRAM is different from those for other DRAM chips. The I/O pads for low power mobile DRAMs are distributed as a line-by-line architecture at both the peripheral ends of the memory chip. It would be preferable in some embodiments to implement bond on lead (BOL) interconnection in the mobile DRAM packaging architecture. BOL interconnection comprising attachment of bumps to narrow pads or traces allows finer effective pitch.
According to embodiments of the present invention, a 3D stacked memory device including multilevel package-on-package (PoP) assembly is provided. The 3D stacked memory device includes a base chip package unit having a logic processing chip (or a memory controller chip) disposed on a base substrate and a memory chip stack overlying the base chip unit. The memory chip stack includes a stack of packaged memory units, each packaged memory unit comprising a memory chip on an IC substrate. Copper pillars are disposed on the back side of the IC substrate and electrically connected to the base substrate.
The main circuit board 410 further comprises an array of solder balls on the bottom surface of the base substrate. There are additional features not mentioned here, which complete the stacked package-on-package memory device 20.
Embodiments of the present invention are advantageous in that by careful monitoring and controlling of the copper pillar's critical features and physical properties, a high quality, reliable bump structure is achievable. Signals can trace upwardly and downwardly through copper pillar interconnection. Copper pillar stacked PoP memory devices enable a higher I/O pad density architecture. The number of I/O pads generally more than 1000 can be easily achieved in one or more embodiments. By comparison with other 3D memory stacks with TSV connection, production cost can be apparently reduced in one or more embodiments.
The IC substrate 120 which has a core sheet 50. A top circuitry 55T embedded in dielectric layers 51 such as prepreg or Ajinomoto Build-up film (ABF), is configured on top of the core sheet 50. A bottom circuitry 55B embedded in dielectric layers 51 is configured on bottom of the core sheet 50. A plurality of plated through holes 56 passing through the core sheet 50 electrically couples the top circuitry 55T with the bottom circuitry 55B. A layer of solder resist SR covers the top surface of the top circuitry 55T and a plurality of top metal pad 50P is exposed from the solder resist SR. The top metal pad 50P is configured for a chip or chips 140 to mount thereon.
A memory module can be formed, in one or more embodiments, as the stacked structure of
While the invention has been described by way of examples and in terms of preferred embodiments, it would be apparent to those skilled in the art to make various equivalent replacements, amendments and modifications in view of specification of the invention. Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such replacements, amendments and modifications without departing from the spirit and scope of the invention.
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