Addressing system responsive to a transfer vector for accessing a memory
阅读：740发布：2022-08-02
专利汇可以提供Addressing system responsive to a transfer vector for accessing a memory专利检索，专利查询，专利分析的服务。并且A memory comprising a plurality of bit storing containers each having upper and lower boundaries is partitioned into a plurality of modules. The containers in each module are arranged in a plurality of locations. Fields of data bits can be stored partly in one module and partly in another module and can thereby extend across the boundary between modules. Each module is coupled to its own access control means. During a memory access, each access control means receives an absolute address signal, responds thereto to select a location in its associated module; all the containers in the selected location are accessed; and data bits are transferred between a data register and a selected group of the accessed containers. The absolute addresses are derived from a bit boundary address and a transfer vector. The bit boundary address comprises a field of encoded signals which field has a length sufficiently long to specify an arbitrary boundary in the memory. A subfield of the bit boundary address is selectively modified by address modifying circuitry so as to produce the absolute addresses. The transfer vector comprises a transfer sign field and a transfer width field. The transfer sign field indicates which side of a specified boundary has the containers involved in the data transfer. The transfer width field indicates the number of bit containers involved in the data transfer. Circuitry coupling the memory to the data register provides rotation and masking so that the contents of accessed containers which are not involved in the data transfer do not affect the data transfer or change as a result thereof.，下面是Addressing system responsive to a transfer vector for accessing a memory专利的具体信息内容。
1. A memory and addressing system therefor comprising: an input-output circuit; a memory comprising a sequence of addressable memory locations, a separate one of a sequence of memory location addresses being assigned to each of said memory locations, each location including a plurality of bit storing containers, the containers being assigned a predetermined sequential order within memory locations and from one memory location to the next in the sequence of memory locations, thereby forming a corresponding sequence of imaginary boundaries located between adjacent containers in the sequential order, a sequence of boundary addresses assigned, one to each of, said imaginary boundaries,; means for receiving address codes identifying a desired continuous sequence of containers, each address code comprising a first field for specifying as the beginning of the desired continuous sequence any one of the boundary addresses and a second field for specifying the desired continuous sequence of containers as being on one of either side of the specified boundary address, predetermined ones of said address codes identifying a desired continuous sequence of containers in a plurality of different memory locations and having a first field specifying a boundary address between any two adjacent containers included within a single memory location; circuit means responsive to said received addresses for producing memory location addresses and comprising means responsive to said predetermined address code for producing a plurality of memory location addresses comprising the address of each of said plurality of different memory locations including the address of said single memory location; the memory further including memory accessing means for accessing each of the memory locations corresponding to the plurality of produced memory location addresses; and circuit means coupled between the input-output circuit and the memory for selectively transferring bits therebetween and comprising selection means responsive to the same predetermined address code used for accessing for selecting bits for transfer between only the identified desired continuous sequence of containers and the input-output circuit.
2. A system according to claim 1 wherein the receiving means includes means for receiving a third field as a part of each address code, the third field for specifying one of a variable number of containers and wherein the circuit means for selectively transferring bits includes means responsive to each received third field for transferring only the number of bits specified by the third field.
3. A system according to claim 1 wherein the memory comprises a plurality of independently addressable memory modules having corresponding pluralities of said locations; the memory accessing means includes a different module access control circuit coupled to each memory module, each module access control circuit being responsive to an absolute address to access in parallel all containers in the corresponding location in the memory location to which it is coupled; and wherein the circuit means for producing memory location addresses provides substantially simultaneously a memory location address to each module access control circuit.
4. A memory and addressing system therefor comprising: register means; a memory including a sequence of addressable memory locations, the memory locations having respectively assigned to them a separate one of a sequence of memory location addresses, each location including a plurality of bit storing containers, the containers being assigned a predetermined sequential order within memory locations and from one memory location to the next in the sequence of memory locations, thereby defining a corresponding sequence of imaginary boundaries each shared with adjacent containers on opposite sides, a first one of the locations having stored in some of its containers one part of a field of information and a second one of the locations having stored in some of its containers another part of the field of information such that the field of information is stored in a continuous sequence of containers; a source of address codes, each address code for identifying a continuous sequence of containers and comprising first and second fields, the first field for specifying as the beginning of the identified continuous sequence an arbitrary boundary address, the second field for indicating the direction in which the identified sequence of containers extends from the specified boundary address, the address codes including first and second address codes that each identify the same containers that are in the first and second location and that store the field of information; circuit means for producing memory location addresses, the circuit means being coupled to the address code source, and responding to either the first or second address codes to produce the memory location addresses for the first and second locations; memory access means including means responsive to the produced memory location addresses to read out all of the bits stored in the first and second locations; and circuit means coupled between the register means and the memory for selectively transferring bits and including selective transfer means responsive to either the first or second address code for transferring to the register means out of all the bits read out of the first and second locations only those bits forming said field of information.
5. Apparatus according to claim 4 wherein the means producing the memory location addresses includes address modification means modifying the first field to produce a first modified address in response to the first address code and to produce a second, different modified address in response to the second address code, the first modified address being the address of the first location and the second modified address being the address of the second location.
6. Apparatus according to claim 5 wherein the address code source further comprises means providing a third field for indicating the number of bits in a field of information; and wherein the selective transfer means includes isolating means responsive to the third field for transferring to the register means the number of bits of information indicated by the third field and read out from the memory by the memory access means.
7. Apparatus according to claim 4 wherein the memory comprises a plurality of independently addressable memory modules having corresponding pluralities of said locations, and the memory access means include a different module access control circuit coupled to each memory module, each access control circuit being responsive to an memory location address to read out in parallel all containers in a selected location in the memory module to which it is coupled; and wherein the address producing means provides substantially simultaneously a memory location address to each module access control circuit so that the first and second locations can be read out at substantially the same time.
8. Apparatus according to claim 7 wherein the address code source further comprises means providing a third field for indicating the number of bits in a field of information; and wherein the selective transfer means includes isolating means responsive to the third field for transferring to the register means the number of bits indicated by the third field and read out substantially simultaneously from the memory modules by the module access control circuits.
9. Apparatus according to claim 7 wherein the source of address codes includes means for providing as a part of the first field a subfield that is the memory location address of the location in one of the memory modules and which location includes a container sharing the specified boundary address; and wherein the means producing the memory location addresses includes means for modifying the first field to produce A modified address, means to provide the subfield as an absolute address to one of the module access control circuits and, means to provide the modified address as a memory location address to at least one other module access control circuit.
10. Apparatus according to claim 7 wherein the register means is a multi-stage register for storing multi-bit fields in a predetermined order of significance; and further comprising a memory read register; each module access control circuit loading a different portion of the memory read register with data bits read out of the selected location in the module to which it is coupled; and wherein the selective transfer means includes rotation circuit means coupled between the memory read register and the multi-stage register for transferring a field of information therebetween such that the multi-stage register receives multi-bit fields of information in the predetermined order of significance.
11. A memory system comprising an addressable memory having a plurality of sequentially adjacent containers including a top container, a bottom container, and a plurality of intermediate containers, each container for storing a bit of a field of information, and each container having an upper and a lower boundary address with the upper and lower boundary addresses of each intermediate container being shared with adjacent containers on opposite sides; first means for simultaneously identifying any arbitrary contiguous group of adjacent containers, each such group having a lower boundary address, an upper boundary address, and a variable number of containers therebetween, the variable number being between one and a prefixed number greater than one, the first means including means for storing a three address field, the first address field for specifying an arbitrary boundary address between adjacent containers storing data bits of two different fields of information, the second address field for indicating whether the first field specifies the upper or lower boundary address of the contiguous group, and the third field indicating the variable number; and second means responsive to the first means for transferring only the data bits stored in the identified contiguous group to a circuit in the system.
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