This is a continuation of application Ser. No. 335,638, filed Dec. 30, 1981, now abandoned, which is a continuation of application Ser. No. 164,361, filed June 30, 1980, now abandoned, which is a continuation of application Ser. No. 900,265 filed Apr. 26, 1978, now abandoned.

BACKGROUND OF THE INVENTION

The subject invention relates to data communication equalizers and more particularly to automatic adaptive equalizers utilized in high speed data modems. The equalization scheme of the subject invention is particularly adapted to implementation under microprocessor control and provides a method and apparatus for performing highly accurate, ultra-fast equalization by operation on the channel response to only a single transmitted test impulse.

The equalizer of the invention is particularly suited to high speed polling applications. In such applications, it is customary to rapidly successively address a number of remote stations, for example in different cities, from a central site. Transmission from each remote station involves a new transmission line such that equalization must be re-established each time a new remote site is polled. Therefore, it is highly desirable to shorten the equalization time as much as possible in order to increase data throughput.

Many prior art equalizers have been relatively slow to equalize when first connected to a new transmission line and have thus wasted valuable data throughput time. Typically, many time consuming incremental adjustments of the equalizer taps are required during analysis of a relatively long period of random data or a training pattern containing numerous test pulses.

One prior art system proposes to equalize on a single transmitted test pulse but actually requires a multiplicity of test pulses. This system is disclosed in the Bell System Technical Journal, Vol. 50, No. 6 pp. 1969-2041, in an article by Robert W. Chang titled "A New Equalizer Structure for Fast Start Up Digital Communications."

Another prior art system, disclosed in U.S. Pat. No. 3,962,637 issued to David Motley et al, achieves equalization during the duration of the response to two transmitted impulses utilizing a technique which approximates the well-known zero-forcing scheme and does not employ correlation of signal samples. Equalization in this system requires an extra impulse to adjust the phase of the line signal so that proper sampling will occur. Because this system uses a zero-forcing scheme and then only an approximation thereto, it will not work on a highly distorted line or when high precision is necessary. While the Motley system suggests itself for operation at 4800 bps, it is not suitable for operation at the much higher data rate of 9600 bps at which the equalizer of the subject invention can operate.

In IEEE Transactions On Communications, Vol. Com-23, No. 6, June 1975, P. Butler et al disclose a method permitting a direct solution of a matrix equation in real variables describing the settings of equalizer tap constants in a single sideband system. This technique does not equalize on a single impulse response, but rather uses a much longer training sequence to reach an estimation of reasonable accuracy than that proposed by the subject invention. Moreover, Butler et al. do not solve a complex variable matrix equation. Accordingly the approach does not achieve equalization in a double sideband system as does the subject invention.

SUMMARY OF THE INVENTION

It is therefore an object of the invention to provide a faster operating and more accurate equalizer for data transmission systems.

It is another object of the invention to provide a practical equalizer which requires analysis of only a single transmitted impulse to initially set the equalizer taps for a wide range of varying line distortions and data rates.

It is another object of the invention to provide an equalizer wherein the equalizer tap constants are calculated exactly, rather than by using approximations.

It is another object of the invention to achieve such an exact calculation by an iterative technique which is performed during the time when a transmitted impulse response is being received such that the equalizer tap constants are calculated and set during the interval between the end of the impulse time and the time when the first received data reaches the major tap of the equalizer.

It is another object of the invention to provide an equalizer which can achieve a precise initial setting within a very fast time, such as 30 milliseconds for a data rate of 9600 bps and 15-20 milliseconds for a data rate of 4800 bps.

According to the invention, these and other objects and advantages are achieved by analyzing a signal that is transmitted from a transmitter over a communication medium. That signal may include, for example, a single received impulse response. From the received signal, the apparatus forms in-phase and quadrature phase impulse response signals. The in-phase and quadrature phase impulse response signals may be in passband or baseband or other translated frequencies. Sampled values from these two impulse response signals are employed to define a complex matrix equation. One complex matrix of that equation has elements formed by the auto and the cross correlation of sampled values taken from the in-phase and quadrature impulse response signals. The equalizer of this invention solves the complex matrix equation thus formed and obtains the exact values for initial setting of all equalizer taps. The initial equalizer settings compensate fully and completely for distortion in the communication medium over which the training signal was transmitted. After initial setting with the equalizer apparatus of this invention, more conventional adaptive equalization occurs during receipt of data.

The apparatus of the invention has the major advantage of enabling precise equalization constant calculations from the samples in a in a minimal amount of time despite wide variations in the distortion induced by the medium over which the received impulse is transmitted. Utilizing the invention, an equalizer has been constructed which can achieve initial equalization in a time on the order of 30 milliseconds at a data rate of 9600 bits per second. This is nearly five times faster than equalization can be achieved by presently commercially available systems. In the preferred embodiment of the invention, equalization is performed in response to a single received impulse, and an important feature of the preferred apparatus is provision of a means to determine the optimum points at which to sample the impulse response prior to receiving it. While equalization is performed using in-phase and quadrature phase impulse response signals at baseband frequencies in the preferred embodiment, such signals may be derived at passband or other translated frequencies.

BRIEF DESCRIPTION OF THE DRAWINGS

The preferred embodiment and best mode presently contemplated for implementing the just summarized invention will now be described in detail in conjunction with the drawings of which:

FIG. 1A illustrates the received signal utilized by the equalizer of the preferred embodiment.

FIGS. 1B and 1C illustrate two phase components in relative quadrature produced from the received signal on the same time scale as FIG. 1A.

FIG. 2 is a schematic diagram useful in illustrating the structure and operation of the equalizer of the preferred embodiment.

FIG. 3 is a schematic diagram illustrating the digital processor utilized in the preferred embodiment of the invention.

FIG. 4 is a flow diagram illustrating the overall structure and operation utilized to properly time the sampling of the received signal in the preferred embodiment.

FIG. 5 is a detailed flow diagram illustrating the method and apparatus utilized to detect the presence of the received signal in the preferred embodiment.

FIG. 6 is a detailed flow diagram illustrating the method and apparatus employed in the preferred embodiment to properly set the points for sampling the received signal.

FIG. 7 is a detailed flow diagram illustrating the method and apparatus employed in the preferred embodiment to determine the equalizer tap constant settings from the samples of the received signal.

FIG. 8 is a continuation of the flow of FIG. 7.

FIG. 9 illustrates one technique suitable for generating phase quadrature signals for use in the subject invention.

FIG. 10 illustrates an alternative technique for generating phase quadrature signals for use in the subject invention.

FIG. 11 illustrates an alternative technique for generating phase quadrature signals for use in the subject invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

The automatic adaptive equalizer of the invention may be conveniently introduced in conjunction with the training pattern waveform utilized to set up automatic gain control, timing and equalization, as shown in FIG. 1. The training pattern of FIG. 1 is the analog demodulated pattern at the receiver after transmission. The system of the preferred embodiment is particularly directed to the quadrature amplitude modulation (QAM) technique.

The training pattern includes in succession a number of bauds of carrier-only 11, a number of bauds of clock-only 13, a quiet or squelch period 15, a received impulse 17, and another squelch period 19. The training pattern may also include an optional fine tuning sequence before the transmission of customer data 20.

In the preferred embodiment, eight bauds of carrier-only 11 and seventeen bauds of clock-only 13 are sent. The squelch periods 15, 19 are twenty-seven and twenty-one bauds long, respectively, and the impulse period is one baud long when sent. Each baud period is 416.7 miliseconds. Of course, other baud periods could be utilized. Also, the length of the periods 11, 17, 15 and 19 depend on the maximum distortion. When the line distortion is less, fewer bauds are required for each one of them, especially for periods 17, 15 and 19, and the total time for tuning will be shorter. When the line distortion is severe, more bauds are required for each period, and the total tuning time will be longer.

During the carrier-only period 13 in FIG. 1, the initial incidence of carrier energy on the line is detected (carrier detect), starting system operation. When carrier detect occurs, a rough timing counter KSTMX is started, which ultimately anticipates the occurrence of the impulse response 17. KSTMX counts once per baud.

Automatic gain control is then performed on the carrier-only signal 11. After a fixed number of bauds of carrier-only 11 are detected, the system knows it is actually receiving a training pattern and can then expect the clock-only signal 13.

During the clock-only pattern 13, the apparatus examines the transmitted pattern to determine the optimum points to sample the forthcoming impulse response 17. The apparatus then sets up for the impulse response sampling procedure. The first step is to use the sampling point previously calculated to jump or preset the sampling clock to the optimum sampling position. It may thus be seen that the preferred embodiment actually samples the response to a transmitted impulse although other means for generating signals representative of such samples could be employed.

During the squelch period 15, the rough timing counter KSTMX, which was set-up upon detection of carrier-only, continues to count to subsequently indicate to the apparatus the point in time at which to start to sample the in-phase and quadrature phase impulse responses 17 (FIG. 1B, 1C). The samples are then taken, stored and correlated for forming a matrix. After the matrix is formed a special iterative technique is utilized to determine the precise initial equalizer tap settings, as discussed further below.

The apparatus employed to perform these operations is illustrated conceptually in block form in FIG. 2. The apparatus includes an analog to digital (A/D) converter, an automatic gain control (AGC) section 21, a digital processor 23, and a transversal equalizer 28. The equalizer 28 is shown conceptually for purposes of illustration and is preferably implemented digitally, in which case it could also be shown as part of the digital processor 23.

Digital demodulation of the QAM signal into in-phase (X) and quadrature-phase (Y) baseband components, is preferably accomplished in the digital processor 23. The analog form of the demodulated in-phase and quadrature-phase baseband components is illustrated in FIGS. 1B and 1C, respectively. Demodulation again may be performed by well-known techniques and may optionally be performed by dedicated apparatus outside the digital processor 23. Neither the AGC or demodulation technique used form a part of the subject invention.

The X and Y phase components produced by demodulation represent samples in digital form of the baseband signal, the Y component sample being demodulated by a carrier 90° out of phase from the carrier demodulating the X component sample. In order to calculate the proper sampling time during the clock-only period, two samples per baud are taken in the preferred embodiment. After the optimum clock phase is set, the system takes one sample per baud.

These samples X, Y are sent to separate channels 25, 27 of the transversal equalizer 28. Each channel 25, 27 includes equally spaced digital delay elements 29, 31 and digital multipliers 30, 32, 33, 35 as known in the prior art. The multipliers 32, 33 multiply the delayed samples X_m by constants cp_i and cq_i while the multipliers 30, 35 multiply the delayed samples Y_m by constants cp_i and cq_i. The "constants" just referred to are also called "coefficients" by some persons in the art. The outputs of each multiplier 30, 32, 33, 35 are summed by respective summers 40, 42, 44, 46 and fed to an adder 36. The output of one summer 46 is subtracted from that of the other 42 in a summer 37 to give the output data signal EQX. The outputs of the other two summers 40, 44 are summed by a summer 36 to give the output data signal EQY.

As shown in more detail in FIG. 3, the preferred embodiment of the invention includes a programmed microprocessor structure and an equalizer unit. The equalizer unit 34 includes the functions of the equalizer 28 of FIG. 2 and performs steady state adaptive equalization, for example as taught in U.S. Pat. No. 4,035,625 issued on July 12, 1977, assigned to the present assignee and incorporated by reference herein. In the preferred structure of the present invention, the equalizer unit 34 also contains some circuitry for accomplishing the initial equalizer setting, as will be further detailed below.

The microprocessor structure of FIG. 3 is conventional, and includes a program store 16, a program counter 18, for addressing the program store 16, a command decoder 14 for decoding instructions from the program store 16 to produce control signals and an arithmetic unit 22 for performing the instructions in response to the control signals from the decoder 14. The microprocessor structure also includes a data storage memory 26 and an address decoder 24 for addressing the memory. The program store 16 is a conventional read only memory (ROM) of sufficient capacity to store the instructions for performing the equalizer operations to be described below and may be constructed from four AMD 9216 ROM chips. The program counter 18 is a conventional counter which can be loaded or jumped as necessary in response to control signals from the command decoder 14. The arithmetic unit 22 is also conventional in structure and of sufficient power to carry out necessary operations as hereafter described. The data storage memory 26 includes storage for constants and 256 words of random access memory and may be configured from three AM91L12ADC RAM chips and one General Instrument R03-5120 chip. The random access storage is used to store incoming samples of the impulse response 17 and subsequent data 20 while calculations are underway.

The apparatus of FIG. 3 just described performs rapid initial equalization by calculating the initial equalizer tap multiplier constants in very rapid fashion. The manner of this calculation and the function and structure of the apparatus of FIG. 3 will now be explained in detail.

The multiplier constants to be calculated are labeled c_p1, c_p2, c_p3 . . . c_pi and c_q1, c_q2, c_q3 . . . c_qi (see FIG. 2). In complex form the equalizer tap constants may be expressed as:

ci =cpi +jcqi , i=1, 2, 3, . . . n

To calculate the equalizer constants c_i from the pair of demodulated impulse responses as shown in FIGS. 1B and 1C, the following definitions are adopted: ##EQU1## The following elements are defined: ##EQU2## In the above equations (1)-(6), X_m and Y_m are the m-th sample of the in-phase and quadrature phase of the impulse response used for calculating the autocorrelation and cross correlation. Equations, (2), (3), (4) represent the auto-correlation and cross-correlation of the samples X_m and Y_m.

In the above equations 1-6, M is the total number of samples used for calculating the auto-correlation and cross-correlation and n is equal to the number of taps, twenty for M and sixteen for n in the preferred embodiment, and q equals the subscript of the first sample actually used to calculate h_k. The variable q accounts for the fact that in the preferred embodiment not all samples taken are used, in other words n is less than M as later explained in detail. If n equals M, q=1.

With these definitions, the equations defining the optimum tap constants c₁, c₂, . . . c_n for an equalizer of n taps is written as follows in matrix form: ##EQU3## In equation (7), r₁ . . . r_i and h₁ . . . h_n are complex constants while c₁ . . . c_n are complex variables. The asterisk (*) indicates the complex conjugate form.

According to the invention, a special solution of this equation (7) permits a precise iterative calculation of the tap constants c₁ . . . c_i within the time interval required by the training scheme of FIG. 1 plus the time delay required for data to propagate between the input and output of the equalizer. According to this solution, the following definitions are made:

e1 =1-|r1 |2              (8)

Where |r₁ | represents the magnitude of the complex quantity r₁ ;

s1.sup.(1) =-r1                                  (9)

Where superscript "(1)" indicates the first iteration i=1; and

c1.sup.(1) =h1                                   (10)

Adapting these definitions, the exact iterative solution for the tap constants is as follows: ##EQU4## The superscripts again indicate the value of the variable for a particular iteration. These equations 7-16 provide a simple means for rapidly and exactly calculating the tap constants c_i in the complex matrix equation (7). This iterative technique enables the apparatus of the invention to calculate the constants c_i and set the equalizer to achieve initial equalization during a total training time of approximately 30 milliseconds from the beginning of carrier-only to the first bit of customer data in a 2400 baud machine. Variations of the matrix equation (7) may be written and solved by the technique illustrated above without departing from the scope of this invention.

The structure and operation of the apparatus of FIG. 3, as it relates to the preferred embodiment of the invention, will now be described in further detail in conjunction with FIGS. 4-8.

After the carrier is detected and the clock KSTMX is started, the system operates according to the flow illustrated in the flow chart of FIG. 4. The flow of FIG. 4 illustrates accomplishment of the automatic gain control function, filter, demodulation, the detecting of the training pattern present (TPP) and calculation of the optimum sampling point to be used in the subsequent operations of FIG. 7. Two samples of the carrier-only signal are processed each baud for the eight bauds of carrier-only 11. A counter N is set up at -8 to direct operation.

As long as N is less than zero, the left branch 43 of the flow is followed and each sample is subjected to an automatic gain control operation 47, a filter and demodulation operation 49 and the test pattern present detection 51. The test pattern detection checks six successive bauds of carrier-only signal and thereafter sets a flag indicating that a test pattern is in fact being received. Each baud, the counter N is incremented by one, as is the counter KSTMX.

When N equals zero, the clock-only signal 13 begins. The AGC is frozen and the right hand branch 53 of the flow of FIG. 4 is entered. In this branch 53, a filter and demodulation operation 55 is performed and a test 57 of the TPP flag is made. Assuming TPP has been detected and the TPP flag set, the fast learn clock operation 59 is performed. During this operation, denoted FLCLK, the apparatus calculates the optimum sampling point for the forthcoming impulse based on the demodulated clock-only information. After each two samples per baud have been demodulated and used in the FLCLK process, the counter KSTMX is incremented by one, as is the N counter. When FLCLK is done, the flow proceeds to FIG. 7.

The manner in which the training pattern detection is performed is illustrated in more detail in FIG. 5. Referring to FIG. 5, X and Y samples of the demodulated baseband signal are supplied to respective inputs at the rate of two samples per baud.

The samples presented to the X input are operated upon as follows. Each sample is first squared by a multiplier 63 and the output of the multiplier 63 is stored for one sample time in a delay element 65. The current output of the multiplier 63 is added to the negative value of the previous output of the multiplier 63 in an adder 67. The output of the adder 67 is supplied as one input to a second adder 69. The X input is also supplied to a second one sample time delay element 71. The output of the second one-sample delay element 71 is supplied to a second multiplier 73, also supplied with the X input, such that the current X input sample is multiplied by the immediately preceding X sample. The output of the second multiplier 73 is fed to one input of a third summer 75.

The Y input is similarly operated on. A delay element 77 delays the first sample of the Y input and a multiplier 79 multiplies the first sample of the Y input by the delayed sample for supply to the third summer 75. The Y input is also squared and the squared Y input value is supplied to a delay element 81. The delayed squared sample is subtracted from a present squared sample by a summer 83 whose output is supplied to the second summer 69.

The output of the third summer 75 is multiplied by two at a multiplier 85 to form an output denoted ACK. The output of the second summer 69 is denoted BCK. The arc tangent of ACK/BCK is then taken to determine the sampling angle θ_n. The current value of θ_n is stored by a delay element 87. The stored value of θ_n is used in the clock preset to be subsequently discussed.

It is then determined whether θ_n is within bounds for each of a number of counts NTPP. When NTPP is greater than 10, five bauds of samples have been examined. Thus, if |θ_n -90°| is less than 15 continuously for greater than 10 NTPP counts, it is confirmed that carrier has been received for 5 bauds, and the TPP flag is therefore set equal to 1. This operation is illustrated in FIG. 5 by proceeding through blocks 91, 92, 93, to block 94, TPP equals 1. Once |θ_n -90°| is greater than 15° and TPP equals 1, the clock preset routine is entered.

In the event, however, that |θ_n -90°| is greater than 15° on any of the carrier-only samples operated on, the test block 95, TPP=1, will not be satisfied, and NTPP will be reset to zero. In such event, if KSTMX is greater than 19, indicating nineteen bauds have occurred without detecting TPP, TPP not present is indicated. Failure to detect TPP normally indicates line dropout.

Once the training pattern is detected, it is necessary to properly align the timing of the sampling of the received impulse response 17. The sampling points are calculated such that the equalizer can best minimize the output error. The structure and technique used in the preferred embodiment for performing the presetting of the sampling clock (FLCLK) is illustrated in detail in FIG. 6.

Assuming no distortion or noise, the difference between successive angles θ_n should be 180°. Therefore, if the magnitude

φ=||θn -θn-1 |-180°|

is less than 12° for several successive samples, the clock is in good range. Assuming that θ_n is in good range over several sampling intervals of the clock-only pattern, the loop including blocks 101, 102, 103, 104, 105, 106, and 107 in FIG. 6 is operative. Initially, three counters NCNT, NSAMP, and NAV are set to zero. When the first sample is tested, the sampling counter NSAMP is incremented by 1 as indicated by the block 101. The angle φ is then tested, and if it is within range, the counter NCNT is incremented by 1. After four consecutive good samples, the test, NCNT greater than or equal to four (Block 104), is satisfied, and NAV=0 is satisfied. In this event, the test indicated by block 106 is performed to ascertain whether the magnitude of θ_n is less than 90°. If so, a counter NR is set equal to 1. The counter NAV, representing the number to be averaged, is set equal to 1 and TAGL (total angle) is defined as equal to θ_n at this moment. The next time around the loop, the test NAV=0 is not true, and NR is incremented by one at block 108. NR+1 is then equal to two. NR is then not odd, and another sample is taken. After this sample, assuming φ is still in bounds, NR is odd (equal to 3). Therefore, the number averaged NAV+1=2 and TAGL is equal to the previous θ_n value plus the new θ_n value. Thus there are two angles to be averaged. Assuming that θ_n continues to be within bounds, the number of θ_n samples averaged is incremented to 4 and then the angle P.sub.θ is determined at block 109 by calculating the quotient of TAGL and NAV. P.sub.θ indicates the number of degrees from which the sampling point being used diverges from the optimum sampling point. Thus, it takes 10 angle differences within bounds to reach the block P.sub.θ =TAGL/NAV.

In the event, however, that distortion is occurring, other provisions are made for calculating P.sub.θ. For example, if it occurs that φ is greater than 12, satisfying block 102, a test 110 is made to determine if the number of good samples counted NCNT is greater than or equal to 4, i.e. whether four in-bounds angle tests have occurred. If so, a test 111 is made of the NAV counter to determine whether any samples TAGL have been stored for averaging. If any samples have been stored, the average θ_av =TAGL/NAVL is computed as indicated by the four blocks 112, 113, 114, 115. These four blocks indicate that P.sub.θ is taken as equal to θ_av if NR is even, whereas P.sub.θ is taken as equal to

[SGN(θav)][180°-|θav |]

if NR is odd. If, however, at the test 111, NAV is found to be equal to zero, indicating no samples θ_n have been accumulated, P.sub.θ is taken to be the current sample θ_n.

If the NCNT≧4 test 110 is not satisfied, a test 117 of the number of samples, indicated by counter NSAMP, is made. If that number NSAMP is greater than 29 (>14 bauds), P.sub.θ is again taken to be θ_n. If NCNT≧4 is not satisfied and NSAMP≧29 is not satisfied, NCNT is set to zero and another sample is examined. This procedure assures that if the angle determination is initially or occasionally out of bounds, subsequent angles can be examined to average the clock according to the previously discussed procedures.

P.sub.θ then determines the phase shift of the impulse sampling clock to be used in the matrix sampling operation illustrated in FIG. 7.

In FIG. 7, the first time through, the new program (NP) test 121 is positive and the left branch 123 of the flow is followed. Here the equalizer random access memory (RAM) 26 is reset. Also the optimum sampling point determined by FLCLK is used to jump the sampling clock to the optimum sampling position within each baud. The clock rate is reduced in half to 2400 Hz such that one sample per baud of the impulse response is taken from each of the X and Y channels.

The second time through the flow of FIG. 7, a second branch 125 is followed. Detected samples are demodulated (block 127), and then a test 129 is performed on KSTMX to see if it is greater than 45. If it is not, KSTMX is incremented (block 131). As soon as KSTMX is greater than 45, matrix formation 133 from the sampled impulse 17 begins.

The branch followed when KSTMX≦45 includes a demodulated output energy test which assures that the system is receiving the equalizer test pattern and not customer data. After KSTMX is greater than 38 the energy is determined as denoted by blocks 134, 138. If the energy is below a set level E_ref, the squelch period is assumed to have been detected and the system knows a training pattern is present. If the energy is greater than E_ref, training pattern TPP not present is indicated. This provides a double check on the presence of a training pattern.

Sampling of the impulse wave form 17 is illustrated by the vertical lines in FIG. 1B and 1C. The number of samples is counted by a counter K, started when KSTMX=45. Each sample produces an X component x_i and a Y component y_i. As the samples x_i, y_i are successively taken, formation of the matrix equation (7) according to the definitional equations (1), (2), (3), (4) begins. For example, during the first baud, x₁ and y₁ are taken and stored in the RAM 25 and may then be used to calculate x₁ ² +y₁ ², the first iteration of rT₀, equation (1). During the second and successive samples, iterations of rT₀ and the correlating equations rT₁, rT₂ . . . are calculated.

As the second sample x₂, y₂ is taken, it is stored in the RAM 26, and the square of its magnitude, X₂ ² +y₂ ² is compared to the square of the first sample magnitude x₁ ² +y₁ ² to determine which is larger. The larger is retained and compared to the square of the magnitude of the next sample to determine the largest sample and hence the peak 180 of the sampled impulse response 17. The baud KP during which the peak 180 occurs is stored to be used in subsequent operations. All samples x_i, y_i are also stored.

Sampling is terminated upon one of two conditions as indicated by a test 137 (FIG. 7). For the application of the preferred embodiment, it is advantageous to use eight samples before the peak and eleven after the peak. If eleven samples have occurred after the peak, K=KP+11, and matrix formation is terminated. If K<8, KP is set equal to eight (blocks 135, 136) so that at least nineteen samples must be taken before formation can be terminated upon K=KP+11. Otherwise, once twenty-four total samples have been taken, matrix formation is terminated and a flag is set.

Once the matrix flag is set, the next time through the flow, a branch 132 occurs to the test 141, K>20 (FIG. 8). If greater than 20 samples have been taken, the test 141 is satisfied, and the processor 23 proceeds to correct the effect on the matrix of taking too many samples.

Thus, K>20 indicates that, because of the rough alignment of the counter KSTMX, too many samples before the occurrence of the peak 18 have been taken. These samples will likely contribute to inaccuracies and their effect is subtracted by an operation 143 denoted SUB 1. This subtraction is accomplished by taking the first samples x₁, y₁ from memory, calculating their impact upon the values for the equations (1), (2), (3) for rT₀, rT₁, rT₂, etc. and subtracting that impact. After the effect of the first sample x₁, y₁ is subtracted the sample counter K is decremented by one (block 145) and the K>20 test 141 is again performed. If the test 141 is satisfied, the effect of the second sample pair x₂, y₂ is calculated and subtracted, etc. until K≦20. Once K≦20, the values determined by the remaining samples x₁, y_i are utilized in the subsequent matrix calculations.

Once K is reduced to 20, a branch 147 occurs to the tap constant calculation process, equations (5)-(6) and (8)-(16), first passing through a test 149 to determine if the calculation has already been done. At the beginning of the calculation process, a counter N is set to zero. A test 151 of the value of N is then made.

The first step 153 in the calculation process, with N equal to zero, is a normalization process. During this step, the r_i 's and h_k 's of equations (4) and (5) are calculated by the microprocessor structure of FIG. 3.

The next time through branch 147, with N equal to 1 (block 155), the microprocessor develops the equalization constants c_i by calculating successive iterations of the equations (11) (12) (13) (14) (15) (16), previously discussed.

With N=2, the microprocessor structure of FIG. 3 begins to interact with the equalizer unit 34 in the following manner. The microprocessor calculates equations (11) and (12) and then transfer the "r" matrix (equation 7) and other intermediate calculation results to the equalizer unit 34. In this manner, the microprocessor shifts part of the calculation responsibility to the equalizer unit 34 in order to free the processor to handle other operations on the incoming data. The equalizer unit 34 contains hard wired logic which performs or calculates the subsequent iterations of equations (11) through (14). For N=2, the equalizer only calculates equations (13) and (14). At the end of each calculation of an iteration of equations (11) through (14) in the equalizer unit 34, (13 and 14 only for N=2) the processor calculates the quantity z_i +1, equations (15) and (16), and returns that value to the equalizer 34 for performance of the next iteration of equations (11) through (14). This allocation of calculation between microprocessor and equalizer unit is merely due to a desire to efficiently utilize the apparatus. As is apparent, the assignment of the calculations of equations (11) through (14) to circuitry associated schematically with the equalizer unit 34 is one approach to calculating the instant equalizer settings. Other approaches such as utilization of a more powerful microprocessor to do all calculations could be implemented according to the subject invention.

When N is equal to 15, the matrix has been solved for the tap constants c_k and the iteration done flag is set. When the final tap constants are calculated, the h_k 's are stored and the final equalizer constants c_i determined according to the just described procedure are set.

The just discussed operation is sufficient to set 16 taps. If the line signal is of such a poor quality that additional taps are needed, a fine tuning procedure may be performed in which additional bauds of known two phase data are sent and the error difference detected and used to adjust the additional taps according to conventional procedures.

As is indicated in the above discussion, many modifications and adaptations of the preferred embodiment are possible without departing from the scope and spirit of the invention.

For example, as illustrated in FIGS. 9, 10, and 11 the in-phase and quadrature-phase signals used by the equalizer of the invention may be derived other than at baseband and in systems using various demodulation schemes.

FIG. 9 illustrates a simple quadrature demodulation technique wherein baseband signals x(t) and y(t) constitute the in-phase and quadrature-phase signals. In FIG. 9, the received signal on an input line 201 is fed to first and second mixers 203, 205 wherein the line signal is mixed with respective signals cos ω_c t and -sin ω_c t where ω_c is the carrier frequency. The components are then filtered by respective baseband filters 207, 209 to yield the baseband quadrature components x(t) and y(t).

In FIG. 10, the received signal is fed to a first passband filter 211 having an impulse response h(t) and to a second passband filter 213 having an impulse response h(t), which is the Hilbert transform of the impulse response h(t) of the first filter 211. The respective outputs h(t), h(t) of the filters 211, 213 are at passband frequency and constitute in-phase and quadrature-phase signals which could be sampled by the equalizer of the subject invention.

In FIG. 11, an output h(t) of the filter 211 is fed to a first mixer 215 and to a fourth mixer 221. The output h(t) of the filter 213 is fed to a second mixer 217 and to a third mixer 219. The four mixers 215, 217, 219, 221 receive respective second inputs of cos ω_c t, sin ω_c t, cos ω_c t, sin ω_c t, where ω_c is the carrier frequency. The outputs of the first and second mixers 215, 217 are then summed by a summer 218 to give the demodulated baseband signal x(t). The output of the fourth mixer 221 is subtracted from the output of the third mixer 219 at a summer 220 to give the demodulated baseband signal y(t). In FIG. 11, x(t) and y(t) are in-phase and quadrature-phase signals which can also be sampled according to the invention to accomplish initial setting of the equalizer taps.

Therefore, it is to be understood that, within the scope of the appended claims, the invention may be practiced other than as specifically described herein.