OUTPUT BUFFER CIRCUIT FOR CMOS INTEGRATED CIRCUIT
专利汇可以提供OUTPUT BUFFER CIRCUIT FOR CMOS INTEGRATED CIRCUIT专利检索，专利查询，专利分析的服务。并且Two P-type wells (22a, 22b) are formed in an isolated way in the surface of an N-type semiconductor substrate (1), in each of which an enhancement type N-channel MOS transistor is formed. The two transistors are connected across a higher voltage source (V u) and a lower voltage source (V u) in series, with using the series connection point therebetween as an output terminal (OUT). Gate terminals (27a, 27b) of the two transistors are applied with input signals (IN, IN) of opposite levels, respectively. The P-type well (22b), in which the transistor connected with the higher voltage source (V u) is formed, is connected with the output terminal (OUT) and the P-type well (22a), in which the transistor connected with the lower voltage source (V u) is formed, is connected with the lower voltage source (V u), so that both of them are utilized as an output buffer circuit for a CMOS integrated circuit. The circuit of the invention can be used as an output buffer circuit for a CMOS (Complementary Metal Oxide Semiconductor) integrated circuit and enables to make higher integration and to increase the output.，下面是OUTPUT BUFFER CIRCUIT FOR CMOS INTEGRATED CIRCUIT专利的具体信息内容。
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