BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to a high performance sense amplifier that is fabricated from complementary metal oxide semiconductor (CMOS) devices and is suitable for sensing, reading, or writing amplifier applications with large scale integrated semiconductor memories, and the like.

2. Statement of the Prior Art

As is known to those skilled in the art, some of the primary performance characteristics that must be ideally optimized in a sense amplifier that is utilized in conjunction with a high capacity and medium or high performance memory include increased sensitivity, speed, and noise immunity and decreased space and power consumption. The conventional sense amplifier approach generally comprises a differential type amplifier with flip-flop type operation. Typically, the conventional sense amplifier is characterized by medium speed, sensitivity, and power dissipation.

While the prior art differential amplifier could be modified to improve the sensitivity, the gain and the speed of operation, the number and/or the size of the component devices thereof, and the corresponding power dissipation typically increases. In addition, the prior art differential amplifier is not adapted to tolerate non-symmetrical parameters or load on its two sides.

Some of the other problems inherent in the fabrication of the sense amplifiers of the prior art include the following. The desired precharge voltage does not match with the high gain area of the sense amplifier. That is, the precharge voltage is defined by the logical "0" and "1" signal levels occurring within a selected memory cell, by the threshold voltages of the transmission devices, by the different charge couplings and leakage currents, by capacitive and resistive load non-symmetricity, and by the offset voltage of the sense amplifier. However, the location of the high gain area of the sense amplifier is otherwise dependent upon the width-to-length ratio, the threshold voltage, the leakage current, the body effect factor, and the gain factor of the individual MOS devices which comprise the sense amplifier.

What is more, the differential type amplifiers of the prior art and the MOS devices associated therewith cannot tolerate any non-symmetrical changes in the structure of the component devices, the threshold voltages, and the parasitic capacitances, resistances and leakages, such as those caused by either device processing or by a nuclear radiation event. Any deviation from the ideal symmetrical case degrades performance rapidly and usually is accompanied by error or malfunction. More particularly, exposure of a conventional sense amplifier to a nuclear radiation event may result in both permanent degradation of MOS component parameters as well as a temporary upsetting of the sense amplifier operation. Permanent degradation in the characteristics of the semiconductor components which comprise the sense amplifier is typically caused by ionizing and neutron radiation effects. A permanent degradation in component characteristics may result in a shifting (i.e. an increase or decrease) in the threshold potentials of complementary semiconductor devices, an increase in leakage current, and a decrease in gain. The shifting of component characteristics (i.e. electrical parameters) varies with each individual component device and depends upon the voltage bias of the device electrodes that occurs during the time of radiation exposure. Additionally, temporary upsets induced by high energy, short term radiation exposure with rapid anneal effects from a nuclear event may result in momentary shifts in the parameters of the MOS components, which parameters return approximately to original parameter levels. Such rapid anneal effects are common when the sense amplifier is exposed to a large dose from x-rays, or gamma rays. The transient radiation temporarily causes extremely high leakage, transient shifts in the threshold voltages, as well as degradation in gain factor and in other parameters of the components which comprise the sense amplifier. As the rapid anneal effects dissipate with time, the parameters of the components subsequently and approximately recover to the level of permanent degradation.

The following patents show examples of prior art sensing arrangements:

U.S. Pat. No. 4,003,035 Jan. 11, 1977;

U.S. Pat. No. 4,003,034 Jan. 11, 1977;

U.S. Pat. No. 3,959,781 May 25, 1976,

U.S. Pat. No. 3,909,739 Sept. 30, 1975.

However, none of the aforementioned patents discloses a CMOS sense amplifier comprising first and second cross-coupled inverter-amplifier stages having series or parallel connected compensating components which automatically compensate for the effects of electrical parameter non-uniformities that may occur as a result of MOS device processing or exposure to a radiation event. Moreover, none of the aforementioned patents shows a sense amplifier which utilizes the body effect (such as that available in a MOS transistor device fabricated by silicon on sapphire techniques) to achieve self-compensation, as provided by some of the embodiments of the present invention.

SUMMARY OF THE INVENTION

Briefly, and in general terms, a high performance sense amplifier is disclosed that, in a preferred embodiment, is fabricated from complementary metal oxide semiconductor (CMOS) field effect transistors (FETs) with silicon on sapphire (SOS) technology. In one embodiment of the present invention, the sense amplifier is comprised of first and second complementary pairs of series connected p and n-channel FETs forming cross-connected inverter-amplifier stages with or without feedback. The source electrodes of the p-channel FETs that comprise the inverter-amplifiers are connected together at an electrical junction. Another p-channel FET is connected between this electrical junction and a source of relatively positive source voltage. The gate electrode of the additional p-channel FET is supplied with a clock control signal. The source electrodes of the n-channel FETs that comprise the inverter-amplifiers are also connected together at an electrical junction. Another n-channel FET is connected between this last mentioned electrical junction and a source of relatively negative source voltage. The gate electrode of the additional n-channel FET is also supplied with a clock control signal. By virtue of the present invention, the sense amplifier achieves high sensitivity, high gain, optimum noise immunity, and low power dissipation, inasmuch as the complementary field effect transistor pairs operate with the sum of their respective drain-source voltages equal to the sum of the threshold voltages of a pair of complementary field effect transistors.

In another embodiment of the present invention, a self-compensating sense amplifier is provided which automatically compensates for geometrical non-uniformities that may occur as a result of MOS device processing or from exposure to a nuclear radiation event. Self-compensation is achieved by arranging either series or parallel connected compensating elements (resistors, FETs, and the like) with the first and second pairs of complementary series connected field effect transistors so as to automatically control the respective drain currents in each of the first and second transistor pairs. Moreover, self-compensation may also be achieved by utilizing the body effect on MOS device threshold voltages by fabricating both the complementary transistor pairs and the compensating elements with silicon on sapphire techniques, or the like.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a high performance CMOS sense amplifier formed in accordance with the present invention.

FIGS. 2-8 each show a high performance, self-compensating CMOS sense amplifier formed in accordance with another embodiment of the present invention.

FIGS. 9-11 each show a CMOS sense amplifier that utilizes the body effect on field effect transistor device threshold voltage to automatically compensate for non-uniformities occurring as a result of device processing or exposure to a nuclear radiation event.

DESCRIPTION OF THE PREFERRED EMBODIMENT

FIG. 1 of the drawings shows a preferred embodiment of a complementary metal oxide semiconductor (CMOS) sense amplifier 2 with maximized signal sensitivity, speed, noise immunity, and gain and minimized size and power dissipation. In accordance with the present invention, the sense amplifier 1 is formed by first and second cross-coupled inverting amplifier stages 2 and 4. Inverter-amplifier stage 2 is comprised of a pair of series connected field effect transistors (FETs) Q₂ and Q₃. Inverter-amplifier stage 4 is comprised of a pair of series connected field effect transistors (FETs) Q₄ and Q₅. Each of the gate electrodes of FETs Q₂ and Q₃ are connected together at a first electrical junction and input terminal 6 formed between the series connected conduction paths of FETs Q₄ and Q₅. Each of the gate electrodes of FETs Q₄ and Q₅ are connected together at a second electrical junction and input terminal 8 formed between the series connected conduction paths of FETs Q₂ and Q₃ so that the cross-coupled inverter stages 2 and 4 provide feedback signals to one another. The series connected conduction paths of FETs Q₂ and Q₃ are connected in electrical parallel with the series connected conduction paths of FETs Q₄ and Q₅ between a pair of electrical junctions 10 and 12.

A first FET Q₁ is connected between a source of relatively positive supply voltage V_DD and the electrical junction 10. The gate electrode of FET Q₁ is connected to a clock terminal means 14 to receive a first clock signal φ. A second FET Q₆ is connected between electrical junction 12 and a source of relatively negative supply voltage V_SS, such as, for example, ground. The gate electrode of FET Q₆ is connected to a clock terminal means 16 to receive a second clock signal φ. The first and second clock signals may be complements of one another. FETs Q₁ and Q₆ are rendered conducting by the respective clock signals φ and φ so as to clamp electrical junctions 10 and 12, with suitable varying resistance, to one of the supply voltages V_DD or V_SS. In a preferred embodiment, FETs Q₁, Q₂, and Q₄ are p-channel transistor devices, while FETs Q₃, Q₅, and Q₆ are n-channel transistor devices. Moreover, for minimizing voltage and current offset, FETs Q₂ and Q₄ as well as Q₃ and Q₅ are identically sized devices.

To separate the presently disclosed sense amplifier 1 from any one of a plurality of memory cells 20 comprising a suitable array thereof or to precharge input terminals 6 and 8 independently from the data bus lines, well known coupling means are connected between the sense amplifier 1 and a pair of the data bus lines. More particularly, a first coupling transistor means 17 is connected between the input electrical junction 8 and a BIT data bus line. A second coupling means 18 is connected between the input electrical junction 6 and an opposite state BIT data bus line. By way of example, coupling transistor means 17 and 18 may each comprise a pair of complementary field effect transistors having their respective conduction paths connected in electrical parallel with one another between a sense amplifier input terminal 6 or 8 and a corresponding data bus line. However, the coupling transistor means 17 and 18 may also be fabricated from single devices or, depending on the memory organization, they may be eliminated entirely. The conductivity of each of the pair of coupling transistors is controlled by the clock signals φ and φ applied to the respective gate electrodes thereof. The presently disclosed sense amplifier 1 may be interfaced with an array of memory cells 20 via the BIT and BIT data bus lines in any well known configurations, such as a row amplifier arrangement, a pipe lined amplifier arrangement, or the like.

The operation of the presently disclosed CMOS sense amplifier 1 having optimized performance is described as follows. During the start of operation, disabling clock control signals φ and φ are supplied from clock terminal means 14 and 16 to the respective gate electrodes of FETs Q₁ and Q₆, and FETs Q₁ and Q₆ are rendered non-conducting. Although the electrical potentials applied to electrical junctions 10 and 12 are floating, the voltage of electrical junction 10 is nearly that of the V_DD supply voltage, and the voltage of electrical junction 12 is nearly that of the V_SS supply voltage. Precharge voltages more positive than the sum of the V_SS supply voltage and the threshold voltage drop of an n-channel FET and more negative than the difference between V_DD supply voltage and the threshold voltage drop of a p-channel FET are respectively applied to each of the electrical junctions 6 and 8 and to the gate electrodes of FETs Q₂, Q₃, Q₄ and Q₅ so as to render conducting each of FETs Q₂ -Q₅. After developing the proper precharge voltages, the voltage at electrical junction 10 is equivalent to the sum of the precharge voltage plus the threshold voltage drop V_tp of the p-channel FET Q₂. The voltage at electrical junction 12 is equivalent to the difference between the precharge voltage and the threshold voltage drop V_tn of the n-channel FET Q₅. Therefore, the voltage difference between electrical junctions 10 and 12 is equivalent to the sum of the threshold voltage drops of the p-channel FET Q₂ (or Q₄) and the n-channel FET Q₅ (or Q₃), i.e.: |V_tp |+V_tn, which, thereby, automatically results in a nearly rectangular function of input-output transfer characteristics regardless of the size of the amplifier component devices and automatically places the initial operating point into the center of this rectangular function regardless of varying device parameters, temperature, supply voltage, or radiation effects. Thus, the sense amplifier 1 begins to work automatically at the optimum operating point where the highest sensitivity, highest gain, best noise immunity, and lowest power dissipation of any amplifier can be achieved whenever FETs Q₁ and Q₆ are rendered conducting by the φ and φ clock signals.

When a particular memory cell 20 from the array thereof is selectively accessed, the potentials at electrical junctions 6 and 8 are respectively increased and decreased, or vice versa, in accordance with the information stored in the selected memory cell. After the selected memory cell 20 is accessed, FETs Q₁ and Q₆ are relatively slowly rendered conducting. During this slow conduction of FETs Q₁ and Q₆, the sense amplifier works close to the initial ideal operating point. However, after the proper potential difference has been achieved between electrical junctions 6 and 8, high sense amplifier sensitivity is no longer critical, and the clock signals φ and φ that are supplied to the gate electrodes of FETs Q₁ and Q₆ cause FETs Q₁ and Q₆ to be rendered fully conducting to thereby provide to the electrical junctions 6 and 8, in a relatively short time, a maximum logic "1" signal level (that is equivalent to the V_DD supply voltage) and a minimum logic "0" signal level (that is equivalent to the V_SS supply voltage). Unlike those sense amplifiers of the prior art, because of the nearly ideal transfer characteristics and the automatic ideal operating point adjustment, the present sense amplifier 1 is characterized by small integrable size, while achieving optimum performance for sensitivity, gain, noise immunity, and power dissipation. However, the sense amplifier 1 remains responsive to the non-symmetricity of devices, load, or parasitic effects on either of the two cross-coupled inverter-amplifier stages 2 and 4.

Immunity from non-uniformities as a result of device processing or from imbalances caused by exposure to a nuclear radiation event is provided by arranging MOS devices, according to the following embodiments of the present invention, so as to form sense amplifier configurations which automatically compensate for the undesirable effects of non-symmetry and for degradation in the characteristics of the semiconductor components caused by ionizing radiation, neutron and transient annealing effects.

FIG. 2 shows a self-compensating CMOS sense circuit 21 that operates in the linear MOS region and has both read and write capabilities. The sense circuit 21 is identical to the sense circuit 1 of FIG. 1, except for the addition of compensating resistors R₁ -R₄. Referring to FIG. 2, resistor R₁ is connected in electrical series with FET Q₂ between electrical junctions 10 and 8. Resistor R₂ is connected in electrical series with FET Q₃ between electrical junctions 8 and 12. Resistor R₃ is connected in electrical series with FET Q₄ between electrical junctions 10 and 6. Resistor R₄ is connected in electrical series with FET Q₅ between electrical junctions 6 and 12.

In operation, resistors R₁ -R₄ enable the presently disclosed sense amplifier 21 to achieve high sensitivity relative to the level of the information signals on the BIT and BIT data bus lines by supplying individual compensation to the critical MOS devices (e.g. FETs Q₃ and Q₅) to prevent sense amplifier failure as an undesirable result of either temperature or radiation induced threshold voltage changes. The effective transconductance g_m ' of the sense amplifier 21 is represented by:

gm '=gm /(1+Rs gm),

where g_m depends upon transistor device parameters such as threshold voltages, mobility, geometry, etc. However, if R_s (e.g. R₁ -R₄)>>1, then g_m ' is approximately equal to 1/R_s, so that, by virtue of the present sense amplifier 21, g_m becomes virtually independent of the transistor device parameter changes.

In two similar self-compensating CMOS sense amplifiers 31 and 41, the compensating resistors R₁ -R₄ of FIG. 2 are replaced by compensating FET devices Q₁₁ -Q₁₄ that operate in the triode region, as illustrated in FIGS. 3 and 4. FETs Q₁₁ -Q₁₄ decrease the required silicon area while facilitating the utilization of a simplified process technique and decreasing the processing and masking strips. However, the radiation hardness of the sense amplifiers 31 and 41 is usually weaker, inasmuch as FET devices are more sensitive to radiation than are hardened resistors.

Each of the sense amplifiers 31 and 41 is identically comprised of the aforementioned four compensating FETs Q₁₁ -Q₁₄. Sense amplifier 31 also includes first and second cross-coupled inverter-amplifier stages 2 and 4, having cross-connected FETs Q₂ -Q₅, identical to that illustrated in FIG. 1. The sense amplifier 41 includes first and second inverter-amplifier stages 42 and 44, comprising respective pairs of series connected FETs Q₁₅, Q₁₆ and Q₁₇, Q₁₈, which FETs are not cross-connected so that no feedback signals are supplied to one another. Therefore, the sense amplifier 41 of FIG. 4 can be characterized as having a high input impedance, while providing inverted output signals at electrical junctions 46 and 48. Each of the gate electrodes of the compensating FETs Q₁₁ and Q₁₃ of both of the sense amplifiers 31 and 41 are connected together and to the clock terminal means to receive the φ clock signal. Moreover, each of the gate electrodes of the compensating FETs Q₁₂ and Q₁₄ of both of the sense amplifiers 31 and 41 are connected together and to the clock terminal means to receive the φ clock signal. An electrical junction between the series connected conduction paths of inverter-amplifier FETs Q₁₅ and Q₁₆ of sense amplifier 41 is connected together to form a first output. An electrical junction between the series connected conduction paths of inverter-amplifier FETs Q₁₇ and Q₁₈ of sense amplifier 41 is connected together to form a second output. The conduction path of a first additional FET Q₁ is connected between the relatively positive source of supply voltage V_DD and one conduction path electrode of each of the compensating FETs Q₁₁ and Q₁₃ of sense amplifiers 31 and 41. The gate electrode of FET Q₁ is connected to clock terminal means to receive the φ clock signal. The conduction path of a second additional FET Q₆ is connected between one conduction path electrode of each of the compensating FETs Q₁₂ and Q₁₄ of sense amplifiers 31 and 41 and the relatively negative source of supply voltage V_SS. The gate electrode of FET Q₆ is connected to clock terminal means to receive the φ clock signal. In a preferred embodiment, compensating FETs Q₁₁ and Q₁₃ are p-channel transistor devices, while compensating FETs Q₁₂ and Q₁₄ are n-channel transistor devices.

Another self-compensating CMOS sense amplifier 51 is illustrated in FIG. 5. The presently disclosed sense amplifier 51 includes a pair of cross-coupled inverter-amplifier stages 2 and 4, comprising FETs Q₂ -Q₅, as previously illustrated in FIG. 1, and four cross-connected compensating FETs Q₁₉ -Q₂₂. The conduction path of a first compensating FET Q₁₉ is connected between electrical junctions 52 and 56 and in electrical series with FET Q₂. The conduction path of a second compensating FET Q₂₁ is connected between electrical junctions 54 and 56 and in electrical series with FET Q₄. The gate electrodes of FETs Q₁₉ and Q₂₁ are cross-connected to electrical junctions 54 and 52, respectively. The conduction path of a third compensating FET Q₂₀ is connected between electrical junctions 53 and 58 and in electrical series with FET Q₃. The conduction path of a fourth compensating FET Q₂₂ is connected between electrical junctions 55 and 58 and in electrical series with FET Q₅. The gate electrodes of FETs Q₂₀ and Q₂₂ are cross-connected to electrical junctions 55 and 53, respectively. The conduction path of a first additional FET Q₁ is connected between the relatively positive source of supply voltage V_DD and the electrical junction 56. The gate electrode of the FET Q₁ is connected to clock terminal means to receive the φ clock signal. The conduction path of a second additional FET Q₆ is connected between the electrical junction 58 and the source of relatively negative supply voltage V_SS. The gate electrode of the FET Q₆ is connected to clock terminal means to receive the φ clock signal. In a preferred embodiment, FETs Q₁, Q₂, Q₄, Q₁₉, and Q₂₁ are p-channel transistor devices, and FETs Q₃, Q₅, Q₆, Q₂₀, and Q₂₂ are n-channel transistor devices.

The operation of the self-compensating sense amplifier 51 of FIG. 5 is briefly described as follows. Under ideal operating conditions, the respective drain currents in each of the cross-coupled inverter FETs Q₃ and Q₅ are identical. However, should an undesirable geometrical non-uniformity or an exposure to a radiation event cause an amplifier variation such as, for example, in the threshold potential, leakage current, or gain factor in one of the cross-coupled inverter-amplifier stages 2 or 4, the drain current of one of the first inverter FETs Q₃ exceeds the corresponding drain current of one of the second inverter FETs Q₅, inasmuch as the source-drain resistance of FET Q₃ becomes less than that of FET Q₅. Hence, the voltage at electrical junction 53 exceeds the corresponding voltage at electrical junction 55, and, as a result, FET Q₂₂ turns on harder than FET Q₂₀. Therefore, the source-drain resistance of FET Q₂₂ is effectively reduced relative to the source-drain resistance of FET Q₂₀, so that the voltage at electrical junction 55 is decreased and the voltage at electrical junction 53 is correspondingly increased. By virtue of the self-compensating sense amplifier 51, the sum of the source-drain resistances of the series connected FETs Q₃ and Q₂₀ approximates that of FETs Q₅ and Q₂₂, whereby the drain currents of FETs Q₃ and Q₅ are approximately equalized.

Another self-compensating CMOS sense amplifier 61 is illustrated in FIG. 6. Sense amplifier 61 is comprised of an arrangement of four compensating FETs Q₂₃, Q₂₄, Q₂₅ and Q₂₆. In addition to the compensating FETs Q₂₃ -Q₂₆, the conduction paths of a pair of FETs Q₂₇ and Q₂₈ are connected in electrical series with one another between electrical junctions 62 and 63. The conduction paths of another pair of FETs Q₂₉ and Q₃₀ are connected in electrical series with one another between electrical junctions 64 and 65. The respective gate electrodes of FETs Q₂₇ and Q₂₉ are connected together at the source of relatively negative supply voltage V_SS. The respective gate electrodes of FETs Q₂₈ and Q₃₀ are also connected together at the source of relatively negative supply voltage V_SS. Unlike the sense amplifier of FIG. 1, the gate electrodes of FETs Q₂₇ -Q₃₀ are not cross-connected relative to one another, so that the presently disclosed sense amplifier 61 operates without inverter feedback, with a high sense input impedance at input electrical junctions 6' and 8', and with a minimum number of transfer devices.

One conduction path electrode of a first compensating FET Q₂₃ is connected at the electrical junction 66. The second conduction path electrode of FET Q₂₃ and the gate electrode of a second compensating FET Q₂₅ are connected together at the electrical junction 62. One conduction path electrode of the compensating FET Q₂₅ is connected at the electrical junction 66. The second conduction path electrode of FET Q₂₅ and the gate electrode of compensating FET Q₂₃ are connected together at the electrical junction 64. A first additional FET Q₁ is connected between the electrical junction 66 and the source of relatively positive supply voltage V_DD. The gate electrode of FET Q₁ is connected to clock terminal means to receive the φ clock signal. In a preferred embodiment, FETs Q₁, Q₂₃, Q₂₅, Q₂₇, and Q₂₉ are p-channel transistor devices.

One conduction path electrode of a third compensating FET Q₂₄ is connected to the electrical junction 68. The second conduction path electrode of compensating FET Q₂₄ and the gate electrode of a fourth compensating FET Q₂₆ are connected together at the electrical junction 63. One conduction path electrode of compensating FET Q₂₆ is connected to the electrical junction 68. The second conduction path electrode of FET Q₂₆ and the gate electrode of FET Q₂₄ are connected together at the electrical junction 65. The conduction path of a second additional FET Q₆ is connected between electrical junction 68 and the source of relatively negative supply voltage V_SS. The gate electrode of FET Q₆ is connected to clock terminal means to receive the φ clock signal. In a preferred embodiment, FETs Q₆, Q₂₄, Q₂₆, Q₂₈, and Q₃₀ are n-channel transistor devices.

The operation of the self-compensating sense amplifier 61 of FIG. 6 is briefly described as follows. Under ideal operating conditions, the drain currents of each of FETs Q₂₈ and Q₃₀ are identical. However, should the drain current of FET Q₂₈ exceed that of FET Q₃₀ due to an unbalance, such as that caused by a device parameter nonuniformity or by a nuclear radiation event, the corresponding voltage at electrical junction 63 exceeds that at electrical junction 65. Hence, FET Q₂₆ turns on harder than FET Q₂₄, and, as a result, the sum of the source-drain resistances of the series connected FETs Q₃₀ and Q₂₆ approximates that of the series connected FETs Q₂₈ and Q₂₄. Therefore, by virtue of the disclosed self-compensating sense amplifier 61, the drain currents of each of FETs Q₂₈ and Q₃₀ are approximately equalized. What is more, maximized logic level "0" and "1" signals (i.e. V_DD and V_SS) can be generated by the sense amplifier 61 at electrical junctions 6' and 8', which signals are clearly distinguishable from one another.

Another form of the self-compensating CMOS sense amplifier configuration illustrated in FIG. 6 is that shown in FIG. 7. The sense amplifier 71 of FIG. 7 includes a pair of cross-coupled inverter-amplifier stages 2 and 4, comprising FETs Q₂ -Q₅ and an arrangement of four compensating FETs Q₃₁, Q₃₂, and Q₃₄ (identical to those illustrated in FIG. 5). One conduction path electrode of each of the compensating FETs Q₃₁ and Q₃₃ are connected together at an electrical junction 76. The gate electrode of compensating FET Q₃₁ is connected at an electrical junction 72 with the second conduction path electrode of compensating FET Q₃₃ and one conduction path electrode of FET Q₂. The second conduction path electrode of FET Q₃₁ is connected at an electrical junction 74 with the gate electrode of FET Q₃₃ and one conduction path electrode of FET Q₄. Thus, the conduction paths of FETs Q₃₁ and Q₄ and FETs Q₃₃ and Q₂ are connected in electrical series. One conduction path electrode of each of the compensating FETs Q₃₂ and Q₃₄ are connected together at an electrical junction 78. The second conduction path electrode of compensating FET Q₃₂ and the gate electrode of compensating FET Q₃₄ are connected together at an electrical junction 75 with one conduction path electrode of FET Q₅. The second conduction path electrode of FET Q₃₄ and the gate electrode of FET Q₃₂ are connected together at an electrical junction 73 with one conduction path electrode of FET Q₃. Thus, the conduction paths of FETs Q₃ and Q₃₄ and FETs Q₅ and Q₃₂ are connected in electrical series. The conduction path of the first additional FET Q₁ is connected between the source of relatively positive supply voltage V_DD and the electrical junction 76. The gate electrode of FET Q₁ is connected to clock terminal means to receive the φ clock signal. The conduction path of a second additional FET Q₆ is connected between the electrical junction 78 and the relatively negative source of supply voltage V_SS. The gate electrode of FET Q₆ is connected to clock terminal means to receive the φ clock signal. In a preferred embodiment, FETs Q₁, Q₂, Q₄, Q₃₁, and Q₃₃ are p-channel transistor devices, while FETs Q₃, Q₅, Q₆, Q₃₂, and Q₃₄ are n-channel transistor devices.

It is pointed out that while the mechanization and operation of the sense amplifier 71 of FIG. 7 are electrically identical to that of the sense amplifier 51 of FIG. 5, the sense amplifier 71 may have certain geometrical advantages. More particularly, on the silicon surface, each of FETs Q₂, Q₃, Q₃₁, and Q₃₂ is geometrically arranged on one side of symmetrical axis 79, and each of the FETs Q₄, Q₅, Q₃₃, and Q₃₄ is arranged on the other side of axis 79. This symmetrical arrangement of FET devices achieves a compensating effect during processing to account for misalignments from fabrication. For example, if the gain of a FET Q₅ is higher than that of Q₃ as a result of different channel widths, the gain of FET Q₃₄ is usually also higher than that of FET Q₃₂. Since FET Q₃ is connected in electrical series with FET Q₃₄ and FET Q₅ is connected in electrical series with FET Q₃₂, any resulting gain difference is minimized.

Another self-compensating CMOS sense amplifier 81 which compensates for the effects of processing, temperature and radiation induced parameter changes in MOS devices is illustrated in FIG. 8. Unlike those sense amplifiers illustrated in FIGS. 2-7 that include an arrangement of series connected compensating devices, FIG. 8 shows a sense amplifier 81 having parallel connected MOS compensating devices. More particularly, the disclosed self-compensating sense amplifier 81 includes first and second cross-coupled inverter-amplifier stages 2 and 4 comprising respective pairs of series connected FETs Q₂, Q₃ and Q₄, Q₅ identical to that illustrated in FIG. 1. The conduction path of a first compensating FET Q₃₅ is connected in electrical parallel with inverter FET Q₂ between electrical junctions 82 and 8. The conduction path of a second compensating FET Q₃₆ is connected in electrical parallel with inverter FET Q₃ between electrical junctions 8 and 84, whereby the conduction paths of compensating FETs Q₃₅ and Q₃₆ are connected in electrical series relative to one another. The gate electrodes of FETs Q₃₅ and Q₃₆ are connected together at electrical junction 8. The conduction path of a third compensating FET Q₃₇ is connected in electrical parallel with inverter FET Q₄ between electrical junctions 82 and 6. The conduction path of a fourth compensating FET Q₃₈ is connected in electrical parallel with inverter FET Q₅ between electrical junctions 6 and 84, whereby the conduction paths of compensating FETs Q₃₇ and Q₃₈ are connected in electrical series relative to one another. The gate electrodes of FETs Q₃₇ and Q₃₈ are connected together at electrical junction 6. In a preferred embodiment, FETs Q₃₅ and Q₃₇ are p-channel transistor devices, while FETs Q₃₆ and Q₃₈ are n-channel transistor devices. The conduction path of a first additional FET Q₁ is connected between the relatively positive source of supply voltage V_DD and the electrical junction 82. The gate electrode FET Q₁ is connected to clock terminal means to receive the φ clock signal. The conduction path of a second additional FET Q₆ is connected between the electrical junction 84 and the source of relatively negative supply voltage V_SS. The gate electrode of FET Q₆ is connected to clock terminal means to receive the φ clock signal. In operation, each cross-coupled inverter-amplifier stage 2 and 4 functions as a well known source follower to provide compensation for the logic level signals applied to the electrical junctions 6 and 8.

In another embodiment of the present invention, the body or back gate bias effect on MOS device threshold voltage is employed for self-compensation, as illustrated by the sense amplifier 91 in FIG. 9. The sense amplifier 91 is identical to that illustrated and previously disclosed when referring to FIG. 2, except that the respective floating body nodes (inherently formed between the conduction path electrodes and under the channel region of a MOSFET) of each of the p-channel FETs Q₁ ', Q₂ ', and Q₄ ' are connected to the relatively positive source of supply voltage V_DD. The respective body nodes of each of the n-channel FETs Q₃ ', Q₅ ', and Q₆ ' are connected to the relatively negative source of supply voltage V_SS. In a preferred embodiment, FETs Q₁ ', Q₂ ', Q₃ ', Q₄ ', Q₅ ', and Q₆ ' are each fabricated by conventional silicon on sapphire (SOS) techniques.

The operation of the self-compensating sense amplifier 91 of FIG. 9 is briefly described as follows. Under ideal operating conditions, the drain currents in each of FETs Q₃ ' and Q₅ ' are identical. However, should the drain current of FET Q₃ ' exceed that of FET Q₅ ' due to an unbalance, such as that caused by a parameter non-uniformity or by a nuclear radiation event, the corresponding source voltage of FET Q₃ ', is increased relative to that of FET Q₅ '. As a result, the difference between the source voltage of FET Q₃ ' and the source of negative supply voltage V_SS (which is connected to the body node of FET Q₃ ') is, accordingly, increased. Because of the well known body effect or back gate bias effect, the threshold voltage of FET Q₃ ' is also increased, thereby causing a decrease in the difference between the gate voltage and threshold voltage of FET Q₃ '. Hence, the drain current of FET Q₃ ' is diminished. What is more, due to similar, but opposing effects, the drain current of FET Q₅ ' is increased. Therefore, by virtue of the self-compensating sense amplifier 91, the drain currents of each of FETs Q₃ ' and Q₅ ' are approximately equalized. Moreover, the value of the resistors R₁ -R₄ is virtually independent of the radiation level that results from a nuclear event.

Another self-compensating sense amplifier configuration 101 that utilizes the body effect on MOS transistor device threshold voltages is shown in FIG. 10. The self-compensating sense amplifier 101 is identical to that illustrated and previously disclosed while referring to FIG. 6, except for the connections of the inherently formed body nodes of each of the MOSFETs. More particularly, the respective body nodes of p-channel FETs Q₁ ', Q₂₇ ', and Q₂₉ ' are each connected to the relatively positive source of supply voltage V_DD. The respective body nodes of each of the p-channel compensating FETs Q₂₃ ' and Q₂₅ ' could be connected together at electrical junction 66, as shown, or connected to the source of positive supply voltage V_DD when bulk CMOS fabrication techniques are employed. The respective body nodes of the n-channel FETs Q₆ ', Q₂₈ ', and Q₃₀ ' are connected to the relatively negative source of supply voltage V_SS. The respective body nodes of each of the n-channel compensating FETs Q₂₄ ' and Q₂₆ ' could be connected together at the electrical junction 68, as shown, or connected to the source of negative supply voltage V_SS when bulk CMOS fabrication techniques are employed. In a preferred embodiment, FETs Q₁ ', Q₆ ', Q₂₃ ', Q₂₄ ', Q₂₅ ', Q₂₆ ', Q₂₇ ', Q₂₈ ', Q₂₉ ', and Q₃₀ ' are each fabricated by conventional silicon on sapphire techniques.

The operation of the self-compensating sense amplifier 101 of FIG. 10 is briefly described as follows. The threshold voltages of MOSFET devices (e.g. FETs Q₂₈ ' and Q₃₀ ') depend upon the substrate (body) bias thereof, and, by changing the sourcebody voltage of these MOS devices, any current difference therethrough can be compensated by the respective body-source voltages. Under ideal operating conditions, the drain currents in each of FETs Q₂₈ ' and Q₃₀ ' are identical. However, should the drain current of FET Q₂₈ ' exceed that of Q₃₀ ' due to an unbalance, such as that caused by a nuclear radiation event, the corresponding voltage at electrical junction 63 exceeds that at electrical junction 65. As a result, the body-source voltage of FET Q₂₈ ' exceeds that of FET Q₃₀ ', and, accordingly, the source-drain resistance of FET Q₂₈ ' is increased, while the source-drain resistance of FET Q₃₀ ' is decreased. Hence, the sum of the resistance of the series connected FETs Q₂₈ ' and Q₂₄ ' approximates that of the series connected FETs Q₃₀ ' and Q₂₆ '. Therefore, by virtue of the self-compensating sense amplifier 101, the drain currents of each of FETs Q₂₈ ' and Q₃₀ ' are approximately equalized.

Another self-compensating sense amplifier configuration 111 that utilizes the body effect on MOS transistor device threshold voltages is shown in FIG. 11. The sense amplifier 111 is identical to that illustrated and disclosed when referring to FIG. 7, except for the connections of the inherently formed body nodes of each of the MOSFETs. More particularly, the respective body nodes of each of the p-channel FETs Q₁ ', Q₂ ', Q₄ ', Q₃₁ ', and Q₃₃ ' are connected to the relatively positive source of supply voltage V_DD. Moreover, the respective body nodes of each of the n-channel FETs Q₃ ', Q₅ ', Q₆ ', Q₃₂ ', and Q₃₄ ' are connected to the relatively negative source of supply voltage V_SS. In a preferred embodiment, each of FETs Q₁ ', Q₂ ', Q₃ ', Q₄ ', Q₅ ', Q₆ ', Q₃₁ ', Q₃₂ ', Q₃₃ ', and Q₃₄ ' is fabricated by conventional silicon on sapphire techniques. Inasmuch as the principle of operation of the sense amplifier 111 of FIG. 11 to compensate for undesirable unbalances is similar to that of the sense amplifier 101 illustrated in FIG. 10, a description of the operation of the self-compensating sense amplifier 111 is omitted.

It will be apparent that while a preferred embodiment of the invention has been shown and described, various changes and modifications may be made without departing from the true spirit and scope of the invention. For example, although the presently disclosed sense amplifiers are preferably fabricated from MOSFET devices, it is to be understood that either metal insulated semiconductor (MIS), junction field effect transistor (JFET), or bipolar devices may also be suitably employed to mechanize the instant sense amplifiers.