Circuit arrangement for the measuring of the maximal value of the distortion of a binary series of steps during an adjustable measuring period专利检索-定时信号发生器电子零件及设备专利检索查询-专利查询网

Circuit arrangement for the measuring of the maximal value of the distortion of a binary series of steps during an adjustable measuring period

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专利汇可以提供Circuit arrangement for the measuring of the maximal value of the distortion of a binary series of steps during an adjustable measuring period专利检索，专利查询，专利分析的服务。并且A circuit arrangement is described for measuring distortion values for binary signals. The arrangement measures a maximum value occurring in a preselected measuring period. A timing signal generator is arranged for producing, during an ideal duration of a step, a number of timing impulses corresponding to the distortion stages to be measured. A synchronizing device is arranged for classifying the incoming binary signal series of steps in a time frame. Timing impulses control the first counter which produces impulses having time differences corresponding to the aforementioned ideal signal length. The timing impulses control second and third counters, as well. The aforementioned three counters count in a phase locked relation to each other, and each counter counts once during the duration of an ideal step. Each counter has as many counting positions as there are distortion values to be measured. The second counter is returned to its starting position and the appearance of a measuring impulse, and this indicates leading distortion. For the duration of the phase difference between one of the counters and one of the remaining two counters, a gate is opened for switching through timing impulses to a measuring device. The number of timing impulses measured corresponds to the distortion value.，下面是Circuit arrangement for the measuring of the maximal value of the distortion of a binary series of steps during an adjustable measuring period专利的具体信息内容。

权利要求

1. Apparatus for measuring the maximum values of distortion of binary signals during an adjustable measuring period, the duration of said binary signals differring from an ideal duration, the appatatus comprising: timing signal generator means for producing clock pulses, input means for receiving said binary signals and for regenerating said binary signals, synchronizing means coupled to said timing signal generator and said input means for producing corrected clock pulses whereby ones of said corrected clock pulses will coincide with edges of said binary signals, first, second and third counting means controlled by said corrected clock pulses, said first counting means producing output signals at intervals corresponding to said ideal duration, each counting means being adapted to register one count cycle during said ideal duration and having as many counting positions as there are corrected clock pulses within said ideal duration, means for generating measurement pulses, said measurement pulses coinciding with edges of said received binary signals, first gate means for receiving said measurement pulses and for coupling same to reset inputs of said second counting means, second gate means for receiving said measurement pulses and for coupling same to reset inputs of said third counting means, means connecting an output of said first and said second counting means to an input of said first gate means, means connecting an output of said first and said third counting means to an input of said second gate means, whereby upon the occurrence of a leading distorted measurement pulse, there appears over said first gate means a reset signal for said second counting means, and upon the occurrence of a lagging distorted measurement pulse there appears over said second gate means a reset signal for said third counting means, fourth counting means for counting said corrected clock pulses and indicating a corresponding distortion value and fourth gating means having as inputs the outputs of said second and third counting means and said corrected clock pulses, said gating means being operable to connect said corrected clock pulses to said fourth counting means during the time said output signals of said second and third counting means are different.

2. The apparatus defined in claim 1 wherein said fourth gating means comprises fifth, sixth and seventh gating means, and including a measuring period gate generating means for establishing a period in which the maximum distortion shall be measured, wherein an output of said second counting means is applied to an input of said fifth gating means with said fifth gating means receiving as other inputs an output from said measuring period gate generating means and an output from said first counting means, an output from said third counting means is applied to an input of said sixth gating means which has as other inputs an output from said second counting means and an output fron said measuring period gate generator means, the outputs from said fifth and sixth gating means being applied to said seventh gating means which also receives as an input said corrected clock pulses, the output fron said seventh gating means being applied to said fourth counting means to count said distortion value.

3. The apparatus defined in claim 2 wherein said measuring period gate generator means derives said clock pulses fron said first counter means, and wherein said measuring period gate generator means has an output connected to a reset input of said second counting means and an output connected to a reset input of said third counting means, said gate generator outputs being used to bring said second and third counting means in phase with said first counting means after the producing of a distortion value.

4. Apparatus as claimed in claim 3 wherein an output of said measuring period gate generator means is connected to a reset input of said fourth counting means to set it in the zero position before the counting of a distortion value.

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Circuit arrangement for the measuring of the maximal value of the distortion of a binary series of steps during an adjustable measuring period

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