专利汇可以提供Chip package structure and method of fabricating the same专利检索,专利查询,专利分析的服务。并且A chip package structure including a heat dissipation substrate, a chip and a heterojunction heat conduction buffer layer is provided. The chip is disposed on the heat dissipation substrate. The heterojunction heat conduction buffer layer is disposed between the heat dissipation substrate and the chip. The heterojunction heat conduction buffer layer includes a plurality of pillars perpendicular to the heat dissipation substrate. The aspect ratio of each pillar is between about 3:1 and 50:1.,下面是Chip package structure and method of fabricating the same专利的具体信息内容。
What is claimed is:
This application claims the priority benefit of Taiwan application serial no. 97147409, filed Dec. 5, 2008. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of specification.
1. Field of the Invention
The present invention relates to a chip package structure and method of fabricating thereof providing good heat dissipation and absorption of shear stress.
2. Description of Related Art
In consideration of and by requirement of energy conservation and development of new technology for non-polluting energy sources, renewable energy sources have become the focus of attention, especially solar cells. In general, a III-V solar cell chip usually has better photoelectric effect but also has a rather high cost. Therefore, a great area of concentration system is used in association with the III-V solar cell chip to increase the concentration ratio to over a thousand times or more. However, a first problem to be solved for such a system is heat dissipation. In addition, a high power light emitting diode (LED) chip is also one of the current and common concentrator photovoltaic cells but also has the same problem of poor heat dissipation.
During the packaging process, a chip is usually disposed on a substrate and heat conducting adhesive or solder bumps are often used as a bonding medium for the chip and the substrate. The heat conducting adhesive is usually resin having a low coefficient of thermal conductivity and poor heat dissipation. Although the bonding method using solder bumps is easy at fabrication and has a low cost, coefficients of thermal expansion of bonding surfaces differ. Fatigue effect resulted from repetitive changes in temperature during system operation is mainly the reason for damage to bonding points of the chip. Fatigue failure may be classified into mechanical fatigue failure and thermal fatigue failure. Mechanical fatigue failure is due to continuous transformation and movement, resulting in decrease in mechanical strength. Thermal fatigue failure, on the other hand, is caused by poor match of coefficients of thermal expansion between two surfaces, resulting in the two surfaces pulling each other because of minor transformation generated at high and low temperatures, which, under long term influences, may easily cause the surfaces to peel off. As such, the chip and the substrate under the chip are damaged and performance as well as reliability of the chip package structure thereby decreases. In addition, the chip may be bonded to a submount which has a close coefficient of thermal expansion to the coefficient of thermal expansion of the chip. However, a material of the submount is usually ceramic such as Al2O3 and AlN. The structure of high power chip package has to include the submount. Therefore, there exist problems such as a low coefficient of thermal conductivity and high costs.
The present invention discloses a chip package structure providing good heat dissipation, absorption of shear stress, and prevention of mechanical fatigue failure or thermal fatigue failure of the system due to temperature changes.
The present invention provides a fabricating method for a chip package structure using a micro-electroforming technology for fabricating the chip package structure, thereby increasing performance and reliability of the chip package.
The present invention provides a chip package structure including a heat dissipation substrate, a chip, and a heterojunction heat conduction buffer layer. The chip is disposed on the heat dissipation substrate. The heterojunction heat conduction buffer layer is disposed between the heat dissipation substrate and chip. The heterojunction heat conduction buffer layer includes a plurality of pillars perpendicular to the heat dissipation substrate. The aspect ratio of each pillar is between about 3:1 and 50:1.
The present invention further provides a method of fabricating a chip package structure. First, a heat dissipation substrate is provided. Next, the heterojunction heat conduction buffer layer is formed on the heat dissipation substrate and includes a plurality of pillars perpendicular to the heat dissipation substrate. Then, the chip is bonded onto the heterojunction heat conduction buffer layer.
In the chip package structure of the present invention, the heterojunction heat conduction buffer layer disposed between the chip and the heat dissipation substrate has good heat dissipation, may release shear stress, and thus can prevent mechanical fatigue failure or thermal fatigue failure of the system due to temperature changes, thereby increasing performance and reliability of the chip package structure.
In order to make the aforementioned and other objects, features and advantages of the present invention more comprehensible, several embodiments accompanied with figures are described in detail below.
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
Referring to
The chip 106 is disposed on the heat dissipation substrate 102. The chip 106 is an LED chip having a P-electrode 105 and an N-electrode 107, for example. The chip 106 may also be a solar cell chip or other concentrator photovoltaic cells.
The heterojunction heat conduction buffer layer 104 is disposed between the heat dissipation substrate 102 and chip 106. A material of the heterojunction heat conduction buffer layer 104 includes tin, copper, or other high heat conduction metal material. In one embodiment, for example, the heat dissipation substrate 102 has a plurality of bonding pads 103 disposed thereon and the heterojunction heat conduction buffer layer 104 is disposed on the bonding pads 103 of the heat dissipation substrate 102.
Next, referring to
In addition, a cross-section of the pillar 108 of the heterojunction heat conduction buffer layer 104 is circular, for example. The pillars 108 are arranged in array, for example, in a most compact regular triangular array, as shown in
The chip package structure 100 of the present invention may also include a bonding layer 110 and a filler 112. The bonding layer 110 is disposed between the chip 106 and the heterojunction heat conduction buffer layer 104. Specifically, the bonding layer 110 is disposed on surfaces of the P-electrode 105 and the N-electrode 107. A material of the bonding layer 110 may be the same as or different from a material of the heterojunction heat conduction buffer layer 104. The material of the bonding layer 110 includes tin (Sn), copper, gold (Au), silver, or Au—Sn alloy, for example.
The filler 112 is disposed among the pillars 108 of the heterojunction heat conduction buffer layer 104. A material of the filler 112 includes polymer such as thermal grease and silver paste, or metallic powder such as non-metallic resin mixed with metallic powder.
In the chip package structure 100 of the present invention, the pillars 108 of the heterojunction heat conduction buffer layer 104 are arranged in high density to increase heat conduction area. Furthermore, the pillars 108 of the heterojunction heat conduction buffer layer 104 have a high aspect ratio and thus have flexibility to release the shear stress. In addition, the filler 112 disposed among the pillars 108 of the heterojunction heat conduction buffer layer 104 can further increase heat conduction. In other words, the chip package structure 100 of the present invention has good heat dissipation, may release shear stress, and thus can prevent mechanical fatigue failure or thermal fatigue failure of the system due to temperature changes, thereby increasing performance and reliability of the chip package structure 100.
Several embodiments are described below to illustrate the fabricating method of the chip package structure of the present invention.
First, referring to
Next, the steps to form a heterojunction heat conduction buffer layer on the heat dissipation substrate 300 using a micro-electroforming technology are as shown in
Referring to
Next, referring to
Afterward, referring to
Subsequently, referring to
In addition to the abovementioned micro-electroforming technology, the heterojunction heat conduction buffer layer may also be formed using the currently developed nano-technology to increase the aspect ratio of the pillars 308 thereby formed to about 50:1.
After completing the fabrication of the heterojunction heat conduction buffer layer 310, referring to
Subsequently, the bonding layer 316 of the chip 314 is bonded onto the heterojunction heat conduction buffer layer 310. In one embodiment, a material of the heterojunction heat conduction buffer layer 310 and the bonding layer 316 is tin, for example. Then, a solder reflow equipment, for example, may be used to bond the heterojunction heat conduction buffer layer 310 and the bonding layer 316 at 250° C. through eutectic bonding. In another embodiment, the material of the heterojunction heat conduction buffer layer 310 and the bonding layer 316 is copper, for example. Then, bonding may be done by a sintering process.
A difference between the second embodiment and the first embodiment lies in the method of forming the heterojunction heat conduction buffer layer. An illustration on the difference between the second and first embodiments is described below, wherein similarities therebetween are omitted.
First, referring to
Then, referring to
Afterward, referring to
Subsequently, referring to
A difference between the third embodiment and the first embodiment lies in the method of forming the heterojunction heat conduction buffer layer. An illustration on the difference between the third and first embodiments is described below, wherein similarities therebetween are omitted.
First, referring to
Next, as shown in
Subsequently, referring to
Then, referring to
The fourth embodiment is similar to the second and third embodiments with a difference in the method of forming the heterojunction heat conduction buffer layer. An illustration on the difference between the fourth embodiment and the second and third embodiments is described below, wherein similarities therebetween are omitted.
First, referring to
Refer to
Computer simulations illustrating a chip 206 of chip package structures 200a and 200b sustaining shear stress when having and not having the heterojunction heat conduction buffer layer 204 of the present invention are respectively shown in
A horizontal axis of
As shown in
Similarly, as shown in
In summary, in the chip package structure of the present invention, a metal material with high thermal conductivity (e.g. tin or copper) is used to replace heat conducting adhesive or solder bumps in the conventional technology for the heterojunction heat conduction buffer layer. In addition, a high density arrangement is adopted to increase thermal conduction area. Furthermore, because of a high aspect ratio, pillars of the heterojunction heat conduction buffer layer have flexibility, can release shear stress, and thus prevents the system from mechanical fatigue failure and thermal fatigue failure resulted from temperature changes. In addition, a filler such as metallic powder or polymer disposed among the pillars of the heterojunction heat conduction buffer layer can further improve thermal conduction. The chip package structure of the present invention has good heat conduction and can release shear stress for CTE mismatch, and thus is suitable as a heat dissipation solution for an LED package light source of large area and high heat or a concentration solar cell package.
It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.
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