Procedure for making semiconductor devices of small dimensions
阅读：67发布：2022-07-02
专利汇可以提供Procedure for making semiconductor devices of small dimensions专利检索，专利查询，专利分析的服务。并且A method for making a high speed field effect transistor of the planar type with Schottky-barrier or junction contacts, in which all apertures required for production of electrodes in an insulating layer covering the semiconductor body are produced simultaneously. A field effect transistor in which the gate electrode surrounds the drain electrode in a loop while the source electrode is subdivided and its parts essentially surround the gate electrode. The contact lands of the gate electrode are arranged essentially outside the region of capacitive influence of the source electrode.，下面是Procedure for making semiconductor devices of small dimensions专利的具体信息内容。
1. Method of making a field effect transistor comprising the steps of: forming a channel layer of high conductivity semiconductor material on a substrate of opposite conductivity type; forming an insulating layer on said channel layer; simultaneously removing portions of said insulating layer in a single removing operation to expose spaced source, drain, and gate areas in said channel layer; forming metal contacts in each of said source, drain and gate areas.
2. A method according to claim 1 wherein forming of the metal contacts comprises the steps of: depositing contacts of a first kind in each of said source, drain, and gate areas; and converting said contacts of said first kind in said source and drain areas into contacts of a second kind.
3. A method according to claim 2 wherein said contacts of said first kind are schottky barrier contacts and said contacts of said second kind are ohmic contacts.
4. A method according to claim 3 wherein said contacts are produced by the steps of: forming the schottky barrier contacts by depositing a first layer of chromium and a layer of nickel into each of said source, drain and gate areas; covering the gate area with a mask; converting the schottky barrier contacts so formed in the source and drain areas into ohmic contacts by depositing a second layer of chromium, a layer of gold-antimony, and a third layer of chromium into the source and drain areas; and heat treating the transistor at a temperature sufficient to allow the diffusion of the gold-antimony through the underlying layers, whereby the gold-antimony alloys with the channel layer to form ohmic contacts in the source and drain areas.
5. A method according to claim 4 wherein said first layer of chromium has a thickness range of from 20 to 100A; said layer of nickel has a thickness range of from 70 to 300A; said second layer of chromium has a thickness range of from 10 to 60A; said layer of gold-antimony comprises 0.5 to 4 per cent antimony and has a thickness range from 100 to 600A; said third layer of chromium has a thickness range of from 5 to 20A; and said heat treating is accomplished within a temperature range of from 350* to 550* C.
6. A method according to claim 4 wherein the steps of forming schottky barrier contacts comprise the additional step of depositing a layer of gold on top of said layer of nickel in each of said source, drain and gate areas.
7. A method according to claim 4 wherein the steps of forming schottky barrier contacts comprise the additional step of depositing a layer of goLd on top of said first layer of chromium.
8. A method according to claim 1 wherein the forming of metal contacts comprises the steps of: depositing contacts of a first kind in said source and drain areas; and depositing a contact of a second kind in said gate area.
9. A method according to claim 8 wherein said contacts of said first kind are ohmic contacts and said contact of said second kind is a schottky barrier contact.
10. A method according to claim 9 wherein said contacts are formed by the steps of: producing ohmic contacts in said source and drain areas by depositing a layer of chromium and a layer of gold-antimony into said source and drain areas; heat treating the transistor at a temperature sufficient to allow diffusion of the gold-antimony into the silicon whereby the gold-antimony alloys with the channel layer to form ohmic contacts in said source and drain areas; depositing a layer of gold into the gate area, thereby forming a schottky barrier contact in said gate area.
11. A method according to claim 10 wherein said layer of chromium has a thickness range of from 5 to 20A; said layer of gold-antimony comprises 0.5 to 4 per cent antimony and has a thickness of from 100 to 600A; said heat treating is accomplished within a temperature range of from 400* to 600* C; and said layer of gold deposited in the gate area has a thickness range of from 100 to 600A.
12. A method according to claim 10 which comprises the additional step of heat treating the transistor after said layer of gold has been deposited into the gate area.
13. A method according to claim 1 wherein said depositing of metal contacts comprises the steps of: diffusing a doping material of the same conductivity type as said channel layer into said source and drain areas; and depositing in the source, drain, and gate areas at least one layer of metal, thereby forming a schottky barrier contact in said gate area, and ohmic contacts in said source and drain areas.
14. A method according to claim 13 further comprising the steps of: masking the gate area prior to diffusing the doping material by generating a comparatively thin silicon dioxide layer in said gate area; and removing said silicon dioxide layer from the gate area after diffusing the doping material.
15. A method according to claim 13 wherein said doping material is phosphorus with a concentration range of between 10 20 to 10 19 atoms per cm3 in said channel layer; and one of said layers of metal is gold having a thickness of from 100 to 600A.
16. A method according to claim 13 which comprises the additional step of heat treating the transistor after one of said layers of metal has been deposited into the source, drain and gate areas.
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