High power microwave field effect transistor
阅读：578发布：2022-07-08
专利汇可以提供High power microwave field effect transistor专利检索，专利查询，专利分析的服务。并且The present invention relates to field transistors having source and drain electrodes in ohmic contact with a semiconductor body, and having an intervening gate electrode of the Schottky barrier type. The present device is designed for high power and high frequency applications. These capabilities are achieved by use of a meandering channel of appreciable width, to which an efficient path for power transmission is provided at both low and high frequencies. The path entails the use of an additional conductive layer superimposed over the source and drain metallizations and not only providing a low resistance d.c. path to the gate, but also forming an efficient low phase dispersion transmission line into the active region of the device.，下面是High power microwave field effect transistor专利的具体信息内容。
1. A high power field effect transistor comprising: a. a body of semiconductor material having a thin epitaxial active region, b. a metallic source electrode making ohmic contact with said active region, c. a metallic drain electrode making ohmic contact with said active region, said source and said drain metallizations having facing irregular boundaries defining a channel in said active region of predetermined length which meanders to enhance the channel width with respect to the overall dimensions of said region, d. an insulating layer overlaying said sOurce and drain metallizations having a meandering groove along said channel penetrating to said active region, and e. metallic conductive means, including a first portion for external connection, coating said insulating layer and the side walls of said meandering groove and overlaying portions of said source and drain metallization, and including a second portion contacting said channel in spaced relationship between the boundaries of said source and drain electrodes to form a meandering Schottky barrier gate electrode, said first gate portion reducing differences in electrical path length to points along said gate electrode to less than twice the distance between any two points, and the height of said insulating layer being adequate to reduce capacitive coupling between said conductive means and said source and drain metallizations to increase the impedance between them to permit efficient high frequency coupling into said gate region.
2. A field effect transistor as in claim 1 wherein said source electrode and said first conductive portion have planar metallizations extending from said active region, which are spaced to form an input transmission line matching the input impedance of said field effect transistor.
3. A field effect transistor as in claim 1 wherein said drain electrode and said first conductive portion have planar metallizations extending from said active region, which are spaced to form an output transmission line matching the output impedance of said field effect transistor.
4. A field effect transistor as in claim 1 wherein a. said source electrode and said first conductive portion have planar metallizations extending from said active region, which are spaced to form an input transmission line, and b. said drain electrode and said first conductive portion have planar metallizations extending from said active region, which are spaced to form an output transmission line matching the input and output impedance respectively of said field effect transistor.
5. A field effect transistor as in claim 2 wherein said input transmission line provides a signal path having a generally straight constant phase wave front orthogonal to said signal path, and wherein said irregular boundaries form a row of similarly shaped interpenetrating digital elements, said elements being pointed approximately normal to said wave front and having their bases aligned approximately parallel to said wave front for maintaining each digit at substantially the same phase.
6. A field effect transistor as in claim 3 wherein said output transmission line provides a signal path having a generally straight constant phase wave front orthogonal to said signal path, and wherein said irregular boundaries form a row of similarly shaped interpenetrating digital elements, said elements being pointed approximately normal to said wave front and having their bases aligned approximately parallel to said wave front for maintaining the output from each digit at substantially the same phase.
7. A field effect transistor as in claim 5 wherein the planar metallizations of said source electrode and of the first conductive portion within each input digit, together with the distributed intrinsic gate to source capacity, form a transmission line matched to the electrical input impedance of the channel formed along the perimeter of each input digit.
8. A field effect transistor as in claim 7 wherein said input digital elements are tapered, with said metallizations for each input digit also being tapered to produce, together with the intrinsic gate to source capacity, a transmission line associated with each digit whose characteristic impedance progressively increases as one proceeds into the digit to equalize the input current distribution about the perimeter of each input digit.
9. A field effect transistor as in claim 6 wherein the planar metallizations of said drain electrode and of first conductive portion within each output digit, together with the distributed Intrinsic gate to drain capacity, form a transmission line matched to the electrical output impedance of each output digit.
10. A field effect transistor as in claim 9 wherein said output digital elements are tapered, with said metallizations for each output digit also being tapered, to produce, together with the intrinsic gate to drain capacity, a transmission line associated with each digit whose characteristic impedance progressively decreases as one proceeds out of the digit to equalize the output loading about the perimeter of each output digit.
11. A high power field effect transistor comprising: a. a body of semiconductor material having a thin epitaxial active region, b. a metallic source electrode making ohmic contact with said active region, c. a metallic drain electrode making ohmic contact with said region, said source and said drain metallizations having facing boundaries defining a channel in said active region of predetermined length, d. an insulating layer overlaying said source and drain metallizations and having a groove along said channel penetrating to said active region, e. metallic conductive means, including a first portion for external connection, coating said insulating layer and the side walls of said groove and overlaying portions of said source and drain metallizations, and including a second portion contacting said channel in spaced relationship with the boundaries of said source and drain electrodes to form a Schottky barrier gate electrode, and the height of said insulating layer being adequate to reduce capacitive coupling between said conductive means and said source and drain metallizations to increase the impedance between them to permit efficient high frequency signals coupling into said path region.
12. A field effect transistor as in claim 11 wherein said source electrode and said first conductive portion have planar metallizations extending from said active region, which are spaced to form an input transmission line matching the input impedance of said field effect transistor.
13. A field effect transistor as in claim 11 wherein said drain electrode and said first conductive portion have planar metallizations extending from said active region, which are spaced to form an output transmission line matching the output impedance of said field effect transistor.
14. A field effect transistor as in claim 11 wherein said insulating layer is formed of SiOx deposited from silane decomposition.
15. A field effect transistor as in claim 14 wherein said insulating layer is provided with an intervening thin layer of SiO2 applied by sputtering to relieve thermal stresses between the source and drain metallizations and insulating layer.
16. A field effect transistor as in claim 11 wherein said active region is an epitaxial layer formed upon a high resistivity semiconductor body member.
17. A field effect transistor as in claim 16 wherein the boundaries of said active epitaxial region are delineated by sputter etching to achieve a minimum height mesa consistent with electrical isolation.
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