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Phase lock-loop frequency synthesizer

阅读:533发布:2023-02-09

专利汇可以提供Phase lock-loop frequency synthesizer专利检索,专利查询,专利分析的服务。并且A phase lock-loop synthesizer having a coarse voltage adjustment loop, an error loop, and a phase comparison loop. The coarse voltage adjustment loop includes in series a phase lock-loop device, buffer, frequency discriminator, variable gain D.C. amplifier, sum and difference amplifiers. The error loop includes in series the phase lock-loop device, buffer, divide by N circuit, frequency discriminator, sum and difference amplifiers and variable gain D.C. amplifier. The phase comparison loop includes the phase lock-loop device, buffer, divide by N circuit, divide by 2 circuits and a clock. The phase lock-loop frequency synthesizer can select any one of many operating frequencies and automatically maintain the preselected frequency. The coarse adjustment loop functions to generate a control voltage to maintain the desired frequency from the synthesizer. The error voltage loop functions to detect and correct errors between the programmed frequency and the output frequency and to change the output frequency on demand. The phase comparison loop compares the output frequency with the standard frequency.,下面是Phase lock-loop frequency synthesizer专利的具体信息内容。

1. A frequency synthesizer comprising: a. a generator means for generating an output signal having an operating frequency; b. a clock means for generating a standard signal having a predetermined frequency; c. a coarse voltage adjustment loop means; d. an error loop means; e. a phase comparison loop means; f. said coarse voltage adjustment loop means being responsive to said output signal and generating a control voltage for maintaining said synthesizer at a predetermined operating frequency; g. said error loop means responsive to said output signal and said standard signal for generating an error signal; h. said phase comparison loop responsive to said output signal and said standard signal for generating a signal that is compared with said control voltage for maintaining said synthesizer at said predetermined frequency; and i. said coarse voltage adjustment loop means includes a phase lock-loop device the output of which is connected to the input of a buffer the output of which is connected to the input of a first frequency discriminator, the output of which is connected to the input of a first variable gain D.C. amplifier, the output of which is connected to the input of a first sum and difference amplifier, the output of which is connected to the input of a second sum and difference amplifier, the output of which is connected to the input of said phase lock-loop device.
2. The device of claim 1 wherein: a. said error loop means includes said phase lock-loop device, the output of which is connected to the input of said buffer, the output of which is connected to the input of a divide by N circuit, the output of which is connected to the input of a second frequency discriminator, the output of which is connected to the input of a third sum and difference amplifier, the output of which is connected to the input of a second variable gain D.C. amplifier, the output of which is connected to the input of said second sum and difference amplifier, the output of which is connected to the input of said phase lock-loop device.
3. The device of claim 2 wherein: a. said phase comparison loop means includes said phase lock-loop device, the output of which is connected to the input of said buffer, the output of which is connected to said divide by N circuit, the output of which is connected to the input of a first divide by 2 circuit, the output of which is connected to the input of said phase lock-loop device, a clock, the output of which is connected to the input of a second divide by 2 circuit, the output of which is connected to the input of said phase lock-loop device.
4. The device of claim 3 wherein: a. said first variable gain D.C. amplifier includes a variable D.C. source operably connected to the input thereof.
5. The device of claim 4 wherein: a. said second variable gain D.C. amplifier includes a variable D.C. source operably connected to the input thereoF.
6. The device of claim 5 wherein: a. said second sum and difference amplifier includes a variable D.C. source operably connected to one of the inputs thereof.
7. The device of claim 6 wherein: a. said third sum and difference amplifier includes a variable D.C. source operably connected to one of the inputs thereof.
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