Balanced correlated ternary coding system
阅读：6发布：2021-12-30
专利汇可以提供Balanced correlated ternary coding system专利检索，专利查询，专利分析的服务。并且A balanced correlated ternary coding system including a modulator, a demodulator and an error detector. The modulator is designed so as to code a binary signal of level 0 or 1 into a ternary signal of level +, 0, or - according to any of the following truth tables: TABLE I TABLE II Binary Binary Ternary 0 1 Ternary 0 1 0 -+0+++0+0+-0 ---0 The demodulator is designed in such a way as to perform the inverse function of the modulator according to the following two truth tables which correspond respectively to the above truth tables of the modulator: TERNARY CODEBINARY CODETERNARY CODEBINARY CODEn-1n mn-1n m ++ 0++ 1 +0 1+0 0 --1-- 0 -0 0-0 1 0+ 1 0+ 1 0- 00-0 The error detector is designed so as to detect any one of the following code variations: A. A TERNARY + FOLLOWED BY A TERNARY -; B. A TERNARY - FOLLOWED BY A TERNARY +; AND C. TWO CONSECUTIVE TERNARY 0.，下面是Balanced correlated ternary coding system专利的具体信息内容。
1. A modulator for converting a binary code into a ternary code comprising: a. an inverter for receiving a binary code B and capable of generating at its output the complement B; b. a first and a second flip flop of the JK type each having two inputs J and K and two complementary outputs Q and Q satisfying the following logic equations: Qn 1 Qn Jn + Qn Kn (1) Qn 1 Qn Jn + Qn Kn (2) c. a first and a second gate each having two inputs and one output, the output of said first and second gates connected to one of the inputs J and K of the first and second flip flops respectively; d. an arithmetic adder having a first and a second input and one output, the first and second inputs of said arithmetic adder connected to one output of said first and second flip flops respectively and the output of said arithmetic adder providing said ternary code; and e. means interconnecting the outputs of said first and second gates to one of the inputs J and K of said first and second flip flops respectively, one of the outputs Q and Q of said first and second flip flops to the first and second inputs respectively of said arithmetic adder, one of the binary code B and its complement B to one input of said first and second flip flops and to the first input of said first and second gates, and the second input of the first and second gates to one output of said second and first flip flops respectively so that the first and second inputs of said arithmetic adder satisfy the following logic equations respectively: Y1n 1 Y1n Y2n Bn + Y1n Bn (3) Y2n 1 Y1n Y2n Bn + Y2n Bn (4) wherein Bn a digit of the binary code, Y1n, Y2n the present state of the ternary code expressed in binary form, Y1n 1, Y2n the following state of the ternary code expressed in binary form.
2. A modulator as defined in claim 1, wherein equations (3) and (4) are correlated with equation (1) and wherein said first and second gates are AND gates, and wherein the outputs of the first and second gates are connected respectively to the input J of the first and second flip flops, the output Q of said first and second flip flops is connected to the arithmetic adder, the binary code B and its complement B are connected to the inputs K of said second and first flip flops respectiveLy and to the first input of the second and first AND gates respectively, and the second input of said first and second AND gates are connected to the output Q of the second and first flip flops respectively.
3. A modulator as defined in claim 1, wherein equations (3) and (4) are correlated with equations (1) and (2) respectively and wherein said first and second gates are AND gates, whereby the outputs of the first and second AND gates are connected respectively to the input J of the first flip flop and to the input K of the second flip flop, the output Q of the first flip flop is connected to the first input of the arithmetic adder whereas the output Q of the second flip flop is connected to the second input of the arithmetic adder, the binary code B and its complement B are connected to the input J of the second flip flop and to the input K of the first flip flop respectively and to the first input of the second and first AND gates respectively, and the second input of the first and second AND gates is connected to the output Q of the second flip flop and to the output Q of the first flip flop respectively.
4. A modulator as defined in claim 1, wherein equations (3) and (4) are correlated with equations (2) and (1) respectively and wherein said first and second gates are AND gates, whereby the outputs of said first and second AND gates are connected to the input K of the first flip flop and to the input J of the second flip flop respectively, the output Q of the first flip flop and the output Q of the second flip flop are connected to the first and second inputs respectively of the arithmetic adder, the binary code B and its complement B are connected to the input K of the second flip flop and to the input J of the first flip flop respectively and to the first input of the second and first AND gates respectively, the second input of the first and second AND gates being connected to the output Q of the second flip flop and to the output Q of the first flip flop respectively.
5. A modulator as defined in claim 1, wherein equations (3) and (4) are correlated with equation (2) and wherein said first and second gates are AND gates, whereby the outputs of said first and second AND gates are connected to the inputs K of said first and second flip flops respectively, the outputs Q of the first and second flip flops are connected to the first and second inputs of the arithmetic adder respectively, the binary signal B and its complement B are connected to the inputs of the second and first flip flops respectively and to the first input of the second and first AND gates respectively, the second input of the first and second AND gates being connected to the outputs Q of the second and first flip flops respectively.
6. A modulator as defined in claim 1, wherein equations (3) and (4) are correlated with equation (1) and wherein said first and second gates are NOR gates, whereby the outputs of the first and second NOR gates are connected to the inputs J of the first and second flip flops respectively, the outputs Q of the first and second flip flops are connected to the first and second inputs respectively of the arithmetic adder, the binary code B and its complement B are connected to the inputs K of the second and first flip flops respectively and to the first input of the first and second NOR gates respectively, the second input of the first and second NOR gates being connected to the output Q of the second and first flip flops respectively.
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