Digital register readout circuit
阅读：1015发布：2020-11-07
专利汇可以提供Digital register readout circuit专利检索，专利查询，专利分析的服务。并且A register readout circuit arranged for use with common control switching systems wherein number digits are stored and serially read out at a high speed into a common controller. The circuitry utilizes binary ripple counters having a predetermined number of counting states to register each number digit. During the readout sequence, the common controller applies a high speed pulse train having a number of pulses equal to the number of counting states to each counter. When the counters are advanced to their initial zero counting states associated logic circuitry is enabled to gate remaining pulses of the high speed pulse train over digital leads to the common controller. Since the remaining pulses are mathematically equal to the registered number digits of the counters their reception by the common controller effectively constitutes a nondestructive readout of the registered number digit.，下面是Digital register readout circuit专利的具体信息内容。
1. In a system having control means responsive to digit pulse trains representing digits, the combination comprising means having a fixed number of counting states and responsive to said digit pulse trains for counting pulses of said digit pulse trains by assuming ones of said counting states representing said digits, means controlled by said control means for applying a high speed pulse train having a number of pulses equal to the number of said counting states to said counting means to cycle said counting means from said assumed digit counting states through said fixed number of counting states, and means enabled when said counting means are advanced through a defined one of said counting states for serially gating a number of said high speed pulses corresponding to said assumed digit counting states to said control means.
2. In a switching system having control means responsive to digit pulse trains, the combination for registering said digit pulse trains and for successively transferring each such registered pulse train to said control means during an interdigital interval over a single lead for each such pulse train comprising means having a fixed number of counting states and responsive to said digit pulse trains for counting pulses of said digit pulse trains by assuming one of said counting states, means controlled by said control means for applying a high speed pulse train having a number of pulses equal to the number of said counting states to said counting means to advance said counting means from said assumed counting state through said fixed number of counting states during an interdigital time interval, and means enabled when said counting means are advanced through a defined one of said counting states for serially gating a number of said high speed pulses corresponding to said assumed counting state to said control means.
3. In a switching system the invention defined in claim 2 wherein said counting means comprises means having said fixed number of counting states and enabled by said pulses of said digit pulse trains for recording a sum of said pulses in said assumed ones of said counting states, and means for selectively steering said digit pulse trains to predetermined ones of said recording means.
4. In a switching system the invention defined in claim 3 wherein said recording means comprises accumulating means including a chain of n serially connected bistable elements, wherein n is an integer, for registering the binary sum of said pulses in predetermined ones of 2n counting states, and control gate means connected to said accumulating means and enabled by said steering means to advance said accumulating means one counting state for each sequentially received pulse.
5. In a switching system the invention defined in claim 4 wherein said steering means comprises sequentially controlled bistable elements having a fixed number of counter states for selectively enabling said control gate means.
6. In a switching system the invention defined in claim 5 wherein said applying means comprises readout means enabled by the termination of each of said digit pulse trains for advancing said sequentially controlled bistable means one said counter state and for signaling said control means to read the recorded pulse sum of said accumulating means.
7. In a switching system the invention defined in claim 6 wherEin said applying means further comprises pulse repeating means enabled by said signaled control means for addressing a fixed number of high speed pulses to said control gate means to advance said accumulating means through 2n counting states.
8. In a switching system the invention defined in claim 7 wherein said gating means comprises means enabled by said serially connected bistable elements advancing through said defined counting states for generating a control signal.
9. In a switching system the invention defined in claim 8 wherein said gating means further comprises means controlled by said steering means and said generating means for transmitting remaining ones of said high speed pulses to said control means.
10. In a telephone switching system wherein telephone stations and trunks may be interconnected through a switch network enabled by a common controller responsive to digit pulse trains received from said stations and said trunks, the combination comprising a plurality of digit counters each having a fixed number of digit counting states for counting dial pulses of said digit pulse trains by assuming one of said digit counting states, control gate means connected to each of said digit counters and enabled by said dial pulses for advancing said digit counters from an initial one of said digit counting states to said assumed digit counting state, steering counter means having a fixed number of counter states for selectively directing said digit pulse trains to predetermined ones of said control gate means, readout means responsive to a termination of each of said digit pulse trains for applying a signal to both said steering counter to advance said steering counter to a next one of said counter states and to said common controller, pulse repeating means enabled by said signaled common controller for applying a high speed pulse train having a predetermined number of pulses to said control gate means to advance said digit counters from said assumed digit counting states through said fixed number of digit counting states, binary logic means enabled by said common controller for detecting the advance of said digit counters through said initial counting states, and means controlled by said steering counter in combination with said enabled binary logic means for gating a number of said high speed pulses corresponding to said assumed digit counting states into said common controller.
11. In a pulse register circuit wherein incoming pulses of digital pulse trains may first be counted and accumulated and then read out onto digital leads by the application of a pulsing train having a fixed number of pulses, the combination comprising a plurality of digit counters each having a chain of n serially connected bistable memory elements where n is an integer for counting said incoming pulses by assuming one of 2n binary counting states, a plurality of control gates each connected to one of said digit counters and responsive to said digital pulse trains for advancing said counters from an initial one of said binary counting states to said assumed binary counting state, a steering counter having serially connected bistable memory elements connected to said control gates for selectively directing said digital pulse trains to predetermined ones of said control gates in response to counter states of said steering counter memory elements, a readout means responsive to a termination of each of said digital pulse trains for applying a signal to advance said steering counter from one counter state to another, a pulse repeating means enabled by said signal of said readout means for applying said pulsing train to said plurality of control gates to concurrently advance said digit counters through said 2n binary counting states, a binary logic means individual to each of said digit counters and enabled by said digit counter bistable memory elements for Detecting the advance of each said digit counter from said assumed binary counting state through a zero counting state, and means controlled by said steering counter in combination with said binary logic means for serially reading out onto said digital leads decimal numbers of pulses of said pulsing train corresponding to the assumed binary counting states of said digital counters.
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