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Wiring delay time display device and automatic wiring device for field programmable gate array

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专利汇可以提供Wiring delay time display device and automatic wiring device for field programmable gate array专利检索,专利查询,专利分析的服务。并且PURPOSE: To use an optimum field programmable gate array(FPGA) product by storing a data relating to the internal block of the FPGA to a ROM and a RAM, etc., and allowing a user to extract the data at any time.
CONSTITUTION: A built-in ROM content reader 27 reads a data relating to an internal block stored in advance in the built-in ROM of a field programmable gate array(FPGA) mounted on an LSI from a field programmable gate array(FPGA) supporting device 21. The wiring delay between wiring blocks of the FPGA is calculated and the wiring delay time is displayed on a cathode ray tube and a liquid crystal display device, etc., of the device 21. Moreover, the device 21 uses an FPGA program basic specific data to place priority onto internal blocks and extracts a data satisfying a specific limit condition among the basic specification data. An FPGA reader/writer 25 is used under the priority and the limit condition to apply automatic wiring to the wire block of the FPGA. Thus, the optimum FPGA product is used.
COPYRIGHT: (C)1992,JPO&Japio,下面是Wiring delay time display device and automatic wiring device for field programmable gate array专利的具体信息内容。

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