Magnetic tape data system
阅读：602发布：2022-06-25
专利汇可以提供Magnetic tape data system专利检索，专利查询，专利分析的服务。并且There is disclosed a data handling system including input-output means, intermediate memory means and principal memory means, together with data transfer and processing control logic. Input and output parallel to serial and serial to parallel and code conversion capability are provided. Input-output temporary storage capability is provided by a shift register. The intermediate memory is a random access memory or the like having a storage capacity substantially exceeding that of the inputoutput shift register. The principal memory is a magnetic tape system, preferably employing a magnetic tape cassette as a memory medium. The system is useable in various ways, for example as a data terminal capable of local keyboard and/or remotely controlled data storage and transmission. Data input and output may be in parallel or serial form and a variety of data rates and data code word may be acoommodated without system modification. Broadly stated, for operation in the record mode, the system accumulates a block of data provided by a data source (for example a line of print) in the intermediate memory through the input-output means, and thereafter transfers the entire data block to the principal memory at a high speed. For playback, an entire block of data is transferred at high speed from the principal memory into the intermediate memory and is thereafter provided through the input-output means to suitable data utilization devices at a data rate compatible with such devices. Among the features provided by the system are error checking and correction on a character-by-character and data block basis, data block identification (search) based on selectable identifying code characteristics and compatibility with a variety of keyboard controlled devices or other data input and output devices, and automatic and manual data gathering and processing machinery.，下面是Magnetic tape data system专利的具体信息内容。
1. An on-line transmission and reception terminal system for serially handling data in the form of multi-bit character code words from a data source, comprising: input-output means including means connected to said data source for converting a character code word from said data source to a characTer code word having a fixed number of bits per character and a preselected bit code, a line of characters having a predetermined number of characters; an intermediate memory connected to said character code word converting means for storing lines of characters in code word form; means for serially reading out code words in said character code word converting means a bit at a time from said input-output means to said intermediate memory; a principal memory including a tape medium; means for driving said tape at a constant speed responsively to the read-out of a line of characters either from said intermediate memory to said principal memory or from said principal memory to said intermediate memory; means for activating said tape drive means and for serially reading out code words corresponding to a line of characters stored in said intermediate memory to one track of said tape memory, the bits representing the characters being serially read out onto one track of said tape as it is moving such that character code words are stored on one track in serial fashion a bit at a time; means for activating said tape drive means and for serially reading out code words corresponding to a line of characters from said tape to said intermediate memory one bit at a time; means for serially reading out said intermediate memory to said input-output means a bit at a time; a data utilization device; and, means for reading out said input-output means to said data utilization device.
2. The system as defined in claim 1 wherein said line of data comprises a block of data, said intermediate memory means storing a block of data comprising a plurality of character code words; said principal memory storing a plurality of data blocks; and wherein said readout means include control logic means for establishing a recording operation sequence comprising entry of data from said data source through said input-output means, accumulation of a block of data in said intermediate memory with said block of data being defined by a particular terminal character, and transfer of said data block to said principal memory; said control logic means including first means coupling said input-output means to said intermediate memory for effecting transfer of data from said input-output means to said intermediate memory, second means coupling said intermediate memory to said principal memory for effecting data transfer in serial bit form from said intermediate memory to said principal memory, first control means coupled to said first transfer means for actuating said first transfer means in response to incoming data from said data source, means coupled to said intermediate memory for sensing said terminal character in said incoming data, and second control means coupled to said second tranfer means and responsive to said sensing means for actuating said second transfer means to transfer the block of data accumulated in said intermediate memory to said principal memory.
3. A system as defined in claim 2 wherein said input-output means includes first means for receiving data from said data source in parallel form with all of the bits defining a character code word appearing simultaneously; second means for receiving data from an data source in serial form with each of the bits defining a character code word appearing in sequence; wherein said first transfer means is operative to provide data to said intermediate memory one bit at a time; and wherein said second transfer means is operative to provide data to said principal memory one bit at a time.
4. A system as defined in claim 2 wherein said input-output means includes multiple bit storage means connected to said data source and said intermediate memory, said storage responsive to the bits of an externally generated character code word to generate an additional bit, the value of which is a function of the parity of the incoming code.
5. A system as defined in claim 2 further including a keyboard and keyboard responSive error correction means coupled to said input-output means to delete an undesired character being entered and to substitute another character therefor.
6. A system as defined in claim 2 wherein said sensing means comprises means for storing a reference code word representing said terminal character, means connected to said reference storage means and said input-output means to compare an incoming character code word with said reference code word, and means for generating a coincidence signal when said incoming character code word matches a reference code word.
7. A system as defined in claim 6 wherein said sensing means includes means for providing a second coincidence signal in response to recognition of a second pre-determined character; and wherein said second control means is responsive to either said first or second coincidence signal to actuate said second transfer means.
8. A system as defined in claim 2 wherein said input-output means includes means for temporarily storing incoming data from said data source; and means responsive to an incoming character code word to transfer a previously received character code word from said input-output storage means to said intermediate memory.
9. A system as defined in claim 8 wherein said control logic means includes means responsive to the arrival of said terminal character in said input-output means to actuate said first transfer means to transfer the data stored in said input-output means together with said terminal character to said intermediate memory, and means for thereafter actuating said second transfer means to transfer the entire block of data to said principal memory.
10. A system as defined in claim 2 wherein said intermediate memory includes a plurality of separate memory sites for storing the individual bits comprising a data block; and wherein said second transfer means comprises means to actuate each of said memory sites in sequence to transfer the contents thereof to said principal memory, means responsive to the actuating of each memory site to generate a timing pulse and means for storing said timing pulse in said principal memory together with the associated data bit.
11. A system as defined in claim 2 wherein said input-output device includes means for temporarily storing character code words received from said data source, means for receiving each bit of an incoming character code word in sequence and for entering said bits in said temporary storage means, further means for receiving all of the bits of an incoming character code word simultaneously and for storing said bits in said temporary storage means, means responsive to incoming data for transferring data previously stored in said temporary storage means to said intermediate memory one bit at a time; wherein said sensing means includes means for storing a reference code word representing said terminal character, means for inspecting each incoming character code word and for generating a coincidence signal when said incoming code word matches said reference code word, means responsive to said coincidence signal for transferring all data contained in said temporary storage means together with said terminal character to said intermediate memory and for thereafter actuating said second transfer means; wherein said intermediate memory comprises a plurality of individual memory sites for storing the individual bits of an incoming data block; and wherein said second transfer means comprises means for actuating each of said memory sites in turn to transfer the contents thereof to said principal memory one bit at a time; means for generating a timing pulse in coincidence with the activation of each memory site, and means for storing said timing pulse in said principal memory together with the associated bit.
12. A system as defined in claim 11 wherein said input-output means further includes means responsive to the bits of an incoming character code word to generate an additional bit, the value of which is a function of a Parity of the incoming code word, and means for entering said additional bit in said temporary storage means together with the associated incoming code word.
13. A system as defined in claim 12 further including a keyboard and keyboard responsive error correction means coupled to said input output means for deleting a character code word from said temporary storage means and for inserting therefor a desired code word.
14. The system as defined in claim 1 wherein said line of data comprises a block of data, wherein said intermediate memory means stores a block of data comprising a plurality of character code words; said principal memory storing a plurality of data blocks; and wherein said readout means include control logic means for establishing a playback operation sequence comprising entry of a block of data in said intermediate memory from said principal memory, and transfer of said block of data to said utilization device through said input-output means; said control logic means including first means coupling said intermediate memory to said input-output means for effecting transfer of data from said intermediate memory to said input-output means, second means coupling said input-output means to said external utilization device for effecting data transfer from said input-output means to said external utilization device, third means coupling said principal memory to said intermediate memory for transferring data from said principal memory in serial bit form to said intermediate memory, first and second control means coupled to said first and second transfer means for actuating said first and second transfer means to provide data to said utilization device, and third control means coupled to said third transfer means and responsive to transfer of said block of data to said utilization device for actuating said third transfer means to enter another block of data into said intermediate memory from said principal memory.
15. A system as defined in claim 14 wherein said second transfer means includes first means for providing data to said utilization device in parallel form with all of the bits defining a character code word appearing simultaneously; second means for providing data to said utilization device in serial form with each of the bits defining a character code word appearing in sequence; wherein said first transfer means is operative to provide data to said input-output means one bit at a time; and wherein said third transfer means is operative to provide data to said intermediate memory one bit at a time.
16. A system as defined in claim 14 wherein said input-output means includes means responsive to the bits of an outgoing character code word to test for an error in said code word, and means responsive to detection of an error for preventing said erroneous code word from being provided to said utilization device.
17. A system as defined in claim 16 further including means responsive to detection of an erroneous code word to suppress said erroneous code word, and to substitute another code word therefor.
18. A system as defined in claim 14 wherein a data block is defined by a particular terminal character, and wherein said third control means comprises means for storing a reference code word representing said terminal character, means connected to said reference storage means and said input-output means to compare an outgoing character code word with said reference code word, means for generating a coincidence signal when said outgoing character code word matches a reference code word, and means responsive to said coincidence signal to actuate said third transfer means.
19. A system as defined in claim 18 wherein a group of data blocks comprising a message is identified by a second particular terminal character, and wherein said third control means includes means for providing a second coincidence signal in response to recognition of said second particular character; and wherein said control logic means is responsive to said second coincidencE signal to prevent said third transfer means from being actuated.
20. A system as defined in claim 14 wherein said input-output means includes means for temporarily storing character code words provided by said intermediate memory, means to initiate transfer of a previously stored character code word to said utilization device, and means responsive to transfer of a character code word from said temporary storage means to enter another code word into said input-output means from said intermediate memory.
21. A system as defined in claim 20 wherein a data block is defined by a particular terminal character; wherein said third control means includes means for sensing the presence of said terminal character in said temporary storage means for operating said second transfer means to transfer out the data stored in said temporary storage means, and for concurrently operating said third transfer means to load a block of data from said principal memory into said intermediate memory, and means for thereafter actuating said first transfer means to transfer data from said intermediate memory to load said temporary storage means.
22. A system as defined in claim 14 wherein said principal memory contains a plurality of control pulses, each data bit being associated with one of said control pulses; wherein said intermediate memory includes a plurality of separate memory sites for storing the bits comprising a data block wherein said control logic means includes means to operate said principal memory to generate data pulses and the associated control pulses; and wherein said third transfer means comprises means responsive to actuation thereof to operate said principal memory, and means responsive to said control pulses to actuate said memory sites in sequence to transfer the data pulses associated with said control pulses to respective memory sites of said intermediate memory.
23. A system as defined in claim 14 wherein said input-output device includes means for temporarily storing a character code word received from said intermediate memory, means coupling said storage means to said data source for extracting each of the bits of a character code word in sequence for provision to said utilization device, further means for extracting all of the bits of a character code word simultaneously for provision to a utilization device, and means responsive to extraction of a character code word from said temporary storage means for entering another character code word therein from said intermediate memory; wherein a block of data is defined by a particular terminal character; wherein said third control means includes means for storing a reference code word representing said terminal character, means for inspecting each character code word in said temporary storage means and for generating a coincidence signal when said inspected code word matches said reference code word, means responsive to said coincidence signal for transferring out all data remaining in said temporary storage means, and for concurrently actuating said third transfer means to load a new block of data into said intermediate memory, and means responsive to completion of the loading of said intermediate memory to actuate said second transfer means to reload said temporary storage means.
24. A system as defined in claim 23 wherein said input-output means further includes means coupled to said temporary storage means to detect the existence of an error in a character to be transferred to a utilization device, and means responsive to detection of an error for preventing transfer of the erroneous code word.
25. A system as defined in claim 24 further including means responsive to detection of an error for suppressing the erroneous code word and for substituting therefor a desired code word.
26. The system as defined in claim 1 wherein said input-output means includes a memory system for storage and retrieval of data in a plurality of different formats, said data being defined by multibit charactEr code words, including information bits and other bits with the number of information bits and other bits per code word, and the actual code word representing a given character varying with the particular format being employed, said memory system comprising: an input-output unit for handling character code words in any acceptable format, including means to receive data from said data source during record operation and means to provide data to said utilization device during playback operation; memory means coupled to said input-output unit for receiving data from said input-output unit during record operation and for providing data to said input-output unit during playback operation; data format selecting means coupled to said input-output unit; mode selecting means coupled to said input-output unit and to said memory means for establishing record and playback operating modes for said memory system; said input-output unit further comprising means for establishing a predetermined number of bits to be stored for each character code word, independent of the data format, said number equaling or exceeding the number of information bits per code word in any acceptable code format, means responsive to said format selecting means, and to an incoming code word having a total number of bits less than said predetermined number to generate one or more additional bits of predetermined value, means for associating said additional bits with said incoming code word for storage in said memory means, and means responsive to said format selecting means and to an incoming code word having a total number of bits exceeding said predetermined number for suppressing one or more of said other bits before storage in said memory means whereby the number of bits stored per code word is always equal to said predetermined number.
27. A system as defined in claim 26 wherein said other bits comprise at least one initial bit and at least one terminal bit, of predetermined value, and wherein said input-output unit includes means responsive to said format selecting means and to a code word provided by said memory means to generate the required initial and terminal bits in accordance with the selected data format.
28. A system as defined in claim 26 wherein said input-output unit includes means responsive to a code word provided by said memory means to suppress all bits of said code word except said information bits and means for coupling said information bits to said utilization device.
29. A system as defined in claim 26 wherein at least one of said information bits is an error checking bit, and wherein said input-output unit includes means responsive to an incoming code word not including said error checking bit for generating an error checking bit, and for associating said error checking bit with said code word before storage in said memory means.
30. A system as defined in claim 29 wherein said input-output means includes means responsive to a code word provided by said memory means and including said error checking bit for suppressing said error checking bit before provision to said utilization device.
31. A system as defined in claim 30 wherein said input-output units includes means responsive to said error checking bit for determining the existence of an error in the associated code word, and means responsive to an error for preventing transmission of said erroneous code word to said utilization device.
32. A system as defined in claim 31 further including means responsive to said error checking means for substituting a predetermined code word for said erroneous code word and for providing said predetermined code word to said utilization device.
33. A system as defined in claim 26 including means responsive to said format selecting means and to an incoming code word for transforming said incoming code word from one format to another.
34. A system as defined in claim 26 further including means responsive to said format selecting means and to a code word provided by said memorY means for converting the information bits thereof from one format to another.
35. The system as defined in claim 1 wherein said input-output means includes means for storing at least one code word, first coupling means for connecting said storage means to said data source, and second coupling means for connecting said storage means to said data utilization device; wherein a line of data comprises a block of data, said intermediate memory means storing a block of data comprising a number of character code words substantially exceeding the storage capacity of said input-output means; said means for serially reading out said input-output means to said intermediate memory and said means for serially reading out said intermediate memory to said input-output means including first means coupling said input-output means to said intermediate memory for transferring data one bit at a time between said input-output means and said intermediate memory; said principal memory tape medium including a two track tape, said two-track tape comprising data storage means having a memory medium; said means for serially reading out said intermediate memory to said principal memory and said means for serially reading out said principal memory to said intermediate memory including second means coupling said intermediate memory to said principal memory medium for transferring information one bit at a time between said intermediate memory and said principal memory medium; and further including logic means coupled to said first and second serial transfer means for controlling the information transfer operations for said system.
36. A system as defined in claim 35 further including a reference clock for generating a primary timing signal, means for generating a first pulse train at a frequency less than the clock frequency; wherein said first coupling means includes means for receiving data one bit at a time at a bit rate which is nominally a sub-multiple of the frequency of said first pulse train; and wherein said logic means includes counter means responsive to said first pulse train and to an actuating signal to generate a series of pulses at said sub-multiple frequency with the first pulse in predetermined time relation to said activating signal, sensing means responsive to an incoming data pulse to generate said activating signal, and means responsive to said series of pulses for operating said input-output storage means to store each incoming data bit.
37. A system as defined in claim 36 further including control means responsive to said series of pulses for operating said first transfer means to transfer previously stored data bits from said input-output storage means to said intermediate memory.
38. A system as defined in claim 37 including means for generating a second pulse train at a frequency substantially exceeding the frequency of said first pulse train, means responsive to the accumulation of an entire block of data in said intermediate memory for generating a data block transfer initiation signal, means in said logic means responsive to said data block transfer initiation signal and to said second pulse train for operating said intermediate memory to transfer data one bit at a time to the principal memory at a bit rate equal to the frequency of said second pulse train,
39. A system as defined in claim 38 including means responsive to said data block transfer initiation signal for generating a second series of pulses, the number of pulses in said second series being equal to the bit storage capacity of said input-output storage means, means for coupling said second group of pulses to said control means to actuate said input-output storage means to transfer all data therein to said intermediate memory and means responsive to completion of said second series of pulses for initiating transfer of said block of data to said principal memory from said intermediate memory.
40. A system as defined in claim 39 including means responsive to said data block transfer inItiation signal for determining the number of bits comprising the data block, and means responsive to transfer of said number of bits to said principal memory for terminating transfer of data from said intermediate memory to said principal memory.
41. A system as defined in claim 40 further including means responsive to completion of transfer of said data block to said principal memory for clearing said intermediate memory in preparation for storage of another data block.
42. A system as defined in claim 36 wherein each character code word commences with a predetermined non-information bearing bit; wherein said sensing means is responsive to said non-information bearing bit to activate said counter to advance in response to the pulses of said first pulse train, said counter including means to provide a first output pulse at a predetermined count corresponding to the nominal center of the bit period of the first information bearing bit of the incoming character code word, and means for providing further counter output pulses at a succession of counts corresponding to the nominal centers of the bit periods for the other information bearing bits of said incoming character code word, means for collecting said pulses to form an electrical signal, and means for deactivating and resetting said counter when a predetermined maximum count is reached.
43. A system as defined in claim 42 wherein the frequency of said first pulse train is at least four times the nominal bit rate.
44. A system as defined in claim 42 wherein the frequency of said first pulse train is eight times the nominal bit rate.
45. A system as defined in claim 35 including a reference clock for generating primary reference timing signal, means connected to said clock for generating a pulse train at a frequency less than the clock frequency; wherein said second coupling means includes means for transmitting data one bit at a time at a bit rate which is nominally a sub-multiple of the frequency of said pulse train; wherein said logic means includes counter means responsive to said pulse train to generate a series of pulses at said sub-multiple frequency, means for actuating said intermediate memory, said input-output means and said second coupling means in response to said series of pulses to transfer a character code word from said intermediate memory to said input-output storage means,and for concurrently transmitting a previously stored character code word to said utilization device at said sub-multiple frequency.
46. A system as defined in claim 45 wherein said counter includes means for generating an additional pulse preceding said series of pulses by an interval equal to the interval between pulses at said data bit rate, means responsive to said additional pulse for generating an initial bit for transmission as part of said code word, and means for preventing actuation of said second coupling means by said series of pulses until after termination of said additional pulse.
47. A system as defined in claim 46 further including means responsive to said master clock to generate a second pulse train at a frequency substantially higher than the frequency of said first pulse train, means responsive to said second pulse train for generating a series of timing pulses, means for storing said timing pulses together with the bits of an associated data block in said principal memory, means for activating said data storage means to retrieve said timing pulses, means responsive to said retrieved timing pulses for activating said intermediate memory to transfer a data block from the principal memory to the intermediate memory, means responsive to said second pulse train for generating a second series of pulses comprising a number of pulses equal to the bit storage capacity of said input-output storage means, means responsive to said second series of pulses, and to transfer of an entire block of data from said principal memory to said intermediate memory to activate said intermediate memory and saiD input-output means for transferring from said intermediate memory to said input-output means a number of bits equal to the number of pulses in said second series of pulses.
48. A system as defined in claim 47 further including means for preventing operation of said counter means during data transfer under control of said second series of pulses.
49. A system as defined in claim 26 wherein said memory medium comprises a magnetic recording tape; wherein said tape driving means includes tape transport means and drive means for said transport means; wherein said second transfer means includes first and second recording circuits for recording first and second information tracks; and wherein said logic means includes means for generating a data transfer pulse train, means to initiate a data record operation sequence comprising means for activating said transport drive means for continuous operation, means for operating said intermediate memory in response to said data transfer pulse train to transfer data to said first record circuit in bit-by-bit synchronism with said data transfer pulses, and means for coupling said data transfer pulse train to said second recording circuit to store a track of timing pulses on said tape with the timing pulses in synchronism with the bits of said data track.
50. A system as defined in claim 49 further including means for deactivating said transport drive means, said intermediate memory and said second recording circuit after a predetermined number of pulses corresponding to the number of bits to be recorded.
51. A system as defined in claim 49 wherein said deactivating means comprises means for storing an indication of the total number of bits comprising a data block, means providing a running count of the number of bits transferred to said first recording circuit, means providing an indication when the number of bits transferred to said first recording circuit equals the pre-stored number of bits comprising said data block, and means responsive to said indication for terminating said data record sequence.
52. A system as defined in claim 49 including means responsive to activation of said transport drive means to delay the actuation of said intermediate memory in response to said data transfer pulse train and said second recording circuit for a predetermined interval to allow said transport to reach its normal operating speed.
53. A system as defined in claim 52 wherein said logic means includes means responsive to said data transfer pulse train and to activation of said transport drive means for generating a series of pulses including a number of pulses equal to the bit storage capacity of said input-output storage means, and means for operating said input-output storage means and said intermediate memory to transfer all data stored in said input-output storage means to said intermediate memory during said predetermined delay interval.
54. A system as defined in claim 49 wherein said first and second recording circuits include means for converting a binary code input to a non-return-to-zero for recording.
55. A system as defined in claim 49 wherein said second transfer means includes first and second playback circuits associated with the first and second information tracks of a tape serving as the principal memory medium, and wherein said logic means includes means to initiate a data playback sequence comprising means for actuating said transport drive means for continuous operation, means for connecting said first playback circuit to said intermediate memory, means connected to said second playback circuit and responsive to timing pulses in said timing track for activating said intermediate memory to store the data bit associated with each timing pulse, means responsive to playback of an entire data block for deactivating said transport drive means and said intermediate memory.
56. A system as defined in claim 55 wherein said deactivating means comprises means for stopping said transport drive means afteR a predetermined interval if timing pulses are not detected by said second playback circuit.
57. A system as defined in claim 56 including means responsive to actuation of said transport drive means to delay activation of said intermediate memory for a predetermined tape start-up interval to allow said transport to reach its normal operating speed, and means for inhibiting operation of said deactivating means during said start-up delay interval.
58. A system as defined in claim 57 wherein said logic means includes means connected to said second playback circuit and responsive to an externally generated command to override said deactivation means until a timing pulse has been played back from said timing track through said second playback circuit.
59. A system as defined in claim 55 including means responsive to actuation of said transport drive means to delay activation of said intermediate memory for a predetermined tape start-up interval to allow said transport to reach its normal operating speed.
60. A system as defined in claim 55 including means responsive to initiation of said data playback sequence for activating said input-output storage means and said second coupling means to transfer any data contained in said input-output storage means to said utilization device during said data playback operation.
61. A system as defined in claim 55 including means responsive to said data transfer pulse train and to deactivation of said transport drive means for generating a series of pulses having a number of pulses equal to the bit capacity of said input-output storage means, and means for activating said intermediate memory and said input-output storage means to enter the initial bits of said data block into said input-output storage means, one bit for each pulse in said series of pulses.
62. A system as defined in claim 61 further including means responsive to entry of said initial bits of said data block in said input-output storage means for activating said intermediate memory and said input-output means to enter the remaining bits of said data block into said input-output storage means on a bit-by-bit basis and to transfer previously entered bits to said utilization device through said first coupling means.
63. A memory system as defined in claim 35 wherein said second transfer means is adapted to retrieve data from a magnetic tape serving as said principal memory medium, said tape having recorded thereon a first track of data pulses and a second track of timing pulses synchronized with said data pulses, groups of said pulses being separated by blank portions of said tape to define individual blocks of data; wherein said second transfer means includes separate playback circuits for said data and timing tracks; wherein said tape drive means includes magnetic tape transport means and transport drive means; and wherein said logic means includes means for establishing a playback operating sequence comprising means for activating said transport drive means, means responsive to activation of said transport drive means for coupling said data track playback circuit to said intermediate memory, control means responsive to timing pulses played back by said timing track playback circuit to activate said intermediate memory to store a data pulse associated with each timing pulse, and cycle termination means responsive to playback of an entire data block for deactivating said transport drive means and preventing further storage of data in said intermediate memory.
64. A system as defined in claim 63 wherein said cycle termination means comprises means to sense the beginning of an unrecorded portion on a tape and to turn off said transport drive means in response thereto, and means for decoupling said data track playback circuit from said intermediate memory and said timing track playback circuit from said intermediate memory control means when said transport drive is not activated.
65. A system as defined in claim 63 wherein said cYcle termination means comprises timing means connected to said timing track playback circuit for generating a cycle termination signal when timing pulses are not played back within a predetermined interval and means responsive to said cycle termination signal to deactivate said transport drive means and to decouple said data track playback circuit from said intermediate memory and said timing track playback circuit from said intermediate memory control means.
66. A system as defined in claim 63 including means responsive to actuation of said transport drive means to prevent operation of said intermediate memory and said cycle termination means for a predetermined start-up delay period to allow said transport to reach its normal operating speed.
67. A system as defined in claim 66 wherein said logic means includes means for establishing a load operation sequence comprising means responsive to an external load command to activate said transport drive means and to deactivate said cycle termination means, and means responsive to the start of playback of information by said second transfer means to reactivate said cycle termination means.
68. A system as defined in claim 67 wherein said means responsive to the start of playback of a data block comprises means for generating a first signal in response to said external load command, means responsive to the first timing track pulse of a data block for generating a second signal, and means responsive to said first signal for deactivating said cycle termination means and responsive to said second signal for reactivating said cycle termination means.
69. A system as defined in claim 63 wherein said logic means includes first sequence control means responsive to entry of a complete data block in said intermediate memory from said principal memory to load an initial portion of said data block into said input-output storage means and second sequence control means responsive to entry of said initial portion of said data block in said input-output storage means to load the remaining bits of said data block into said input-output storage means on a bit-by-bit basis and to transfer prestored bits to said utilization device through said first coupling means.
70. A system as defined in claim 69 wherein said first sequence control means includes means for generating a group of actuating pulses for said intermediate memory and said input-output means, said group having a number of pulses equal to the bit capacity of said input-output storage means.
71. A system as defined in claim 69 wherein said second sequence control means includes means for generating a further group of actuating pulses for said intermediate memory and said input-output means, said further group having a number of pulses equal to the number of bits stored in said input-output storage means per character code word, and means responsive to generation of said further group of pulses for conditioning said second sequence control means to generate another group of pulses.
72. A system as defined in claim 69 wherein said second sequence control means includes means for generating an additional pulse prior in time to the first of the pulses of said second group of actuating pulses, said first coupling means being responsive to said additional pulse to transfer all of the bits of a character code word previously stored in said input-output storage means to said utilization device, said input-output means thereafter being responsive to said second group of actuating pulses to enter all of the bits of another character code word from said intermediate memory to said input-output storage.
73. A system as defined in claim 35 wherein said first coupling means comprises means for receiving said multi-bit character code words in serial form at a nominal bit rate, wherein said logic means includes means for generating a pulse train at a frequency which is a high multiple of said nominal bit rate, dividing means responsive to said pulse train to generate a Second pulse train at a frequency equal to said nominal bit rate, means responsive to the first bit of an incoming character code word to generate an activating signal for said dividing means, said dividing means being operative to generate the first pulse of said second pulse train after a predetermined number of pulses of said first pulse train following said activating signal, and for generating succeeding pulses of said second pulse train at a frequencey equal to said nominal bit rate, means for activating said input-output storage means in response to said second pulse train to store incoming data bits in synchronism with the pulses of said second pulse train, and means for deactivating said dividing means after a predetermined number of pulses of said second pulse train have been generated.
74. A system as defined in claim 73 wherein said first coupling means includes means for receiving said multi-bit code word in parallel form, wherein said logic means includes means responsive to appearance of a character code word in parallel form in said first coupling means to generate said activating signal for said dividing means and also to generate a parallel data entry control signal, means responsive to said parallel data entry control signal to enter the bits of said incoming code word simultaneously into said input-output storage means, said input-output storage means thereafter being responsive to said second pulse train to transfer data stored therein into said intermediate memory on a bit-by-bit basis.
75. A system as defined in claim 74 wherein said input-output storage means has a capacity for storing at least two code words, and is operative in response to said parallel data entry control signal to enter the bits of an incoming code word in a first storage location, and is further responsive to said second pulse train to transfer a code word in said first storage location to said second storage location.
76. A system as defined in claim 35 wherein said tape drive means includes transport means for receiving a magnetic tape as said memory medium, and drive means for said tape transport, said drive means including means for operating said transport in a forward direction, means for operating said transport in a reverse direction, means cooperating with said transport for sensing the beginning of a tape, and means cooperating with said transport for sensing the end of a tape; and wherein said logic means includes means for actuating said forward drive means during data transfer between said principal memory and said intermediate memory, and means responsive to the sensing of the end of a tape for deactivating said forward drive means.
77. A system as defined in claim 76 wherein said logic means includes means responsive to an external rewind command to operate said reverse drive means, and means responsive to the sensing with the beginning of a tape for deactivating said reverse drive means.
78. A system as defined in claim 77 wherein said logic means includes means for establishing a tape erase operation sequence comprising means responsive to an external tape erase command to operate said forward drive means, means responsive to sensing of the end of the tape and to said tape erase command to deactivate said forward drive means and to activate said reverse drive means, means in second data transfer means responsive to said tape erase command to erase the tape, and means responsive to the sensing of the beginning of the tape and said tape erase command to terminate said erase operation sequence.
79. A system as defined in claim 76 further including means responsive to an external tape erase command for operating said tape drive means to erase all information stored on a tape being carried by said transport.
80. A system as defined in claim 79 wherein said logic means includes means responsive to an external error correction command to delete a character code word from said input-output storage means.
81. A system as defined in claim 76 whereIn said transport means includes means for receiving a magnetic tape cassette.
82. A system as defined in claim 35 wherein said logic means includes means responsive to an external error correction command for deleting the contents of said intermediate memory.
83. A system as defined in claim 35 wherein said input-output means further includes means coupled to said storage means to detect the existence of an error in a character to be transferred to a utilization device, and means responsive to detection of an error for preventing transfer of the erroneous code word.
84. A system as defined in claim 83 further including means responsive to detection of an error for suppressing the erroneous code word and for substituting therefor a desired code word.
85. A system as defined in claim 35 wherein said input-output means includes a shift register having a first group of stages defining a first character position and a second group of stages defining a second character position each character position having capacity for storage of one character code word; means responsive to an incoming character code word from an external data source for operating said shift register and said intermediate memory to enter said incoming code word into the first character position of said shift register through said first coupling means and to transfer a previously entered code word from said second character position one bit at a time to said intermediate memory through said first transfer means; said shift register second character position being connected to said second coupling means and said shift register first character position being connected to said first transfer means; and means in said logic means for activating said first transfer means and said second coupling means for transferring a code word previously entered in said shift register to said coupling means; and for transferring another code word from said intermediate memory to said shift register.
86. A system as defined in claim 35 wherein said input-output means includes a shift register having a first group of stages defining a first character position and a second group of stages defining a second character position, each character position having capacity for storage of one character code word; and means responsive to an incoming character code word from an external data source for operating said shift register and said intermediate memory to enter said incoming code word into the first character position of said shift register and to transfer a previously entered code word from said second character position one bit at a time to said intermediate memory.
87. A system as defined in claim 86 wherein said first coupling means includes means for connecting the bits of an incoming character code word simultaneously to respective stages of said first character position and wherein said logic means includes means for entering said code word into said first character position and for thereafter advancing said shift register a sufficient number of times to transfer said code word from said first character position prior to entry of another character code word.
88. A system as defined in claim 86 wherein said input-output means includes means responsive to the bits of an incoming code word to generate an additional bit, the value of which is a function of the parity of the incoming code word, and means for entering said additional bit in one of the bit positions of said first character position, together with the associated code word.
89. A system as defined in claim 86 wherein said first coupling means includes means for accepting information from said external source in serial form, one bit at a time, and wherein said logic means includes means for entering each bit into the first stage of said shift register and means responsive to the first bit of an incoming character code word for advancing said shift register in synchronism with said incoming bit a sufficient number of times to enter said entIre character into respective bit positions of said first character position.
90. A memory system as defined in claim 86 including means for providing an indication when a complete character is present in the stages of said second character position, and means for inhibiting transfer of data from said shift register to said intermediate memory when said indication is not present.
91. A system as defined in claim 35 wherein said input-output means includes a shift register having a first group of stages defining a first character position and a second group of stages defining a second character position, each character position having capacity for storage of one character code word; means responsive to an incoming character code word from an external data source for operating said shift register and said intermediate memory to enter said incoming code word into the first character position of said shift register and to transfer a previously entered code word from said second character position one bit at a time to said intermediate memory; and means responsive to the accumulation in said intermediate memory of an entire block of data for transferring said block of data one bit at a time to said principal memory.
92. A system as defined in claim 35 wherein said input-output means includes a shift register having a first group of stages defining a first character position and a second group of stages defining a second character position, each character position having capacity for storage of one character code word; means in said logic means responsive to an incoming character code word from an external data source for operating said shift register and said intermediate memory to enter said incoming code word into the first character position of said shift register and to transfer a previously entered code word from said second character position one bit at a time to said intermediate memory; means responsive to the accumulation in said intermediate memory of an entire block of data for transferring said block of data one bit at a time to said principal memory; means for transferring an entire block of data from said principal memory to said intermediate memory, means for transferring data from said intermediate memory to the first character position of said shift register one bit at a time; said second coupling means being operative to receive data from the second character position of said shift register, means responsive to entry of a character code word into said shift register for transferring a previously entered code word to said second coupling means; and means responsive to the transfer of an entire block of data from said intermediate memory to said second coupling means for transferring another block of data from said principal memory to said intermediate memory.
93. A system as defined in claim 35 wherein said first and second coupling means comprise means for receiving and transmitting multi-bit character code words in serial form at more than one nominal bit rate, wherein said logic means includes means for generating a pulse train at a frequency which is a high multiple of said nominal bit rate, means for selecting the nominal bit rate at which data is to be transmitted or received, dividing means responsive to said pulse train to generate a second pulse train at a frequency equal to said nominal bit rate; record control means including means for activating said first coupling means; means responsive to an incoming character code word to generate an activating signal for said dividing means, said dividing means being operative to generate the first pulse of said second pulse train after a predetermined number of pulses of said first pulse train following said activating signal, and for generating succeeding pulses of said second pulse train at a frequency equal to said nominal bit rate, means for activating said input-output storage means in response to said second pulse train to store incoming data bits in synchronism with the pulses of said seconD pulse train, and means for deactivating said dividing means after a predetermine number of pulses of said second pulse train have been generated; playback control means including means for activating said second coupling means, means responsive to a signal from a data utilization device for generating an activating signal for said dividing means, and means responsive to said second pulse train to transfer data from said intermediate memory to said input-output storage means and from said input-output storage means to said second coupling means.
94. A system as defined in claim 35 wherein said intermediate memory comprises a random access memory having a plurality of individually accessible memory sites, said random access memory being operable in storage and retrieval operating modes, and means for selectably activating said individual memory sites for storage or retrieval operation.
95. A system as defined in claim 35 wherein said intermediate memory comprises a plurality of the individually accessible memory sites, said intermediate memory being being operable in information storage and retrieval modes, means to address individual ones of said memory sites in a predetermined sequence; wherein siad logic means includes means to advance said addressing means, means to operate said intermediate memory in said information storage mode to enter information in successively addressed memory sites on a bit-by-bit basis; means for selectively activating and deactivating said first and second transfer means to enter data in said intermediate memory from said input-output means or said principal memory respectively; means to operate said intermediate memory in said information retrieval mode, and means for activating said first and second transfer means to accept data from said intermediate memory, and to transfer the same to said input-output means or said principal memory, respectively, on a bit-by-bit basis.
96. A system as defined in claim 95 wherein said addressing means comprises counting means, means for advancing said counting means, means responsive to the state of said counting means for actuating an individual one of the memory sites of said intermediate memory, means for resetting said counting means to a rest state; wherein said means to operate said intermediate memory in said retrieval mode comprises means to reset said counting means, and thereafter to advance said counting means through at least a portion of its counting cycle to read out the contents of said intermediate memory, means responsive to completion of transfer of an entire data block to reset said counting means.
97. A system as defined in claim 96 wherein said logic means further includes means responsive to initiation of said retrieval mode of operation for temporarily storing the count state of said counting means representing the number of characters comprising a data block, means for comparing the count state of said counting means with said stored count states as said counter is advanced, and means responsive to coincidence between the count state of said counting means and said stored count state for deactivating and resetting said counting means.
98. A system as defined in claim 35 wherein said logic means includes means for establishing a data acceptance rate compatible with the data rate of an external data source, means for operating said input-output means and said intermediate memory at said data rate in synchoronism with incoming data to accumulate said incoming data in said intermediate memory, means responsive to accumulation of an entire data block in said intermediate memory to activate said intermediate memory and said principal memory at an internal data transfer rate substantially exceeding said data acceptance rate to transfer said accumulated data block to said principal memory, and means for inhibiting operation of said intermediate memory at said data acceptance rate while said data block is being transferred to said principal memory.
99. A system as defined in claim 96 further including means to permit accumulation of new incoming data in said input-output storage means while a previous data block is being transferred to said principal memory, said internal data transfer rate being sufficiently high in relation to said data acceptance rate to permit transfer of an entire data block to said principal memory while data is accumulated in said input-output storage means at said data acceptance rate.
100. A system as defined in claim 35 wherein said logic means includes means for establishing an external data transfer rate compatible with the data rate of an external data utilization device, means for establishing an internal data transfer rate substantially exceeding said external data transfer rate, means for operating said intermediate memory and said principal memory at said internal data transfer rate to enter an entire block of data from said principal memory into said intermediate memory, means for operating said intermediate memory and said input-output device at said external data transfer rate to transfer said data block to said utilization device, means responsive to transfer of said entire data block from said intermediate memory for operating the principal memory and said intermediate memory at said internal data transfer rate to enter a new data block into said intermediate memory, means for operating said input-output device at said external data transfer rate while said new data block is being entered into said principal memory, and means for inhibiting operation of said intermediate memory at said external data transfer rate while said new data block is being entered.
101. A system as defined in claim 100 further including means for determining the presence or absence of data in said input-output storage means, and means responsive to entry of a new data block in said intermediate memory and to the absence of data in said input-output storage means for operating said intermediate memory and said input-output storage means at said internal data transfer rate for a sufficient time to load an initial portion of said new data block into input-output storage means, said internal data transfer rate being sufficiently high in relation to said external data transfer rate that entry of said new data block in said intermediate memory and loading of the initial portion of said new data block into said input-output storage means occasions essentially no interruption of data transfer to said utlization device.
102. A system as defined in claim 35 wherein each data block is identified by a recognition code comprising at least one initial character; and wherein said logic means includes means for establishing a search mode of operation for locating a particular one of the data blocks based on its particular recognition code.
103. A system as defined in claim 102 wherein said means for establishing said search mode of operation comprises reference character storage means, means for entering into said reference character storage means the recognition code of the data block to be identified, means for entering an entire data block into said intermediate memory from said principal memory; means for transferring an initial portion of said block of data from said intermediate memory to said input-output storage means, means for comparing the contents of said input-output storage means with said stored recognition code, means responsive to a match between said recognition code and the contents of said input-output storage means to terminate said search operation, and means responsive to failure of the contents of said input-output storage means to match said recognition code to initiate transfer of another block of data from said principal memory to said intermediate memory, and to repeat the comparison process.
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