Background of the Invention

Field of the Invention

This invention relates to a computer system, and more particularly, to such a system including a primary computer for processing digital information and an auxiliary service computer which serves to relieve the primary computer of certain auxiliary functions and enhance system operation.

Description of the Prior Art

In addition to executing the main program, digital processors must perform many auxiliary functions, such as: data transfer with peripheral equipment (i.e., terminals, printers); initiated go/no-go, or periodic self-test operations; and terminal interface program command execution from user and maintenance terminals. In conventional systems, the master central processing unit (CPU) executes these functions. If a peripheral needs attention, it interrupts the master. After completing the current instruction, the CPU responds by fetching the interrupt vector, storing the current program status, and executing the vector- defined service routine. When finished, the CPU restores the old status and continues with the main program. The CPU time spent in servicing the interrupt varies from several ten's to several hundred's of microseconds, excluding the time required for the actual service routine.

Communication with terminals, I/O ports, or printers slows down the master CPU since it interrupts the execution of the main program and requires execution of routines to interpret and format the I/0 data. Processor efficiency thus decreases with time spent servicing the interrupt. Consequently, it is desirable to reduce the CPU time spent in servicing peripherals.

Conventional processors use hardware (i.e., watchdog monitor, wraparound links, etc.) and software to test themselves. Obtaining high coverage is difficult because the processor test kernel (CPU, bus, memory, software) cannot check itself. A watchdog monitor can detect a limited percentage (-65%) of the failures. The ability to check, fully, the kernel is essential for achieving high test coverage.

In the maintenance or debug mode, interrupt service time is not important, since the master operates in non-real time. However, of concern is the hardware needed, such as the universal asynchronous receiver/transmitter (UART) required for serial I/O, and the counters required with the UART and watchdog monitor.

To date, for a computer system wherein its program is contained in read-only memory, initial software development has been a problem. Either the program had to be burned into a set of PROMs repetitively, as bugs have been corrected, or a means, such as an auxiliary RAM board, had to be constructed with a link to the software development station to down-load corrected software.

It is, therefore, an object of the present invention to provide an improved computer system capable of providing high coverage test capability, .including testing of the kernel and of affording an operator interaction with the primary computer with a minimal interruption to the real-time behavior of the primary.

It is a further object of the present invention to provide a computer system wherein the hardware needed to execute utility functions and translate terminal-generated commands is a minimum.

It is a further object of the present invention to provide a computer system capable of minimizing the interrupt period when servicing peripherals.

It is a further object of the present invention to provide a computer system wherein the portion of the operating system performing self-test, watchdog monitor and user interface functions is localized within the service computer.

It is a still further object of the present invention to incorporate down-loading capability into the system for program development purposes.

Other objects and advantages of the present invention will become apparent as the description thereof proceeds.

Summary of the Invention

In accordance with the present invention, there is provided a computer system. Included is a primary computer for processing digital information, and an interconnecting local bus. A service computer is connected to the primary computer through the local bus for enhancing the system by providing system hardware and software testing capabilities and for affording an operator interaction with the primary computer with insignificant interruption to the real-time behavior thereof.

In the preferred embodiment, the service computer is a microcomputer which includes a CPU, two real-time counters and a universal asynchronous receiver/transmitter.

Brief Description of the Drawing

In the accompanying drawing comprising Figs. 1A and 1B, there is shown in block diagram form the preferred embodiment of the computer system of the present invention.

Description of the Preferred Embodiment

In accordance with the present invention, and referring now to the drawing, there is shown the preferred embodiment of the computer system of the present invention. A primary computer 10 is provided for processing digital information. Primary computer 10 includes a central processing unit (CPU) 11, a program and data memory 12, a system bus interface 13, a clock 14, input/output device, receiver/transmitter 15, a user terminal 16, and a fast/slow PROM switch 17. Also included is interconnecting bus 20 and a service microcomputer 30 connected to the primary computer 10 through the bus 20 for enhancing the system by providing system hardware and software testing capabilities and for affording an operator interaction with the primary computer with insignificant interruption to the real-time behavior thereof. In the preferred embodiment, a single chip Zilog Z8 microcomputer with a serial I/0 port has been chosen as the service microcomputer.

The Zilog Z8 microcomputer 30 includes an 8-bit CPU, a 144 byte RAM, a 2000 byte ROM, two 8-bit counters and a univeral asynchronous receiver/ transmitter (UART). As shown in the drawing, bus control is passed between the two processors 11 and 30 by a master/slave protocol which mutually excludes one or the other from bus access. The slave or service computer 30 requests bus access by asserting the bus request line 41; the master or primary computer 11 grants access with the bus acknowledge signal 42.

In the serial 1/0 mode, the Z8 microcomputer UART converts from serial to parallel format, and the microcomputer 30 stores the data and makes intelligent decisions as to what to do with it. Only when necessary will the data be transferred to the master RAM, and if applicable, as a block.

In a typical input operation, the UART interrupts the service microcomputer 30 and the service microcomputer stores the data in its RAM. At the end of the message, the service microcomputer interprets the command, strips the command off, formats the data, and generates a bus request signal to the primary CPU 11, in the preferred embodiment a Zilog Z8001 or Z8002. Upon receipt of a bus acknowledge signal, it transfers the formatted data message to the master RAM. With this approach, the master CPU 11 is halted only a few microseconds when receiving a multiple byte message, rather than hundreds of microseconds as is the case with the conventional interrupt.

The service microcomputer 30 is also capable of transmitting data under direction from the master CPU 11. In a typical output operation, the Z8001 processor 11 places its output data in a buffer region in local memory. The Z8001 then instructs the Z8 service microcomputer 30 by writing an instruction into the Z8 port over the data bus 31. This interrupts the Z8 and causes it to execute the proper routine to format the data, then transmits the data out through the UART.

The service microcomputer 30 provides full test capability for the primary computer 10: initiated (foreground) or periodic (background) modes, and simple or high coverage go/no-go checks. However, because of its small (2K/4K) program memory, service microcomputer 30 will be limited to high coverage kernel testing: executing test routines and having the service microcomputer 30 compare the results with a predefined value or with the results computed in parallel by the main processor. To start these tests, service microcomputer 30 interrupts the primary computer 10 and points it to the test routine with the interrupt vector. If the test result is positive, the primary computer continues; if it is negative, the primary is halted and a fault is indicated.

Since the service processor 30 has its own clock, it can not only perform as watchdog monitor, but as an intelligent watchdog monitor. It starts a counter at the beginning of the master iteration period and interrupts the main processor 11 to request an immediate response. It indicates a failure when its timer overflows before the response, an acknowledge signal, is received. The watchdog monitor period can be altered simply by loading different limit values into the counter.

As those skilled in the art will appreciate, the computer system of the present invention has significant advantages. When used as an intelligent serial I/O device, service microcomputer 30 replaces a UART and a counter/timer chip. When used as an intelligent direct memory access device, the time during which the primary computer 10 is diverted from the main program is reduced at least an order of magnitude (microseconds instead of tens of microseconds). When performing as a system monitor, service microcomputer 30 can recognize and execute numerous primary computer system commands such as HALT, CONTINUE, RESET: and conventional debug commands such as DISPLAY, FILL, RUN, SINGLE STEP, INSPECT REGISTER, POWER-UP, etc. transmitted serially from the terminal 16 to the service computer. When operating as a tester, service microcomputer 30 can check the master or primary computer, including the kernel, with high coverage. It can also implement the watchdog monitor function without extra hardware. In addition to serial I/O, test, and monitor functions, the service microcomputer can perform many additional functions with little or no additional hardware.

Another feature of this single board computer system is real-time monitoring of CPU and memory operations. In a typical application, data words in the local memory are periodically read by the main processor 11. The bus request-bus acknowledge procedure is used to gain access to the local memory and the main processor is not interrupted, and in fact is barely slowed down - on the order of 10 microseconds per byte. Moreover, the monitoring is intelligent since the service processor can analyze and screen the snapshots, which it takes, of memory.

During the software development phase of the system, the fast/slow PROM switch 17 is used to inhibit the primary computer from attempting to execute its program. Instead, control is maintained by the service computer 30.

While a computer system has been described in what is presently considered to be a preferred embodiment of the invention, it will be apparent to those skilled in the art that various- changes and modifications may be made in the structure and in the instrumentalities utilized without departing from the true spirit and scope of the invention. For example, both primary and service computer may be on a single VLSI chip. Furthermore, a 16-bit microcomputer may be used as the service computer to reduce complexity.