Data communication system
专利汇可以提供Data communication system专利检索，专利查询，专利分析的服务。并且PURPOSE: To speed up the processing and transfer of a packet and to simplify a procedure by using a two-port RAM where a half flag is provided in an output FIFO in a packet dispatcher.
CONSTITUTION: The output FIFO 12 uses the two-port RAM where the half flag(HF) is provided, and a certain packet is detected to be not empty (EF) in an input FIFO11 and that half the packet becomes empty is detected in the half flag from the output FIFO12, whereby a continuous processing can be executed with respect to the subsequent packet. Input information is inputted to the input FIFO11 in the packet dispatcher 10, a prescribed read processing is executed, processed information is transmitted to the output FIFO12, and the packet processing and transfer are continuously executed by the detection of the half flag. For smoothly executing the continuous action, input status registers(ISR) 13
1 ∼13
n showing the units of the number of input data to be stored from a control part 6 are provided in graphic processing units 2
1 ∼2
n which supply the outputs of the output FIFO12 in parallel.
COPYRIGHT: (C)1989,JPO&Japio，下面是Data communication system专利的具体信息内容。
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