Data processing system with variable prefetch and replacement algorithms
阅读：238发布：2024-01-15
专利汇可以提供Data processing system with variable prefetch and replacement algorithms专利检索，专利查询，专利分析的服务。并且A data processing system using a high speed buffer storage to interface main storage with a central processing unit. Algorithms for the purpose of prefetching the next sequential line from main storage to the high speed buffer and for replacement of existing lines in the high speed buffer may be dynamically modified relative to the type of program being executed by the use of a system console unit.，下面是Data processing system with variable prefetch and replacement algorithms专利的具体信息内容。
1. A data processing system comprising, a processing unit, for providing addresses of locations to be accessed, main storage having a plurality of addressable locations, buffer storage having a plurality of addressable locations for coupling said processing unit to said main storage, addressing means for storing a current address for accessing said buffer storage, control means for controlling the sequencing of addresses to said first addressing means for accessing said buffer store, detecting means for detecting the accessing of said buffer storage by said first addressing means to determine if a preselected criteria is met, means, responsive to said detecting means and to said control means, for causIng said addressing means to access said buffer storage with an address and at a buffer store location determined in response to said preselected criteria, means for changing said preselected criteria whereby the conditions under which information is to be stored in said buffer storage are altered.
2. A data processing system comprising, a processing unit, for providing addresses of locations to be accessed, main storage having a plurality of addressable locations, buffer storage having a plurality of addressable locations for coupling said processing unit to said main storage, addressing means for storing a current address for accessing said buffer storage, control means for controlling the sequencing of addresses to said first addressing means for accessing said buffer store, detecting means for detecting the accessing of said buffer storage by said first addressing means to determine if a preselected criteria is met, address store means for storing a prefetch address, said address store means connected to said addressing means, means, responsive to said detecting means and to said control means, for gating said prefetch address from said address store means to said addressing means for accessing said buffer storage with said prefetch address when said preselected criteria is met, means for changing said preselected criteria whereby the conditions under which information is to be stored into said buffer storage are altered.
3. A data processing system comprising, a processing unit, for providing addresses of locations to be accessed, main storage having a first plurality of addressable locations, first addressing means for accessing main storage, buffer storage having a second plurality of addressable locations smaller than said first plurality of addressable locations for coupling said processing unit to said main storage, second addressing means for accessing said buffer storage with a current address, control means for controlling the sequencing of addresses to said first addressing means for accessing said buffer store, detecting means for detecting the accessing of said buffer storage by said first addressing means to determine if a preselected criteria is met, address store means for storing a prefetch address for prefetching information from said main storage for storage in said buffer storage, means, responsive to said detecting means and to said control means, for gating said prefetch address from said address store means to said first and second addressing means for accessing said main storage and said buffer storage with said prefetch address when said preselected criteria is met to transfer information from said main storage to said buffer storage, means for changing said preselected criteria whereby the conditions under which information is prefetched to said buffer storage are altered.
4. The system of claim 3 wherein, said control means includes means for forming said addresses as byte addresses and means for sequencing a plurality of contiguous byte addresses in sequencing a line of addresses where each line of addresses includes a predetermined number of byte addresses, said address store means including means for forming said prefetch address as the next contiguous line of addresses after the line of addresses including said current address, said detecting means including means for detecting when said current address is between predetermined ones of said byte addresses, for establishing said preselected criteria as the condition that said current address is between said preselected byte addresses, whereby said control means causes the next contiguous line of addresses to be prefetched from main storage and stored in said buffer storage.
5. The system of claim 3 wherein, said means for changing includes a programmable computer connected for monitoring said data processing system.
6. The system of claim 3 wherein, saiD detecting means includes means for detecting when said current address is within any quarter of the four quarters which comprise a line of contiguous addresses.
7. The system of claim 1 wherein said detecting means includes means for sensing when said buffer storage is full at current locations addressed by said current address and means for sensing the oldest information in said current locations whereby the oldest information is replaced.
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