Resolution of address information in a content addressable memory专利检索-内容可寻址存储器随机存取存储器资料储存系统专利检索查询-专利查询网

Resolution of address information in a content addressable memory

阅读：751发布：2022-04-03

专利汇可以提供Resolution of address information in a content addressable memory专利检索，专利查询，专利分析的服务。并且An address resolver for encoding the addresses of flagged information stored in an electronic memory. A matrix of cross conductors interconnected by diodes in the form of a binary tree has the 2n input conductors connected to 2n different two-state storage devices and the n output conductors connected to n AND gates. Under the control of a central processor, selected storage devices are set to indicate the location of the flagged information. The diodes are biased in one of two directions depending on whether the storage devices are set or reset. The bias on the diodes is detected by the AND gates and the results are stored in a register to indicate the highest address.，下面是Resolution of address information in a content addressable memory专利的具体信息内容。

权利要求

1. A resolver for determining in sequence the n digit binary addresses of 2n memory locations each having a flag-bit means associated therewith comprising; 2n storage means, each connected to a different one of said flag-bit means for assuming one of two stable states under the control of said flag-bit means; logic means including a matrix of cross conductors interconnected by diodes in the form of a binary tree connected to said storage means for determining in sequence the addresses of those said memory locations having the associated storage means in said one stable state; and output register means for registering the addresses determined by said logic means.

2. A resolver for determining in sequence the addresses of a plurality of memory locations each having a flag-bit means associated therewith comprising; an array of cross conductors having 2n input conductors and n output conductors, where 2n is the number of said memory locations; a plurality of diodes interconnecting said 2n input conductors and said n output conductors in the form of a binary tree; biasing means connected to said output conductors for providing a source of bias potential to said diodes; a plurality of two-state storage means, each connected to a different one of said flag-bit means, for changing from a first stable state to a second stable state under the control of the associated flag-bit means; each said two-state storage means having the output thereof connected to a different one of said 2n input conductors for establishing the condition of the bias on said diodes connected thereto; said diodes having one condition of bias when the associated two-state storage means is in a first stable state and having a second condition of bias when the associated two-state storage means is in a second stable state; output logic means connected to said N output conductors for determining the bias on said diodes starting from one end of said tree and proceeding sequentially to the other end of said tree; and output storage means for storing sequentially the associated addresses of said two-state storage means in said second stable state.

3. The device according to claim 2 wherein, said output logic means includes gate means connected to each of said n output conductors for detecting in sequence if any of the diodes connected thereto are in said second condition of bias; said output storage means having a plurality of digit storage means each connected to one of said gate means for assuming a predetermined stable state if the associated gate means detects a diode in said second condition of bias; and reset means connected to the output of each said digit storage means fore resetting all said two-state storage means connected to those input conductors not interconnected to the associated output conductor by one of said diodes.

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Resolution of address information in a content addressable memory

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