Defect-tolerant digital memory system
阅读：213发布：2022-04-05
专利汇可以提供Defect-tolerant digital memory system专利检索，专利查询，专利分析的服务。并且A defect-tolerant memory system has means for determining when memory operations are addressed to locations that are defective, and for directing these operations to spare memory locations in a main memory. A content addressable memory is provided which has an argument section for storing the addresses of defective locations in the main memory, and a function section for storing a substitute address for each of the defective locations. When the content addressable memory determines that an addressed memory location of the main memory is one whose address is stored in its argument section, it directs the memory operation to a substitute location which has been assigned to that defective main memory location in its function section, thus enabling bypassing of the defective memory location.，下面是Defect-tolerant digital memory system专利的具体信息内容。
1. In digital memory apparatus, the combination of A. a first memory having plural information-storing locations and means for addressing the storing locations thereof, B. a memory address register connected for receiving addresses of storage locations in said first memory, C. a second register for storing the addresses of locations in said first memory which are not to be used, D. an auxiliary memory having storage locations capable of registering the contents of said first memory locations that are not to be used and having means for addressing the storage locations thereof, E. a third register for storing the addresses of storage locations in said auxiliary memory, F. means for generating a first timing signal and a second timing signal, said second timing signal following the initial appearance of said first timing signal, G. comparator means connected with said memory address register and with said second register for comparing address contents thereof in response to said first timing signal and producing a first or a second signal in response to said second timing signal according to whether the contents are the same or different, respectively, H. means controlled by said first signal for supplying the contents of said third register to the addressing means for said auxiliary memory during the appearance of said second timing signal, and I. means controlled by said second signal for supplying the contents of said memory address register to the addressing means for said first memory during the appearance of said second timing signal.
2. The combination as defined in claim 1 in which A. each location in said third register is associated with a location in said second register, and B. said comparator means further responds to the identity between an address in said memory address register and an address in said second register to actuate a location in said third register associated with the second register location storing the matching address, and C. said means controlled by said first signal supplies the contents of said actuated location in said third register to the addressing means for said auxiliary memory.
2. having a function section providing a storage location associated with each location in said argument section and for storing the address of a location in said auxiliary memory, and
3. responding to an applied address signal identifying the contents of a location in said argument section to cause an address stored in the corresponding location in said function section to be applied to said memory addressing means, and D. means for inhibiting the utilization of a defective location in said argument section.
3. The combination as defined in claim 2 comprising further register means having plural locations each location of said further register means is associated with a different second register location, and each location of said further register means is adapted to inhibit said generating of said first or second signal when said location of said further register means is in a selected state.
4. A memory system comprising A. a first memory having plural information-storing locations and means for addressing the locations thereof, B. memory address register means for receiving addresses of storage locations in said first memory. C. a second register having locations for storing the addresses of locations in said first memory which are not to be used, D. an auxiliary memory having storage locations capable of storing the contents of said first memory locations that are not to be used and having means for addressing the locations thereof, E. a third register having locations for storing the addresses of locations in said auxiliary memory, F. switching means connected for operation in a first manner to supply said addressing means for said first memory with a location address responsive to the contents of said memory address register means, and alternatively for operation in a second manner to supply said addressing means for said auxiliary memory with an address responsive to the contents of a location in said third register, G. comparator means connected for comparing the address contents of said memory address register means with the address contents of said second register locations, and for operating said switching means in said first manner when the contents of one second register location and said memory address register means are different and in said second manner when said contents of one second register location and said memory address register means are the same, and H. forth register means having a plurality of locations each associated with a different second register location, each of said fourth register means locations adapted to inhibit said comparator means from operating said switching means when a location of said fourth register means is in a selected state.
5. Apparatus for substituting auxiliary storage locations for defective storage locations in an addressable memory, said apparatus comprising: A. an auxiliary memory having addressable storage locations, B. memory addressing means connected to address said locations in said auxiliary memory, and C. content addressable memory means
6. In a data processing memory system having a set of addressable locations, the combination of A. register means having locations each of which stores the identification of one location of said set of addressable locations which is not to be used, B. addressable auxiliary locations each of which stores the same amount of information as a location of said set of addressable locations and each of which is associated with one location in said register means, and C. means responsive to the addressing of a first location whose identity is stored in a location of said register means for addressing the auxiliary location associated with that register location in lieu of addressing said first location, and D. further information storiNg means for storing the identification of each location of said register means which is not to be used and for inhibiting the addressing of said means responsive to the addressing of a first location when it stores the identification of a location of said register means that stores the identification of an addressed first location.
7. A memory system, comprising: A. a main memory having storage location addressing means and potentially defective storage locations, B. a memory address register, C. a second register comprising a plurality of locations for storing the addresses of defective locations in said main memory, D. an auxiliary memory having storage location addressing means and at least one storage location for each location in said second register for storing the contents of a storage location in said main memory, E. a third register comprising at least one storage location for each location in said second register for storing the addresses of storage locations in said auxiliary memory, F. comparator means connected to said memory address register and to each location in said second register for comparing address contents, G. means controlled by said comparator means for producing a location identification signal when the contents of a location in said second register are the same as the contents of the memory address register, H. means controlled by said comparator means for producing a control signal when the contents of the memory address register are not the same as the contents of any location in said second register, I. means controlled by said control signal for supplying the contents of said memory address register to the addressing means for said main memory, and J. means controlled by said location identification signal for supplying the contents of a different location in said third register for each identification signal to the addressing means for said auxiliary memory, wherein the improvement comprises: K. signal distributing means settable to a different state for each storage location in said second register, L. first signal generating means for producing a digital signal corresponding to an address in said main memory, M. second signal generating means for producing a digital signal corresponding to an address in said auxiliary memory, and N. means controlled by said first and second signal generating means and said distributing means for loading a different pair of locations in said second register and said third register with the digital signal produced by said first signal generating means and the digital signal produced by said second signal generating means, respectively, in each state of said distributing means.
8. The system of claim 7 further comprising: A. a one-bit register for each pair of locations in said second and said third registers selected by said distributing means for registering the entry of signals into said pair of locations, and B. means controlled by said distributing means for storing a signal in each one-bit register as the corresponding location pair is loaded.
9. The system of claim 8, further comprising: A. a second one-bit register for each of said pairs of locations, B. means for selectively storing signals in said second one-bit register to indicate a defective location, and C. means controlled by each of said second one-bit registers for preventing the loading of the associated location pair when a signal is stored in said second one-bit register.
10. A content addressable memory comprising: A. an argument section including a plurality of storage locations, each of said locations including a plurality of bistable means having first and second states, each of said bistable means set in a predetermined one of said first and second states in accordance with a signal loaded therein; B. means for receiving memory address signals, said signals includiNg a plurality of binary representations proportional to the number of bistable means in each of said locations; C. first gate means responsive to a first timing signal for comparing each of said binary representations with the states of respective bistable means in each of said plurality of locations; D. a plurality of second gate means each for producing a control signal when each of the states of said plurality of bistable means in one of said locations compares with the respective binary representations of said memory address signals; E. a function section including a plurality of storage locations corresponding to the locations in said argument section, each of said locations of said function section including a plurality of storage elements, each of said elements set in a predetermined one of first and second states; F. third gate means responsive to a produced control signal for transferring to a utilizing device an address represented by the states of elements in a function section location corresponding to the argument section location of said produced control signal; and G. means for inhibiting the producing of at least one of said control signals thereby causing the argument section location corresponding to said inhibited control signal to be unusable.
11. A memory as defined in claim 10 wherein said means for inhibiting includes a second plurality of bistable means corresponding in number to the number of argument section locations, each of said bistable means in said second plurality coupled to a corresponding gate in said plurality of second gate means and set to inhibit said corresponding gate in accordance with those argument section locations which are unusable.
12. A content addressable memory comprising: A. an argument section including a plurality of storage locations, each of said locations including a plurality of bistable means having first and second states, each of said bistable means set in a predetermined one of said first and second states in accordance with a signal loaded therein; B. means for receiving memory address signals, said signals including a plurality of binary representations proportional to the number of bistable means in each of said locations; C. first gates means responsive to a first timing signal for comparing each of said binary representations with the states of respective bistable means in each of said plurality of locations; D. a plurality of second gate means each for producing a control signal when each of the states of said plurality of bistable means in one of said locations compares with the respective binary representations of said memory address signals; E. a function section including a plurality of storage locations corresponding to the locations in said argument section, each of said locations of said function including a plurality of storage elements, each of said elements set in a predetermined one of first and second states; F. third gate means responsive to a produced control signal for transferring to a utilizing device an address represented by the states of elements in a function section location corresponding to the argument section location of said produced control signal; and G. a plurality of means for indicating whether said argument section locations are loaded with signals, said plurality of means for indicating corresponding in number to the number of said argument section locations.
13. A memory as defined in claim 12 further comprising fourth gate means coupled to receive said control signals produced by said second gate means, for generating a first state switching signal in response to the presence of at least one control signal and a second timing signal for generating a second state switching signal in response to the absence of all control signals and the presence of said second timing signal.
14. A memory as defined in claim 13 further comprising: A. a main memory including a Plurality of good storage locations and some defective storage locations; B. wherein said argument section location includes the addresses of said defective storage locations; C. an auxiliary memory including storage locations capable of registering the contents of said defective main memory locations; D. wherein said function section locations include the addresses of said auxiliary memory storage locations; E. means for addressing said main memory with said memory address signals when said second state switching signal is generated; and F. means for addressing said main memory with said address represented by the states of said elements in said function section when said first state switching signal is generated.
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