BACKGROUND OF THE INVENTION

The present invention relates to automatic focusing apparatus, and more particularly to automatic focusing apparatus which uses two different types of focus detectors.

Apparatus for automatically focusing an image of an object formed by an optical system, such as a lens, are known and are used in various types of optical imaging equipment, such as self-focusing cameras. Such apparatus generally operate by detecting the degree of focus of the image in the focal plane of the imaging system and by appropriately altering the focus of the optical system, usually with a servomotor, to maximize the degree of focus. One known technique for detecting focus is by monitoring with photosensors the relative displacement of two images of the same object formed by two optical systems through two different optical paths. The relative image displacement technique of focus detection is illustrated in FIGS. 1 and 2. Referring now to FIG. 1, there is shown schematically a focus detection system 100 based on the relative image displacement technique. The apparatus includes two optical imaging systems 107 and 108 each comprising a lens 109 and 110 for forming an image of an object 111 in a respective focal plane 112 and 113. Situated in the focal plane of each imaging system is an array of photosensors 101 and 102. Each photosensor in the array is adapted to sense the light intensity in a respective portion of the focal plane and to provide an electrical signal which is representative of the sensed light intensity. The signals from the photosensors in the two arrays 101 and 102 are provided to a relative image displacement detection circuit 114.

The image of the object 111 formed by the imaging system 107 is displaced relative to the one formed by the imaging system 108, owing to the differences between the optical paths 115 and 116 through which the images are respectively formed. The optical path 116 is coincident with the optical axis of the lens 110. As such, the image formed by the imaging system 108 is centered on the photosensor array 102. By contrast, the optical path 115 is at an angle with respect to the optical axis of the lens 109. Consequently, the image formed by the imaging system 107 is shifted to the left of the photosensor array 101. However, the angle between the optical path 115 and the optical axis of the lens 109 can be altered by means of a suitably shaped prism 117 in the optical path 115. Therefore, the relative displacement between images formed by the imaging systems 107 and 108 can be eliminated by an appropriate rotation of the prism 117. In the system of FIG. 1, the rotation of the prism 117 to eliminate the relative image displacement is accomplished by means of a servosystem 118 which receives a displacement signal from the image displacement detection circuit 114. The servosystem 118 provides the quantities g and h, which represent the sense and magnitude of rotation of the prism 117 required to eliminate the relative image displacement. The quantities g and h, which are derived from conventional encoding circuits within the servosystem 118, can in turn be used to alter the focus of an objective lens in the imaging equipment by means of another appropriate servosystem.

Turning now to FIG. 2, there is depicted a schematic diagram of the photosensor arrays 101 and 102 and the image displacement detection circuit 114 of the apparatus of FIG. 1. For purposes of illustration, the photosensor arrays 101 and 102 each comprise five photosensors d₁ -d₅ and d₁ '-d₅ ', respectively. The image 104 being sensed by the array 102 is shown as being centered in that array, while the image 103 being sensed by the array 101 is shown as being shifted towards one end of the array. The outputs of corresponding pairs of photosensors from each array are provided to respective differential amplifiers 119-123. The outputs of the differential amplifiers 119-123 are received by a summing circuit 106, which provides an output signal representative of the degree of relative displacement of the images sensed by the photosensor arrays 101 and 102.

The relative image displacement focus detection technique is advantageous in that it can be used to control automatic focusing apparatus even when the imaging equipment is far out of focus. However, the relative image displacement technique has the problem in that it lacks sufficient accuracy for fine focusing of the imaging equipment, particularly when the image has a repetitive pattern such as a striped or checkered pattern.

Another known technique for detecting focus in an imaging system, which overcomes the disadvantages of the relative displacement detection technique, is to monitor the contrast of the image (i.e., the relative intensities of different portions of the image) with an array of multiple photosensors arranged in the focal plane of the system. According to the contrast detection technique, focus of an image is obtained when the contrast of the image, as detected by the array of photosensors, is maximized. However, prior automatic focusing apparatus using the contrast detection technique have the problem in that the circuitry used for contrast detection generally is required to perform complex weighting functions on the signals provided by the photosensors and, consequently, is often very complicated and costly to manufacture. Therefore, a need exists for automatic focusing apparatus based on the contrast detection technique which eliminates the need for complex and expensive circuitry.

SUMMARY OF THE INVENTION

Accordingly, the problems of the prior art discussed above are substantially alleviated by the present invention which is an automatic focusing apparatus for an imaging system, such as a camera, which includes an optical system, such as a lens, for forming an image of an object at the focal plane of the imaging system. The automatic focusing apparatus, includes an image contrast detector comprising a plurality of detector/converter elements arranged in an array at the focal plane. Each of the detector/converter elements senses the light intensity in a respective portion of the image and provides a pulse signal having a pulse-width which is related to the light intensity sensed by the detector/converter element, e.g., the pulse-width may be directly or inversely proportional to the sensed light intensity. The pulses from the plurality of detector/converter elements are received by a detection circuit which derives a digital quantity indicative of the difference between the maximum and minimum pulse-widths of the pulses from the detector/converter elements. The digital quantity is provided to control system comprising a comparator, a motor controller and a servomotor for appropriately altering the focus of the optical system to substantially maximize the difference between the maximum and minimum pulse-widths of the pulses provided by the detector/converter elements.

In an illustrative embodiment of the present invention, a relatively large number, n, of detector/converter elements are arranged in the focal plane of the imaging system. Each detector/converter element comprises a photodiode which provides a photocurrent approximately proportional to the light intensity received by the photodiode, a capacitance connected to the photodiode such that the photocurrent of the photodiode acts to discharge the capacitance, and an inverter connected to receive the voltage across the photodiode. The capacitance is initially discharged, causing the voltage across the photodiode to be at a "high" logic level and the inverter to provide a "low" logic level at its output. Thereafter, the capacitance is charged by the photocurrent of the photodiode, and the voltage across the photodiode decreases. When the voltage across the photodiode drops below the threshold voltage of the inverter, the output of the inverter switches to a "high" logic level. Thus, the detector/converter element provides a negative-going pulse having a pulse-width which is approximately inversely proportional to the light intensity received by the photodiode. The pulse from each detector/converter element is received by a respective input of an n-input OR gate and also by a respective input of an n-input NAND gate. The outputs of the n-input OR gate and the n-input NAND gate are provided to a 3-input NAND gate, which also receives a sequence of periodic clock pulses from an oscillator. The period of the clock pulses is relatively short compared to the pulse-widths of the pulses from the detector/converter elements. The output of the 3-input NAND gate is provided to a counter which counts the clock pulses passed by the 3-input NAND gate during a predetermined counting interval and provides the binary state of the counter at the end of the counting interval. The binary state of the counter is stored in a first register. A comparator compares the contents of the first register with the contents of a second register storing the binary state of the counter at the end of a previous counting interval. The comparator causes the larger of the two quantities compared to be stored in the second register and provides a digital output representative of the difference between the two quantities. The digital output from the comparator is provided to the motor controller, which derives therefrom the appropriate control signals to the servomotor for altering the focus of the optical system to maximize the quantity stored in the second register and to reduce the magnitude of digital output from the comparator to be less than a predetermined value.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic illustration of a relative image displacement focus detection apparatus;

FIG. 2 is a schematic diagram depicting the photosensor arrays and the image displacement detection circuit used in the apparatus of FIG. 1;

FIG. 3 is a diagram schematically illustrating an optical imaging system and an array of detector/converter elements situated in the focal plane of the imaging system;

FIG. 4 is a two dimensional graphical representation of the intensity distribution of an exemplary image as detected by an array of detector/converter element in the focal plane of the imaging system;

FIG. 5 is a schematic diagram illustrating four alternative circuit configurations for the detector/converter element, which senses light and provides a pulse having a pulse-width approximately inversely proportional to the intensity of the sensed light;

FIG. 6 is a schematic diagram of the detection circuit for deriving a digital quantity representative of the difference between the maximum and minimum pulse-widths of the pulses from the detector/converter elements;

FIG. 7 are waveforms representative of the signals at certain nodes of the detection circuit of FIG. 6 and is explanatory of the operation of the detection circuit;

FIG. 8 is a schematic block diagram of an automatic focusing apparatus according to the present invention;

FIG. 9 is a schematic block diagram of a motor control circuit suitable for use in the automatic focusing apparatus of FIG. 8; and

FIG. 10 is a schematic block diagram of an alternative configuration for a motor control circuit suitable for use in the automatic focusing apparatus of FIG. 8.

DETAILED DESCRIPTION

Referring now to FIG. 3, there is shown an imaging system 100 comprising an optical system 6 adapted to form the image of an object (not shown) at a focal plane 30 thereof (represented in two-dimensions in the depiction). The optical system may be a conventional arrangement of refracting or reflecting optical components for projecting light reflected from the object onto the focal plane at an appropriate magnification. The details of the optical system are not important to the present invention except that the focus of the optical system must be alterable by some appropriate means. Typically, the focus of a conventional optical system is altered by moving one or more of the optical components of the system closer to or further away from the focal plane of the imaging system. According to the present invention, an image contrast detection system which includes an array 5 of n (n is a relatively large whole number) detector/converter elements D₁ -D_n is positioned at the focal plane of the imaging system is used. Each of the detector/converter elements D₁ -D_n senses the light in a respective portion of the image at the focal plane and provides a pulsed signal at its output, the pulsed signal having a pulse-width which is related to the intensity of the light sensed. Although the array 5 of detector/converter elements is represented as being two-dimensional in the figures, it is contemplated that a three-dimensional array will be used in many cases.

Turning now to FIG. 4 there is shown a curve 7 which is a two-dimensional representation of the intensity distribution of an exemplary image at the focal plane. The same reference numerals used in FIG. 3 are again used on FIG. 4 to denote like components or parts of the apparatus. Each of the detector/converter elements in the array 5 is arranged to sense the average light intensity in a respective portion of the image, the average intensity being represented by the bars drawn in broken lines. In automatic focusing apparatus based on image contrast detection, the degree of focus of an image is determined by the detection of the contrast of the image, and the image is deemed to be in focus when the contrast of the image is maximized. The contrast of an image is defined as the difference in light intensity between the brightest and the darkest portions of the image, and may be represented graphically by the quantity ΔI in FIG. 4. The quantity ΔI will be relatively small when the image is out of focus but will have its maximum value when the image is in focus. Since the detector/converter elements in the array 5 provide pulsed signals having pulse-widths which are related to the light intensity in respective portions of the image, the difference between the maximum and minimum pulse-widths of the pulses is related to the quantity ΔI and, therefore, is also indicative of the degree of focus of the image.

Referring now to FIG. 5, there are shown schematic diagrams of four alternative circuit configurations (a)-(d) for the detector/converter element in accordance with the present invention. Each configuration includes a photodiode 2, a capacitance 3 connected to the photodiode and an inverter 4 connected to the common node between the photodiode 2 and the capacitance 3. Upon receiving light, the photodiode conducts a photocurrent i, which is approximately proportional to the intensity of the light received. In circuit (a), the photodiode is connected between a voltage supply 1 and the capacitance 3. The other terminal of the capacitance 3 is connected to ground. The capacitance 3 is initially discharged by switching means connected across the capacitance. For simplicity of the depiction, the switching means, which may for example be a field-effect transistor, is omitted from the figure. The use of such switching means to establish an initial state in a digital circuit is well known. Under the above conditions, the input voltage V₁ of the inverter 4 is initially zero volts, and the output O of the inverter is initially at a "high" logic level of approximately the supply voltage V. Owing to the light received by the photodiode 2, a photocurrent i flows through the photodiode to charge the capacitance 3 and cause the voltage V₁ to increase according to the relationship

V1 =(1/C)∫idt.                                   (1)

When the voltage V₁ exceeds the threshold voltage of the inverter 4, the output O of the inverter switches to a "low" logic level of approximately zero-volts. Thus, the circuit (a) provides a positive-going pulse having a pulse-width which is approximately inversely proportional to the light intensity received by the photodiode 2.

In circuit (b), the capacitance 3 is connected between the voltage supply 1 and the cathode of the photodiode 2. The anode of the photodiode is connected to ground. Initially, the capacitance is discharged by switching means coupled across the capacitance. Once again, for simplicity of the depiction, the switching means is omitted from the figure. Under the above conditions, the output O of the inverter is initially at a "low" logic level by virtue of the input voltage V₁ of the inverter being at the supply voltage V. Thereafter, the photocurrent i flowing through the photodiode 2 charges the capacitance causing V₁ to decrease. When V₁ drops below the threshold voltage of the inverter 4, the inverter output O switches to a "high" logic level. Thus the circuit (b) provides a negative-going pulse having a pulse-width which is approximately inversely proportional to the light intensity received by the photodiode 2.

In circuit (c), the photodiode 2 and the capacitance 3 are connected in parallel between the input of the inverter 4 and ground. The capacitance 3 is initially charged to the supply voltage V by switching means connected between the capacitance and the voltage supply. For simplicity of the depiction, both the switching means and the voltage supply are omitted from the figure. Under the above conditions, the output O of the inverter 4 is initially at a "low" logic level by virtue if its input voltage V₁ being initially at the supply voltage V. Thereafter, the photocurrent i flowing through the photodiode 2 causes the capacitance to discharge and the voltage V₁ to decrease. When the voltage V₁ drops below the threshold voltage of the inverter 4, the output O of the inverter goes to a "high" logic level. Thus, the circuit (c) provides a negative-going pulse having a pulse-width which is approximately inversely proportional to the light intensity received by the photodiode 2.

In circuit (d), the photodiode 2 and the capacitance 3 are connected in parallel between the voltage supply 1 and the input of the inverter 4. Initially the capacitance 3 is charged to the supply voltage V by switching means connecting the input of the inverter 4 to ground. Once again, for simplicity of the depiction, the switching means is omitted from the figure. Under the above conditions, the output O of the inverter is initially at a "high" logic level by virtue of its input voltage V₁ being initially at ground potential. Thereafter, the photocurrent i flowing through the photodiode 2 causes the capacitance 3 to discharge and the voltage V₁ to increase towards V. When the input voltage V₁ rises above the threshold voltage of the inverter 4, the output O switches to a "low" logic level. Thus, the circuit (d) provides a positive-going pulse having a pulse-width which is approximately inversely proportional to the intensity of light received by the photodiode 2.

Turning now to FIG. 6, there is shown a schematic diagram of a circuit 200 for receiving the signals from the outputs O₁ -O_n of the detector/converter elements D₁ -D_n and for deriving therefrom a digital quantity representative of the difference between the maximum and the minimum pulse-widths of the pulses provided by detector/converter elements. Reference characters and numerals used in FIGS. 3 and 4 are again used in FIG. 6 to denote like components and parts of the apparatus. The detector/converter elements D₁ -D_n have the circuit configuration (b) or (c) of FIG. 1 and provide negative-going pulses having pulse-widths which are approximately inversely porportional to the light intensities received by respective detector/converter elements. The signals from the outputs O₁ -O_n of the detector/converter elements D₁ -D_n are received by an n-input OR gate 8 and also by an n-input NAND gate 9. The outputs of gates 8 and 9 are received by a 3-input NAND gate 11, which also receives the output of an oscillator 10 providing a sequence of periodic clock pulses. The output of gate 11 is received by a counter which counts the clock pulses passed by gate 11 over a predetermined counting interval and provides its binary state at its output 31. The configurations for the detector/converter described above are disclosed in commonly assigned, copending U.S. patent applications bearing Ser. Nos. 483,247 (A25604) and 483,362 (A25621) filed contemporaneously with the present application.

The operation of the circuit of FIG. 6 is now explained with the aid of FIG. 7, which shows the waveforms at certain nodes of the circuit of FIG. 6. Referring now to FIG. 7, waveforms A-E are exemplary of the outputs O₁ -O_n of the detector/converter elements D₁ -D_n . For simplicity of the depiction, the waveforms of only five of the outputs O₁, O₂, O_i, O_j and O_n are illustrated in the present example. As may be seen from the waveforms A-E, at some initial time t_o, all of the detector/converter elements are initialized to have their outputs at "low" logic levels. Thereafter, the outputs return to a "high" logic level at different times depending on the light intensity received by the photodiodes in the respective detector/converter elements. It is noted that one of the outputs O_i returns to the "high" logic level at a time t_min, before any of the other outputs, while another of the outputs O_j returns to the " high" logic level at a time t_max, later than all the other outputs. Therefore, in the present example, outputs O_j and O_i provide pulses with the maximum and minimum pulse-widths, respectively.

Waveform F represent the periodic clock pulses provided by the oscillator 10. It is preferred that the period of the clock pulses be relatively short compared to t_min.

Waveform G represents the output of the n-input OR gate 8. It is noted that the output of gate 8 goes to a "low" logic level at t_o when all of its inputs (O₁ -O_n ) go to a "low" logic level. The outputs of gate 8 returns to a "high" logic level at t_min when one of its inputs (O_i) goes to a "high" logic level.

Waveform H represents the output of the n-input NAND gate 9. The output of gate 9 goes to a "high" logic level at t_o when all of its inputs (O₁ -O_n ) go to a "low" logic level. The output of gate 9 returns to a "low" logic level at t_max when all of its inputs (O₁ -O_n ) are at a "high" logic level.

Waveform I represents the output of the 3-input NAND gate 11. It is noted that gate 11 passes the clock pulses provided by the oscillator 10 during the time interval between t_min and t_max. At t_min gate 11 is enabled to pass the clock pulses by virtue of the outputs of gates 8 and 9 both being at "high" logic levels. Gate 11 is disable at t_max, when the output of gate 9 goes to a "low" logic level. Therefore, the number of clock pulses passed by gate 11 provides a measure of the difference between t_max and t_min. The number of clock pulses passed by gate 11 are counted by the counter 12 during a predetermined counting interval which begins before t_min and ends after t_max. The counter 12, therefore, provides a digital quantity (i.e., its binary state at the end of the counting interval) at its output 31 indicative of the difference between t_max and t_min.

Turning now to FIG. 8, there is shown a block diagram of an automatic focus apparatus according to an illustrative embodiment of the present invention. Block 13 represents the detection circuit illustrated in FIG. 6. The binary state of the counter 11 of the detection circuit after the most recent counting interval is stored in a register 17. Another register 18 stores the counter state from a previous counting interval. A comparator 19 compares the contents e of register 17 with the contents f of register 18 and provides a digital output l to a motor control circuit 16. The quantity l is equal to the difference between the quantities e and f. If the quantity in register 17 is larger than the quantity in register 18, the comparator also causes the contents of register 17 to be transferred to register 18, where it is stored for a subsequent comparison operation. Thus at the end of a focusing operation, the register 18 stores a digital quantity which represents the maximum difference between t_max and t_min, before the register 18 is reset by a RESET signal from the motor control circuit 16.

The apparatus of FIG. 8 also includes a second focus detection system 14 of the relative image displacement detection type, such as that described in FIGS. 1 and 2. An alternative configuration for a relative image displacement detection system is disclosed in a commonly assigned, copending U.S. patent application bearing Ser. No. 483,362 (A25621) filed contemporaneously with the present application. The second focus detection system 14 is used for rough focusing of the image, while the detection circuit 13 is used for fine focusing of the image. To the extent permissible, it is advantageous that the two focus detection systems 13 and 14 share common optical components and photodetectors. The second focus detector 14 provides signals g and h indicative of the direction in which the focus of the optical system is to be altered to bring the image into focus and the magnitude of such alteration, respectively. The signals g and h are both received by motor control circuit 16.

Prior to a focusing operation the register 18 is reset by a RESET signal from the motor control circuit 16. The servomotor 15, which alters the focus of the optical system is initially controlled via the motor control circuit 16 by the signals g and h from the second focus detector. The motor control circuit 16 provides a signal m to a display 20 for indicating the state of focus of the system. The operation of the servomotor continues in one direction under the control of the quantities g and h until the quantity l from the comparator 19 becomes negative. Thereafter, the motor control circuit causes the servomotor to reverse its direction, and the focusing operation continues in the opposite direction under the control of the quantity l until the magnitude of the quantity l becomes smaller than a predetermined value, such as zero or a very small number. At that point the focusing operation is completed. An automatic focusing apparatus which uses both a relative image displacement detection system and an image contrast detection system is disclosed and claimed in commonly assigned, copending U.S. patent application bearing Ser. No. 483,247.

Referring now to FIG. 9, there is shown a schematic block diagram of a motor control circuit 900 suitable for use in the automatic focusing apparatus of FIG. 8. The digital quantity l from the image contrast detection system is applied to a comparator 21 which provides a "low" logic level if l≧0 but provides a "high" logic level if l<0. The output of the comparator 21 is received by the S input of a S-R flip-flop 22 which provides a "high" logic level at its output Q when it is set by a "high" logic level from the comparator 21. Once set, the output of flip-flop 22 remains at a "high" logic level until the flip-flop is reset at the beginning of another focusing operation.

The digital quantity is also provided to an absolute value circuit 23 which provides the absolute value of l(|l|) at its output. The output of the absolute value circuit 23 is received by a scaling circuit 24 which multiplies the quantity l by a scale factor α. The reason for multiplying the quantity l the scale factor α is to compensate for the difference in magnitude between the output h of the relative image displacement detection system and the output l of the image contrast detection system. The output of the scaling circuit 24 is received by a switch 30 along with the digital quantity h from the relative image displacement detection system. The switch 30 is controlled by the output Q of the flip-flop 22, such that the switch 30 provides the quantity h when Q is a "low" logic level, but the switch 30 provides the quantity α|l| when Q is a "high" logic level.

The digital quantity h is also provided to a comparator 25, which compares h with a predetermined value h₀. The comparator 25 provides a "low" logic level when h≧h₀, but provides a "high" logic level when h<h₀. The output of the absolute value circuit 23 is provided to a comparator 6, which compares the quantity |l| with a predetermined value l₁. The comparator 26 provides a "low" logic level when |l|≧l₁, but provides a "high" logic level when |l|<l₁. The output of the comparator 25 is connected to one input of a 2-input AND gate 28. The other input of the AND gate 28 is connected to the output of the comparator 26 through an inverter 27. The output of the AND gate 28 is received by a bias circuit 29, which provides a quantity b when the output of the AND gate 28 is at a "high" logic level. Otherwise, the bias circuit 29 provides a zero output. The outputs of comparators 25 and 26 are also connected to another 2-input AND gate 34.

The output of the switch 30 is received by an adder circuit 31 along with the output of the bias circuit 29. The adder circuit provides the sum of the outputs of the switch 30 and the bias circuit 29 to a switch 32, which is controlled by the output of a switch 33. The switch 33 receives the output of the comparator 21 and the signal g from the relative image displacement detection system, and is controlled by the output Q of the flip-flop 22. The switch 33 provides the signal g to control the switch 32 when Q is at a "low" logic level, but the switch 33 provides the output of the comparator 21 to control the switch 32 when Q is at a "high" logic level. The switch 32 provides the output of the adder circuit 31 on one of its output terminals OUT1 when the control signal from the switch 33 is a "low" logic level, but the switch 32 provides the output of the adder circuit 31 on the other of its output terminals OUT2 when the control signal from the switch 33 is a "high" logic level. The quantities provided on output terminals OUT1 and OUT2 of the switch 32 after appropriate conversion causes the servomotor to rotate in the clockwise and counterclockwise senses, respectively, by magnitudes specified by the quantities provided.

At the beginning of a focus operation, the flip-flop 22 is reset by means not shown in FIG. 9. Therefore, the switch 30 initially provides the quantity h to the adder circuit 31, and the switch 33 initially provides the g signal to control the switch 32. Assuming that the imaging system is initially out of focus, the quantity h is greater than h₀. Furthermore, the quantity l is positive, and the quantity |l| is greater than l₁. Under these conditions the output of the AND gate 28 is at a "low" logic level, and the bias circuit 29 provides the quantity zero. Thus the quantity h is provided to one of the output terminals OUT1 or OUT2, depending on the state of the g signal, and a focus adjustment is made solely under the control of the relative image displacement detection system. As the focus adjustment of the imaging system is being made, i.e., by moving the components of the optical system in a direction specified by the g signal, the quantity h decreases until it becomes smaller than the predetermined value of h₀. At that point the imaging system is considered to be in focus by the relative image displacement detection circuit, and the quantity h becomes too small to cause any further focus adjustments of the imaging system. However, the imaging system may not at that point be considered to be in focus by the image contrast detection system, since the quantity |l| may still be greater than the predetermined value l₁. Under those conditions, where h is less than h₀ and |l| is greater than or equal to l₁, the AND gate 28 provides a "high" logic level to cause the bias circuit 29 to provide the quantity b, which is added to the quantity h by the adder circuit 31. Consequently, the focus adjustment of the imaging system continues in the same direction, as if the quantity h were still greater than h₀, until the quantity l becomes negative signifying that the point of focus as determined by the image contrast detection system has been past. When the quantity l becomes negative, the flip-flop 22 is set and provides a "high" logic level, causing the switch 33 to provide the output of the comparator 21 and the switch 30 to provide the quantity α|l|. Under these conditions, the focus adjustment of the imaging system proceeds solely under the control of the image contrast detection system, until the quantity |l| becomes less than l₁. At that point the AND gate 34 provides a "high" logic level and the focusing operation is terminated.

Turning now to FIG. 10, there is shown an alternative configuration 1000 for a motor control circuit suitable for use in the apparatus of FIG. 8. Reference numerals and characters used in FIG. 9 are again used in FIG. 10 to denote like components or parts of the circuit. As in the case of the circuit of FIG. 9, the quantity l from the image contrast detection system is received by a comparator 21 which provides a "low" logic level if l≧0 and provides a "high" logic level if l<0, and to an absolute value circuit 23. The output of the absolute value circuit 23 is received by a scaling circuit 24 and by a comparator 36 which provides a "low" logic level if |l|≧l₂, where l₂ is a first predetermined value, and a "high" logic level if |l|<l₂. The output of the absolute value circuit 23 is also received by a comparator 37 which provides a "high" logic level when |l|>l₃, where l₃ is a second predetermined quantity larger than l₂, and provides a "low" logic level when |l|≧l₃. Furthermore, the output of the absolute value circuit 23 is received by a comparator 38 which provides a "low" logic level when |l|≧l₄, where l₄ is a third predetermined quantity smaller than l₂, and provides a "high" logic level when |l|<l₄.

The output of the comparator 36 is received by the S input of an S-R flip-flop 35, which is set when a "high" logic level is received at the S input. The output of the comparator 37 is received by the R input of the flipflop 35, which is reset when a "high" logic level is received by the R input. The output of the scaling circuit 24 is received by a switch 30 along with the quantity h from the relative image displacement detection system. The switch 30 is controlled by the output Q of the flip-flop 35 to provide the quantity h at its output when Q is at a "low" logic level and to provide the quantity α|l| when Q is at a "high" logic level. The output of switch 30 is received by a switch 32 which is controlled by the output of a switch 39. The switch 32 provides the output of the switch 30 to one of its two output terminals OUT1 and OUT2 depending on the logic level of the output of the switch 39. As described above, in connection with FIG. 9, the quantities provided on the outputs OUT1 and OUT2 after appropriate conversion are used to control the servomotor which adjusts the focus of the imaging system.

The switch 39 receives the output of the comparator 21 and the signal g, and is controlled by the output Q of flip-flop 35 to provide the signal g at its output when Q is a "low" logic level and to provide the output of the comparator 21 when Q is a "high" logic level.

At the beginning of a focusing operation, the quantity l is such that |l|>l₃, and the flip-flop 35 is reset by the output of the comparator 37. Consequently, the switch 30 provides the quantity h to the switch 32, and the switch 39 provides the signal g to control the switch 32. Under these conditions, the focus adjustment of the imaging system is solely under the control of the quantities g and h of the relative image displacement detection system.

As the focus is adjusted, the quantity |l| becomes smaller, and when |l| becomes less than l₂, the flip-flop 35 is set by the output of the comparator 36. Thereafter, the switch 30 provides the quantity α|l| to the switch 32, and the switch 39 provides the output of the comparator 21 to control the switch 32. Under these conditions, focus adjustment of the imaging system continues solely under the control of the quantity l of the image contrast detection system. Automatic focusing apparatus using the above-described motor control circuits are disclosed and claimed in the afore-mentioned U.S. patent application Ser. No. 483,247.

It is understood that various alterations and modifications may be made to the disclosed embodiments by one skilled in the art without departing from the spirit and scope of the present invention. For example, other configurations of logical circuits will be known to one skilled in the art for performing substantially equivalent logical functions as the illustrative configurations described herein. Moreover, the logic circuitry of the FIGS. 6, 8, 9, and 10 may also be implemented in large part by an appropriately programmed processor rather than with special purpose hard-wired logic as illustrated.