Semiconductor decoding circuit
专利汇可以提供Semiconductor decoding circuit专利检索，专利查询，专利分析的服务。并且PURPOSE: To prevent the increment of an ON resistance of a semiconductor decoding circuit and to attain a high-speed operation by connecting a multi-stage NMOS transistor to a tree structure and increasing the gate width from the transistors closer to the output by an amount equivalent to one unit, two units, four units and so on of memory cell length.
CONSTITUTION: PMOS transistor parts P
1 WP
2 N
-1 obtained by connecting N units of PMOS transistors to which the reverse or non-reverse inputs of N inputs A'
1 WA'N in parallel to these inputs A'
1 WA'N respectively are provided together with NMOS transistor parts connected to a tree structure and set at the next stage of (2N
-1 ) units of PMOS transistor parts P
1 WP
2 N
-1 . The tree structure of the NMOS transistor part is formed by cascade connecting NMOS transistors in vertical stages up to the NMOS transistor of the final stage to which -A'N/A'N is supplied while decreasing the number of those NMOS transistors down to half like (2N
-1 ) units of NMOS transistors to which an input -A'
1 / A'
1 is applied and then (2N
-2 ) units of NMOS transistors to which an input -A'
2 /A'
2 is supplied.
COPYRIGHT: (C)1985,JPO&Japio，下面是Semiconductor decoding circuit专利的具体信息内容。
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