1. An error detecting code conversion network for converting any single one of a plurality of electronic input signals indicative of a fault, the input signals numerically ordered according to radix (M), to deliver electronic signals coded according to a radix (N), where (M) and (N) are integers and (M) is larger than (N), and for converting any two or more of the plurality of electronic input signals indicative of two or more concurrent faults into a unique combination of signals indicative of multiple concurrent faults comprising: a first digital logic means producing first electronic output signals coded according to the radix (N) in response to the electronic input signals numerically ordered according to the radix (M); b. a second digital logic means coupled with said first logic section and producing second electronic output signals in response to any substantially coincident combination of two or more of certain electronic input signals; storage means coupled to said second digital logic section for storing the second electronic output signals; and translating means coupled to said storage means and to said first and second digital logic means, said translating means responsive to said first logic means for translating the first electronic output signals from said first digital logic means into human observable signals, said translating means also responsive to said second digital logic means for translating the second electronic signals into human observable signals.

2. fourth lines connecting between said intermediate lines and said sensing network logic gating means, and

2. a single output line,

2. a plurality of output lines of number fewer than said first plurality of input lines transmitting respectively binary encoded signals in response to said decimally encoded signals,

2. a second plurality of binary-ordered input lines connected to said converter, with said second plurality being fewer in number than said first plurality of input lines; b. a digital logic network means connected with said converter for providing a first type error signal upon sensing an input signal on a single one of said first plurality of input lines, and providing a second type error signal upon sensing the coincident receipt of input signals on at least two of said plurality of input lines; and c. error store means for storing either of said first type or second type error signals.

3. a first level of logic gating means for receiving electrical signals on said plurality of input lines, and for partially converting said decimally encoded signals,

3. logic gating means connected between said second plurality of input lines and said single output line and producing a further signal on said single output line only upon sensing the simultaneous receipt of input signals on at least two of said second plurality of input lines; c. said second plurality of lines connecting said decimal to binary converter to said sensing logic network comprising;

3. fifth lines connecting between said plurality of output lines to said sensing network logic gating means.

4. a second level of logic gating means for producing binary encoded electrical output signals on said plurality of output lines,

4. An apparatus for producing a coded indication of which single incoming input line of a plurality of incoming input lines carries an error condition said apparatus also capable of responding to the receipt of concurrent plural error conditions for more than one of the incoming input lines and producing an unambiguous single or multiple error signal comprising: a. a code converting network for converting input signals of a numerical code having a radix (M) to deliver signals of a numerical code having a radix (N); b. a plurality of input lines coupled to said code converting network said input lines numerically ordered in accordance with a code having the radix (M), and a plurality of output lines coupled to said code converting network said output lines numerically ordered in accordance with a code having the radix (N); c. first digital logic means coupled to said numerically ordered input lines for producing a first signal with a numerical code of radix (M) when an error condition occurs in any single input line, said first signal being converted to a signal with a numerical code of radix (N) by said code converting network; d. second digital logic means coupled to said input and output lines for producing a second signaL on said output lines when a multiple substantially concurrent error condition occurs in two or more of said input lines; e. and translating means coupled to said output lines, said translating means responsive to said first digital logic means for translating the first converted signal with numerical code of radix (N) into human observable signals, said translating means also responsive to said second digital logic means for translating the second signal into human observable signals.

5. intermediate lines connecting said first level logic gating means to said second level logic gating means; b. a sensing logic network having;

7. An apparatus for differentiating between a single error condition and a multiple error condition comprising: a. a decimal-to-binary converter having;

8. An electrical encoding network comprising: a. a decimal-to-binary converter having: