1. In a code conversion process that utilizes a computer having a memory for encoding a succession of fixed-length input codes into an output bit stream composed of variable-length codes which represent the more frequently occurring input codes and fixedlength codes which are respectively identical with the less frequently occurring input codes, the steps of: a. storing in a first portion of said memory representations of the frequently occurring variable-length codes which may be included in said bit stream; b. storing in a second portion of said memory representations of the fixed-length codes which respectively correspond to said variable-length codes; c. comparing each successive one of said input codes with the fixed-length codes stored in said second memory portion; and d. executing one of the following actions in accordance with the result of each such comparison: d1. if an input code matches any of the fixed-length codes stored in said second memory portion, then causing the bits of the corresponding variable-length code stored in said first memory portion to be serially read out as elements of said output bit stream; or d2. if the input code does not match any of the fixed-length codes stored in said second memory portion, then serially reading out the bits of such input code as elements of said output bit stream.

2. In a code conversion process that utilizes a computer having a memory for generating fixed-length output codes in response to an input bit stream containing frequently occurring prefix-free variable-length codes mingled with infrequently occurring fixed-length codes, the steps of: a. storing in a first portion of said memory representations of the frequently occurring variable-length codes which may be included in said bit stream; b. storing in a second portion of said memory representations of the fixed-length codes which respectively correspond to said variable-length codes; c. comparing the bits of an input code with the variable-length codes stored in said first memory portion; and d. executing one of the following actions in accordance with the result of such comparison: d1. if said input code matches any of the variable-length codes stored in said first memory portion, then causing the corresponding fixed-length code in said second memory portion to be read therefrom as the output code; or d2. if said input code does not match any of the variable-length codes stored in said first memory portion, then causing the bits of said input code to be read out as elements of the output code.

2. if the accessed location is the one where said common code is stored, then performing a special encoding operation to generate an output code which consists of said common code combined with the respective input code.

3. In a code conversion process that utilizes a computer having a memory and a shift register for encoding a succession of fixed length input codes into an output bit stream composed partly of variable-length codes representing at least some of the more frequently occurring input codes and also including fixed-length codes identical with at least some of the less frequently occurring input codes, each of the fixed-length output codes being preceded in said bit stream by a special code, the steps of: a. storing in a first portion of said memory representations of the frequently occurring variable-length codes which may be included in said bit stream; b. storing in a second portion of said memory representations of the fixed-length codes which respectively correspond to said variable-length codes; c. storing in a third portion of said memory length indicators which respectively represent the numbers of bits contained in the variable-length codes that are stored in said first memory portion; d. storing in a fourth portion of said memory a representation of said special code; e. comparing each successIve one of said input codes with the fixed-length codes stored in said second memory portion; and f. executing one of the following actions in accordance with the result of each such comparison: f1. if an input code matches any of the fixed-length codes stored in said second memory portion, then causing the corresponding variable-length code in said first memory portion to be entered into said register, and shifting the contents of said register through the number of bit storing positions represented by the corresponding length indicator stored in said third memory portion for reading out therefrom the bits of the variable-length code that have been entered into said register as elements of said output bit stream; or f2. if the input code does not match any of the fixed-length codes stored in said second memory portion, then serially reading out the bits of the special code stored in said fourth memory portion followed by the bits of said input code as elements of said output bit stream.

4. In a code conversion process that utilizes a computer having a memory and a shift register for generating fixed-length output codes in response to an input bit stream containing frequently occurring prefix-free variable-length codes mingled with infrequently occurring fixed-length codes, each of the fixed-length input codes being preceded in said bit stream by a special code of predetermined length, the steps of: a. storing in a first portion of said memory representations of the frequently occurring variable-length codes which may be included in said bit stream; b. storing in a second portion of said memory representations of the fixed-length codes which respectively correspond to said variable-length codes; c. storing in a third portion of said memory length indicators which respectively represent the numbers of bits contained in the variable-length codes that are stored in said first memory portion; d. storing in a fourth portion of said memory a length indicator representing the number of bits in said special code; e. storing in successive orders of said shift register the bits of any selected one of the codes in said bit stream followed by any succeeding bits which may be in said stream, up to the capacity of said register, placing the lowest-order bit of said one code initially in the lowest-order bit storing position of said register; f. comparing the code bits stored in said shift register with the variable-length codes stored in said first memory portion; and g. executing one of the following actions in accordance with the result of such comparison: g1. if said one code matches any of the variable-length codes stored in said first memory portion, then causing the corresponding fixed-length code in said second memory portion to be read therefrom as the output code, and shifting the contents of said register through the number of bit storing positions represented by the corresponding length indicator stored in said third memory portion; or g2. if said one code does not match any of the variable-length codes stored in said first memory portion, then shifting the contents of said register through the number of bit storing positions represented by the special code length indicator stored in said fourth memory portion, reading from the resultant setting of said register those bits which occupy positions corresponding to the various orders of a fixed-length code as elements of the output code, and shifting the contents of said register by a like number of bit positions.

5. A code conversion process utilizing a computer having a memory for encoding a succession of fixed-length input codes into output codes which have variable lengths for the more frequently occurring input codes and fixed lengths for the less frequently occurring input codes, said process comprising the following steps: a. storing representations of said variable-length codes at locations in said memory which may be acceSsed respectively by the more frequently occurring input codes; b. storing at another location, which may be accessed by any of the less frequently occurring input codes, a common code which collectively identifies all of such input codes; c. accessing the respective storage location which is designated by each of the successive input codes; and d. performing one of the following steps according to the particular storage location which is being accessed in each instance: d1. if the accessed location is one at which a variable-length code is stored, then generating an output code that is identical with said variable-length code; or

6. A code conversion process utilizing a computer having a memory for decoding a succession of input codes into fixed-length output codes, where the more frequently occurring input codes are variable-length codes and the less frequently occurring input codes are combination codes each including a common code associated with an individual fixed-length code, said process comprising the following steps: a. storing in said memory, at locations therein which may be accessed respectively by said variable-length codes, representations of fixed-length codes respectively corresponding to said variable-length codes; b. storing at another location, which may be accessed by said common code, control information indicative of a special decoding operation; c. accessing the respective storage location which is designated by each of the successive input codes; and d. performing one of the following steps according to the particular storage location which is being accessed in each instance: d1. if the accessed location is one which is designated by a variable-length code, then generating an output code that is identical with the fixed-length code stored at such location; or d2. if the accessed location is the one designated by said common code, then performing a special decoding operation to generate an output code which is identical with the fixed-length code included within the respective input code.

7. An associative memory apparatus for use as an encoder-decoder to effect conversions between frequently occurring fixed-length codes and corresponding variable-length prefix-free codes without effecting such conversions of the less frequently occurring fixed-length codes, said apparatus comprising: a. rows of memory cells for storing a plurality of words, each word containing a respective one of the frequently occurring variable-length codes, a corresponding one of the frequently occurring fixed-length codes, and a length indicator which denotes the number of significant bits in the corresponding variable-length code, the cells for storing the variable-length codes being three-state cells arranged in a code field which contains a uniform number of cells for each row, each three-state cell being capable of assuming a significant binary 1 or 0 state or a ''''don''t care'''' state wherein the bit which it stores is not significant; b. argument storing means having a portion effective when said apparatus is functioning as a decoder to store strings of bits contained in a series of input codes which may include both variable-length and fixed-length codes, and having a portion effective when said apparatus is functioning as an encoder to store the bits of a fixed-length code which is to be encoded, the portion of said argument storing means which stores input codes during decoding operations being selectively operable to shift the bits stored therein progressively through successive orders; c. data storing means having a portion effective when said apparatus is functioning as an encoder to store bits which are read from cells in the mEmory field storing the variable-length codes and having a portion effective when said apparatus is functioning as a decoder to store bits read from cells in the memory field storing the fixed-length codes, and also having a length counter for storing length indicators read from the related memory cells during both encoding and decoding operations, the portion of said data storing means which stores variable-length output codes during encoding operations being selectively operable to shift the bits stored therein progressively through successive orders; d. encoding control means including the following devices: d1. a supervisory device responsive to the presence or absence of a match between the fixed-length code in said argument storing means and any of the fixed-length codes corresponding to variable-length codes stored in said memory cells to signal either a normal or a special encoding operation in accordance therewith; d2. normal encoding control devices which are effective whenever said supervisory device signals a normal encoding operation for causing code bits to be read from the matching row of said variable-length code storing field into said data storing means and for thereafter causing such bits to be shifted out of said data storing means in accordance with the length indicator stored in said length counter; and d3. special encoding control devices effective whenever said supervisory device signals a special encoding operation for causing a special code to be entered into said data storing means and for thereafter causing an output code to be read in part from the encoding portion of said data storing means and in part from the encoding portion of said argument storing means, thereby producing a composite output code consisting of the input fixed-length code preceded by said special code; and e. decoding control means including the following devices: e1. a supervisory device responsive to the presence or absence of a match between the contents of said argument storing means and any of the variable-length code words stored in said memory cells to signal either a normal or a special decoding operation in accordance therewith; e2. normal decoding control devices which are effective whenever said supervisory device signals a normal decoding operation for causing a fixed-length code to be read from said data storing means and concurrently causing a new variable-length code to be shifted into said argument storing means in accordance with the length indicator stored in said length counter; and e3. special decoding control devices which are effective whenever said supervisory device signals a special decoding operation for causing the special code portion of the composite input code to be shifted out of said argument storing means and for thereafter causing the succeeding fixed-length code portion of said composite code to be read from said argument storing means as the output code.

8. An associative memory apparatus for use as an encoder to effect conversions between frequently occurring fixed-length codes and corresponding variable-length prefix-free codes without effecting such conversions of the less frequently occurring fixed-length codes, aid apparatus comprising: a. rows of memory cells for storing a plurality of words, each word containing a respective one of the frequently occurring variable-length codes, a corresponding one of the frequently occurring fixed-length codes, and a length indicator which denotes the number of significant bits in the corresponding variable-length code, the cells for storing the variable-length codes being three-state cells arranged in a code field which contains a uniform number of cells for each row, each three-state cell being capable of assuming a significant binary 1 or 0 state or a ''''don''t care'''' state wherein the bit which it stores is not significant; b. an argument register for storing the bits of a fixed-length code which is to be encoded; c. a data register for storing bits which are read from cells in the memory field storing the variable-length codes and including a length counter for storing length indicators read from the related memory cells during encoding operations, said data register being selectively operable to shift the variable-length code bits stored therein progressively through successive orders; and d. encoding control means including the following devices: d1. a supervisory device responsive to the presence or absence of a match between the fixed-length code in said argument register and any of the fixed-length codes corresponding to variable-length codes stored in said memory cells to signal either a normal or a special encoding operation in accordance therewith; d2. normal encoding control devices which are effective whenever said supervisory device signals a normal encoding operation for causing code bits to be read from the matching row of said variable-length code storing field into said data register and for thereafter causing such bits shifted out of said data register in accordance with the length indicator stored in said length counter; and d3. special encoding control devices effective whenever said supervisory device signals a special encoding operation for causing a special code to be entered into said data register and for thereafter causing an output code to be read in part from the encoding portion of said data register and in part from the encoding portion of said argument storing means, thereby producing a composite output code consisting of the input fixed-length code preceded by said special code.

9. An associative memory apparatus for use in decoding an input bit stream which contains frequently occurring variable-length prefix-free codes and infrequently occurring composite codes each consisting of a fixed-length code preceded by a special code of predetermined length, said apparatus comprising: a. rows of memory cells for storing a plurality of words, each word containing a respective one of the frequently occurring variable-length codes together with a corresponding one of the fixed-length codes and a length indicator which denotes the number of significant bits in the corresponding variable-length code, the cells for storing the variable-length codes being three-state cells arranged in a code field which contains a uniform number of cells for each row, each three-state cell being capable of assuming a significant binary 1 or 0 state or a ''''don''t care'''' state wherein the bit which it stores is not significant; b. an argument register for storing the bits of said input bit stream, said argument register being selectively operable to shift the bits stored therein progressively through successive orders; c. a data register for storing bits read from cells in the memory field storing the fixed-length codes, and including a length counter for storing length indicators read from the related memory cells; and d. decoding control means including the following devices: d1. a supervisory device responsive to the presence or absence of a match between the contents of said argument storing means and any of the variable-length code words stored in said memory cells to signal either a normal or a special decoding operation in accordance therewith; d2. normal decoding control devices which are effective whenever said supervisory device signals a normal decoding operation for causing a fixed-length code to be read from said data register and concurrently causing a new variable-length code to be shifted into said argument register in accordance with the length indicator stored in said length counter; and d3. special decoding control devices which are effective whenever said supervisory device signals a special decoding operation for causing the special code portion of the composite input code to be shifted out of said argument register and for Thereafter causing the succeeding fixed-length code portion of said composite code to be read from said argument register as the output code.