Error control encoding system, method and device

The present invention relates to an error control encoding method in effecting data communication via a fading channel dominated by burst errors in the data communication of moving body such as a(n) (auto)mobile and to a mobile data communication device employing said method according to claims 1 and 2, respectively.

Error correcting codes for automatically correcting digital information are essential to improvement of reliability of contemporary computer communication systems. The error correcting code is divided into, depending on correctable error patterns, an error correcting code suited to random errors and that suited to burst errors.

In a mobile communication system, a severely bad-conditioned transmission line such as a fading channel is dominated by a burst error. An interleaving system is known as such a system to correct the burst error, which is described in for example "Error correcting Codes Entering upon Extensive Use in Various Fields" by Tanaka, Nikkei electronics, 1975 12-15, p.p. 48 to 52. This employs powerful random error correcting codes for a communication channel dominated by a burst error, renders interleave to digital information for transmission, and transforms a burst error to a random error.

However, the interleaving system encounters trouble with a system severely in delay of time since it takes more time for decoding conducted on the basis of the interleave.

In addition, another error correcting system is known as an automatic repeat and request system (ARQ) as described in "Batch Troughput Efficiency of ADCCP/HDLC/SDLC Selective Reject Protocols" by Malcolm. C. Easton, IEEE, 1980, p.p. 187 to 195.

These systems,however,need several hundreds of bits of interleave for randomizing the signal concerned with the aid of the interleave since a mobile widely changes its moving speed from its standing to a speed of one hundred and several tens of kilometers per hour as well as its receiving level from about minus 100 dBm to about minus several tens of dBm, and results in undesirable prolonged delay of time. Thus, larger capacity of a random access memory (RAM) is required together with a measure for improving throughput efficiency deteriorated. The throughput efficiency deterioration is severe in particular communication only with use of a burst length error correcting code.

JP-A-52147905 and JP-A-5921149 disclose to change the block-length in response to the variation of circuit quality. However, as it is evident from JP-A-5921149, the mere changing of the blocklength does not necessarily lead to a changing of the framelength. In this Patent Application the framelength remains unchanged with only the number of frames per block being changed.

Further to this it is known from the older (within the meaning of Art. 54(3) EPC) European patent application EP-A-0188271 an error-correction method which supervises an error-rate of received data and adaptively changes an error correcting code. The older application suggests to put together a plurality of data frames of the input information data to a data block to provide encoded data, to decode the transmitted data, to detect the erroneous frames, to evaluate as the error rate of said decoded data the ratio of erroneous frames to all frames within one data block and to select a number indicative of the type of the error correcting code according to the ratio of erroneous frames. This older European patent application furthermore suggests to produce error information at least including error frame numbers, in the receiving part; and to return said error information to the transmitting part.

Contrary to this, according to the invention the frame length is dependent on a frame error rate so that a high frame error rate causes a shorter frame length.

In view of the drawbacks with the prior art error control encoding system, it is an object of the present invention to provide an error control encoding system less changed in throughput efficiency in a mobile communication system even if a mobile changes its moving speed from its standing to one hundred and several tens of kilometers. per hour or its receiving level from a lower value to several tens of dBm. The error control encoding system according to the present invention is adapted to detect any error involved in received data as a frame error rate in a data block or bit error rate in a data block when the receiving side receives the data transmitted from the transmitting side, and selects a frame length in response to the extent of the error rate for encoding and decoding the transmission data. The method underlying this system consists of the steps as claimed in claim 1.

For the error information in this method, there are instances where the number of error frames (i.e., frame error rate) received in a data block and a bit error rate received in one-block data are profitably employed.

In addition, a mobile data communication device according to the present invention consists of the features as claimed in claim 2.

The above and other objects, features and advantages of the present invention will become more apparent from the following description when taken in conjunction with the accompanying drawings in which a preferred embodiment of the present invention is shown by way of illustrative examples.

• FIG. 1 is block diagram illustrating a first embodiment of an error control encoding system according to the present invention,
• FIG. 2 is a flowchart illustrating operation of the block diagram of FIG. 1,
• FIG. 3 is a view illustrating transition among steps of frame lengths from L1 to L4,
• FIG. 4 is a view illustrating an exemplary transmission procedure with use of the embodiment of FIG. 1,
• FIG. 5 is a block diagram illustrating the interior of the encoder 2 shown in FIG. 1,
• FIG. 6 is a block diagram illustrating the interior of the decoder 6 shown in FIG. 1,
• FIG. 7 is a view illustrating throughput efficiency in the embodiment of the present invention,
• FIG. 8 is a block diagram illustrating a second embodiment of the error control encoding system according to the present invention, and
• FIG. 9 is a block diagram illustrating the arrangement of a burst length measuring part 6B in the embodiment of FIG. 8.

A first embodiment of an error control encoding system according to the present invention will be described with reference to Fig. 1 and Fig. 2. According to this embodiment, a received error frame is detected on the receiving side and an ACK(acknowledge)signal or an error frame number and an NAK(negative acknowledge)signal are transmitted back to the transmitting side for each data block. A frame error rate for each data block is evaluated in the transmitting side and frame length is altered in conformity with the evaluation for error frame retransmission and data transmission thereafter.

In Fig. 1, designated at 1 is a transmitting terminal, 2 is an encoder, 3 is a transmitter, 4 is a communication channel, 5 is a receiver, 6 is a decoder, 7 is a receiving terminal, 8 is an error frame number selecting means, 9 is an encoder, 10 is a transmitter, 11 is a communication channel, 12 is a receiver, 13 is a decoder, 14 is a frame length selecting part, 15 is in a frame length selecting device, and 16 is a frame length memory.

Operation of the error control encoding system of Fig. 1. Four kinds of lengths L1, L2, L3, and L4 (for example, the frame length L1 is assumed to be twice L2, L2 twice L3, and L3 twice L4) are employed as frame lengths in the encoder 2, and the data concerned is assumed to be encoded with the frame length L1 as initial setting.

The encoder 2 encodes the data with an error detecting code (for example, a cyclic code) frames it with the frame length L1, numbers each frame, and blocks it with a prescribed frame number (Fig. 2, box 22).

The encoded data is modulated through the transmitter 3 and transmitted to the communication channel 4 (Fig. 2, box 23). The communication channel 4 is a fading channel which produces a burst error on the modulated signal as the mobile travels and the modulated signal with the burst error is received by the receiving side. The receiving side demodulates the received signal through the receiver 5 (Fig. 2, box 24). Subsequently, the decoder 6 decodes the demodulated signal with use of the error correcting code or the error detecting code for detecting an erroneous frame, and data obtained from frames without any error is supplied to the receiving terminal 7 (Fig. 2, box 25).

The error frame number selecting means 8 supplies the erroneous frame number and the NAK signal to the encoder 9 for a block decoded by the decoder 6. The frame number is yielded by a counter,for example, (not shown) serving to count the frame number involved in one block. Moreover, the error frame number selecting means supplies an ACK signal to the encoder 9 for the correct frames. The encoder 9 encodes the frame number and NAK signal or ACK signal with use of a code having powerful error improving capability such as a majority logic code, and delivers them to the communication channel 11 via the transmitter 10 (Fig. 2, boxes 26, 27).

The error frame number and the NAK signal or the ACK signal are sent to a frame length selecting part 14 of the frame length selecting device 15 for each frame via the receiver 12 and the decoder 13 in conformity with arbitrarily set time-out needed to permit the ACK/NAK signal to be properly transmitted.

The frame length selecting part 14 decides on the ACK signal and the NAK signal and on selecting a frame length based on their states. For example, with the ACK signal or the NAK signal received in the order of the arriving frames, the frame length selecting part 14 decides at that time that a longer frame length should be selected provided all the frames involved in one block are the ACK signal, decides that a shorter frame length should be selected provided a rate of the ACK signal involved in all the frames is less than a predetermined value, and, furthermore, decides that the present frame length should be maintained. These procedures are repeated until no more frame error is found (Fig. 2, boxes 30, 31, 32). The decided results serve as a signal for selecting any of the frame lengths L1, L2, L3, and L4 in the frame length memory 16. The selection is effected by allowing a controller (not shown) to receive the concerning signal.

For example, assuming that any data is first sent with the frame length L1, provided that a frame error rate is less than a predetermined value, the frame length is changed to the L2 which is shorter than the L1. The encoder 2 for which the frame length L2 in the frame length memory 16 is designated effects data retransmission for a frame having the frame member supplied with the NAK signal, with a new frame length L2 (Fig. 2, boxes 33, 34). Then provided the frame member indicative of the NAK signal is less than the number of frames consituting a block, new data is assigned to the remaining frames based on the frame length L2. Provided that data retransmission with a further shorter frame length is required in case of the transmission with the frame length L2, a further shorter frame length L3 is selected.

If the ACK signal for all the frames from the receiving side is transmitted to the transmitting side, the frame length selecting part 14 selects a longer frame length and delivers input data with its frame length. Details of the retransmission given thereafter will be neglected here.

Referring to Fig. 3, let us describe transition among the steps from the frame length L1 to L4. An initial state is started from a state 1. The state changes toward an arrow 301 based on information on the receiving side indicative of that a frame error rate in one block exceeds a predetermined value. Provided that it is less than the predetermined value, it keeps the same state in accordance with an arrow 303. Where the state changes from the state 1 to the state 2 and with bad channel conditions a frame error rate in one block exceeds a predetermined value, the state changes to a state 3 in accordance with an arrow 304. When the channel conditions get better and a frame error rate is less than a prescribed specific value, the state changes to the state 1 in accordance with arrow 302. When frame error rate ranges within a predetermined specific value, the state keeps the same state in accordance with an arrow 306. Transitions to states 3 and 4 are effected likewise. It is also possible to encode any data with an error correcting code on the receiving side for a frame length of each state. For instance when the state is initiated from the state 1, the state changes to the state 2 in accordance with the arrow 301 based on information on the receiving side indicative of that a frame error rate in a block is evaluated from data yielded by decoding a predetermined error correcting code and it exceeds a predetermined specific value because all of existent errors are impossible to be corrected. Provided all of the existent errors can be sufficiently corrected with use of the error correcting code, the state keeps the same state in accordance with the arrow 303. The state changes to the state 3 in accordance with the arrow 304 provided that the errors are incorrectable with the error correcting code in the state 2.

Provided that the existent error can be sufficiently corrected with the error correcting code in the state 2 and the frame error rate is less than a predetermined specific value, the state changes to the original state 1 in accordance with the arrow 302. In addition, when the frame error rate lies within a predetermined specific value, the state keeps the same state in accordance with an arrow 306. Also for the states 3 and 4, the state changes in the same manner. Error correcting codes employed here may differ from each other in each state of Fig. 3. Namely, any error correcting code may be selected and combined, for example, only an automatic repeat request system may be applicable in the state 1, a BCH (Bose, Chaudhuri, and Hocquenghem) code applicable in the state 2, and a majoring logic code in the state 4.

It can be easily understood that, although the above description is for the automatic repeat request ARQ, it is applicable also for a block ARQ and a basic ARQ. The basic ARQ, if there is any NAK signal, retransmits all frames in block and thus transmits back also a block number together with the NAK signal. In addition, although the transition from the i to i + 1 or i - 1 was described as shown in Fig. 3, transmission from i to i + 2 and i - 2, and i + 3 and i - 3 are also possible depending on the channel conditions.

As shown in Fig. 4 illustrating an example of a transmission procedure, the transmitting side adds an error correcting code to data, frames it with an initial setting frame length L2, and transmits it to the receiving side. The receiving side effects error detection and transmits back to the transmitting side the member of an erroneous frame together with a NAK signal after applying the error detecting code described above. With any error produced here, the transmitting side sends no data to the receiving side, and so the receiving side again issues the same NAK signal.

Although in the present embodiment the transmitting side is adapted to simply transmit data and the receiving side adapted to simply receive data to serve as half-duplex transmission, it is evident that the present invention is applicable as full duplex since one terminal has both transmitting and receiving parts in general.

Referring to Fig. 5, arrangement of an encoder 2 shown in Fig. 1 is illustrated, which operates with a diffusion code. The encoder, as is well known, consists of shift registers and exclusive ORs (mod 2). A circuit in the encoder 2 is uniquely determined with a generator polynomial. Accordingly, the encoder 2, with the diffusion code described above, is arranged as shown in Fig. 5. As shown in Fig. 5, designated at 50 is an encoder input terminal, 51 is a b + 1 stage shift register, 53 and 55, respectively are b - stage shift registers,52, 54, and 56, respectively are exclusive ORs, 57 is a switch for switching between an information mode and a check mode, and 58 is an encoder output terminal. Any information bit supplied to the encoder input terminal 50 is delivered on one hand to the information/check mode switching switch 57, and on the other hand to an input of the b + 1 stage shift regester 51. Thereafter, the information bit is delayed through the exclusive ORs and b - stage shift registers, and a check bit is finally delivered from an output of the exclusive OR 56. These information and check bits are alternately supplied to the encoder output terminal 58 through operation of the information/check switching switch 57, and,furthermore, delivered to the transmitter 3.

Moreover, the decoder 6 of Fig. 1 comprises a circuit of Fig. 6. The decoder 6 of Fig. 1 employs the diffusion code and decodes any data with a majority logic of a convolution code. As shown in this figure, 62 and 63 are b - stage shift registers, 64 is a b + 1 stage shift register, and 65, 66, 67, 68 and 69, respectively are exclusive ORs. Any information bit is supplied to the b - stage shift register 62 through switch 61 for alternately switching between information and check bits, and delayed via the b+1 stage shift register 64. In addition, any check bit is supplied from an output of the exclusive OR 66, which check bit is yielded based on received information bit. The check bit is operated with a check bit supplied via the information/check switching switch 61 by an exclusive OR 65. An output from the exclusive OR 65 is supplied on one hand to the exclusive OR 71 and error-detected through the exclusive ORs 71, 74, 77, and 79, the single-stage shift register 72, the b - stage shift registers 73 and 76, the b + 1 stage shift register 78, and the majority element 80. As a result, the output of the majority element 80 provides an error detecting signal for the information bit while the output of the exclusive OR 79 provides that for the check bit. In addition, an output from the majority element 80 is supplied on one hand to the exclusive OR 69 for effecting error correction for the information bit supplied from the b + 1 stage shift register 64, and a data output signal is delivered to the receiving terminal 7 via the data output terminal 70 of the decoder, the output from the majority element 80, on the other hand,is supplied to an information/check switching switch 81. Moreover, an output from the exclusive OR 79 supplied to the information/check switching switch 81 alternately switches between the error detection signal for the information bit and that for the check bit and outputs any one of them. As a result, the error detection signal is delivered to the error frame number selecting means 8 via the error detection signal output terminal 82.

Referring to Fig. 7 illustrating an effect of the present embodiment, a transmission efficiency of any data is shown with respect to frame lengths with received powers being taken as a parameter when a mobile in travelling at 55 km/h receives the data.

As shown in Fig. 7, with the received power being higher, the longer the frame length, the higher the transmission efficiency, while with the received power being lower, the frame length must be reduced for raising the transmission efficiency. An error produced in the case is a burst-natured one produced due to fading, etc. Consequently, when a mobile moves faster with received power reduced whereby frequent burst errors are produced with a guard length reduced, a reduced frame length enables relatively high efficiency transmission to be achieved. When the mobile stops and performs data transmission, no burst error is produced to permit high efficiency transmission to be assured provided the frame length is increased.

Therefore, when the transmitting side receives more NAK signals than those under prescribed conditions and the transmitting side retransmits the data concerned while levelling down a frame length previously prepared by one step at a time, it can transmit the data with the optimum frame length in response to the conditions of a fading channel. Moreover, since any frame length is determined for each block, the present system can follow up abrupt changes of the conditions of the fading channel. Furthermore, when the number of frames received with any NAK signal and needed to be retransmitted is more than half the number of frames transmitted, the data transmission can be effectively achieved provided that the data is retransmitted with a frame length levelled down by two steps from a previously prepared frame length.

A second embodiment of an error control encoding system according to the present invention will be described with reference to Fig. 8. Although the first embodiment described above was adapted to change a frame length based on an error frame rate involved in a block, the present second embodiment estimates a bit error rate of received data for each frame for comparing the estimated value with a specified transmission quality, i.e., a channel error rate, and thereby decides whether or not the frame concerned is an erroneous one for each frame and changes frame length based on a rate of the number of the resultant error frames involved in a block.

As shown in Fig. 8, designated at 6 is a decoder, 6A is a decoding part, 6B is a burst length measuring part, and the other symbols are the same as those showing in Fig. 1. the transmitted data provided by the transmitting terminal 1 is delivered to the encoder 2. The encoder 2 encodes the data for frame unit with use of the frame length L1, numbers the length for each frame, and blocks a plurality of the frames. (The present embodiment is assumed to employ a convolutional code as the error correcting code.)

The blocked encoded data is modulated through the transmitter 3 and provided to the communication channel 4. The kind L1 of the frame length is also delivered as data. In the receiving side the received encoded data demodulates through the receiver 5 and thereafter decodes in the decoder 6. The decoding part 6A decodes the data with use of a prescribed error correcting code or an error detecting code and sends normal data to the receiving terminal 7. Hereupon, the burst length measuring part 6B receives the error detecting signal delivered from the decoding part 6A and measures the length of a burst error and the length of an error-free interval for each frame for converting them into a channel bit error rate. Hereupon, when transmission quality is intended for example to be less than 10⁻⁶ in terms of the channel error rate, the burst length measuring part 6B decides that the measured frame is correct when its channel error rate is less than 10⁻⁶ while incorrect if more than 10⁻⁶.

Subsequently, a data-making device 17 converts the frame number decided to be erroneous to a data format suited to the present processing, and the encoder 9 encodes this data and provides it to the transmitter 10. The encoder 9 executed the encoding in conformity with a predetermined encoding system. The encoded data is modulated in the transmitter 10 and delivered to the communication channel 11.

The transmitting side demodulates received modulated data through the receiver 12 and decodes the encoded data in the decoder 13 for detecting the error frame number. Although the decoded data is retransmitted from the receiving side to the transmitting side, details thereof will be neglected here.

In succession, the frame length selecting part 14 evaluates a rate of the error frame number to the number of all frames previously transmitted and selects a frame length corresponding to this rate from the frame length memory 16. The selector of the frame concerned is conducted in the same manner as that described in Fig. 2 and 3. Any frame corresponding to a frame number erroneously received by the receiving side is encoded with a selected frame length, modulated, and retransmitted to the receiving side via the transmitter 3. Thereupon, a kind of a newly selected frame length is also transmitted from the transmitting side to the receiving side. Hereby, the decoding part 6A of the receiving side can perform decoding corresponding to the frame length. After that, although the subsequent block data from the transmitting terminal 1 is transmitted with the newly selected frame length, the frame length is thereafter changed corresponding to a frame error rate for each block.

Referring to Fig. 9 illustrating the interior of the burst length measuring part 6B measures the length of a burst error and the length of an error free interval from an error detecting signal provided by the decoding part 6A.

As shown in the same figure, designated at 90 is an error detecting signal input terminal, 91 is a receiving clock input terminal, 92 and 104, respectively are flip-flops, 94 and 105, respectively are counters. 95, 96, 98, and 107, respectively are latches,97 is a burst error length output terminal, 106 is a decoder, 108 is an error-free interval length output terminal, 93, 100, 102, respectively are AND gates, and 99, 101, 103, respectively are inverters.

With a burst error being existent on the communication channel 4, the flip-flop 92 is set by a first error of an error detecting signal supplied by the decoding part 6A via the error detecting signal terminal 90, and an output from the flip-flop is supplied to the counter via the AND gate 93. The counter 94 is kept in the latch 95 every time any burst error is produced. On the other hand, when there is no burst error, a clock signal is provided to the counter 105 via the AND gate 102 and the inverter 103. The counter 105 counts the length of the state without any burst error. When the counted value by the counter 105 reaches a burst limit, this is detected by the decoder 106. As result, an output from the decoder 106 is provided to the clock input of the latch 96 and the burst error length is delivered from the latch 96. In addition, the output from the decoder 106 is supplied to the flip-flop 92 and a reset terminal (RESET) of the counter 94 to reset them. The length of the error-free interval in counting in the counter 105 is delivered from the latch 107 owing to a signal provided via the latch 98 and the flip-flop 104 by a succeeding error. As a result, the burst error length and the error-free interval length, respectively outputs via the burst error length output terminal 97 and the error-free interval length output terminal 108 disposed in the burst length measuring part, and is finally delivered to the outside via the burst length output terminal 18 and the error-free length output terminal 19 shown in Fig. 8.