Test method for viterbi decoder |
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| 申请号 | JP24066785 | 申请日 | 1985-10-29 | 公开(公告)号 | JPS62101128A | 公开(公告)日 | 1987-05-11 |
| 申请人 | Fujitsu Ltd; | 发明人 | SHIMODA KANEYASU; YAMASHITA ATSUSHI; KATO TADAYOSHI; | ||||
| 摘要 | PURPOSE: To test the operation of each section separately respectively by applying an input signal for a test directly corresponding a distributor, an ACS circuit and a path memory constituting a viterbi decoder, leading and collating the output signals. CONSTITUTION: The distributor 1 calculates a branch metric from an input signal such as a demodulation signal fed to a terminal (a), its output signal is fed to selectors 4, 6 and a selection output signal of the selector 4 is fed to the ACS circuit 2. The ACS includes an adder, a comparator and a selector, the adder adds a branch metric and a path metric, the pathmetrics being the outputs of the addition are compared by the comparator, and the most likelihood of the result of comparison is outputted while being selected by the selector. The path memory 3 consists of lots of cells storing the history of the most likelihood path, is reset by a reset signal from a terminal (c) and brought into an initial state. COPYRIGHT: (C)1987,JPO&Japio |
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